From patchwork Fri Feb 9 16:58:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 127870 Delivered-To: patches@linaro.org Received: by 10.46.124.24 with SMTP id x24csp802185ljc; Fri, 9 Feb 2018 08:58:17 -0800 (PST) X-Google-Smtp-Source: AH8x226Droidv7LVyA8EYLjwkGgYU8UdS35c/wqfLTaaeoP9Lsnbf0Wm36ek7TLBMDtOgkAXMI+F X-Received: by 10.98.190.11 with SMTP id l11mr3534276pff.32.1518195497456; Fri, 09 Feb 2018 08:58:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518195497; cv=none; d=google.com; s=arc-20160816; b=LkBI5djpkncIty3nOBQqWRXgy82XJMJD4w+3pVq/YTubZttsZMOyISAJm4nZKcv0wJ Pyck3/nC4Kln78Ll2YpTHtnkL+UZdzKHzlGJX6S86SjPiBrxTx578/xDplphwzVjNlE5 vSLmZDodEeOMA6oAVmtAHc2bZoOjQqFZZBi72WByFNMXmbIO/z7tZ4hgfOyTQ10YjALT 7aUpfaWc+pGLeDrZRVKjJT0l0EJa2ogBBfwFMNg7EU9lJnZKy44YozzMxasI77Nq8HQi t4LGC97aw9tHKCAHgVSzk4B51GOpDAD1aX+M8nR5o+uBLraJCVGkCqdwA7N4Je/L0ixN +38A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=LI7RuXzMx0H/AOlskAaw4Z2larWm5hSq8EQxepAoQMQ=; b=I6r+Y7fDRroZ8H4x/GnSTWH2WvnI6GR9UMieJ+T0xOM2Rc3qdKEdUcMeBxxZLqqM45 a2lUSIY4kypzYaXP2I5ZBsT2Qm3aP3MkWijVMzHDH3Boh/Q980WrUfNmFlwX0B4YiAEn 20V6TS+bRZsnE4uoU9h9kszuJtsN7v0uUcOet3ceu8tG4SEzY8NiLD17FAnLAyF55zXg cJdtN9lQJQ7UxuB9W/Lb+qioVdRrinMjJSQLPZY1a8boJ6MP56m2+82cMKdobjEwpIVg VXz1kOkxrxN/YJ71DKXLKA2ap8El0Io10/+mFhWY3KoNxM86YA/6EKHs5qcfV6euL168 Su/w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id j8-v6si1748726plk.87.2018.02.09.08.58.16 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 09 Feb 2018 08:58:17 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ekC04-0002zI-Np; Fri, 09 Feb 2018 16:58:12 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH v2 01/11] hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC Date: Fri, 9 Feb 2018 16:58:00 +0000 Message-Id: <20180209165810.6668-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180209165810.6668-1-peter.maydell@linaro.org> References: <20180209165810.6668-1-peter.maydell@linaro.org> MIME-Version: 1.0 Instead of hardcoding the values of M profile ID registers in the NVIC, use the fields in the CPU struct. This will allow us to give different M profile CPU types different ID register values. This commit includes the addition of the missing ID_ISAR5, which exists as RES0 in both v7M and v8M. (The values of the ID registers might be wrong for the M4 -- this commit leaves the behaviour there unchanged.) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- hw/intc/armv7m_nvic.c | 30 ++++++++++++++++-------------- target/arm/cpu.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+), 14 deletions(-) -- 2.16.1 Reviewed-by: Richard Henderson diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 360889d30b..63da0fee34 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -990,31 +990,33 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) "Aux Fault status registers unimplemented\n"); return 0; case 0xd40: /* PFR0. */ - return 0x00000030; - case 0xd44: /* PRF1. */ - return 0x00000200; + return cpu->id_pfr0; + case 0xd44: /* PFR1. */ + return cpu->id_pfr1; case 0xd48: /* DFR0. */ - return 0x00100000; + return cpu->id_dfr0; case 0xd4c: /* AFR0. */ - return 0x00000000; + return cpu->id_afr0; case 0xd50: /* MMFR0. */ - return 0x00000030; + return cpu->id_mmfr0; case 0xd54: /* MMFR1. */ - return 0x00000000; + return cpu->id_mmfr1; case 0xd58: /* MMFR2. */ - return 0x00000000; + return cpu->id_mmfr2; case 0xd5c: /* MMFR3. */ - return 0x00000000; + return cpu->id_mmfr3; case 0xd60: /* ISAR0. */ - return 0x01141110; + return cpu->id_isar0; case 0xd64: /* ISAR1. */ - return 0x02111000; + return cpu->id_isar1; case 0xd68: /* ISAR2. */ - return 0x21112231; + return cpu->id_isar2; case 0xd6c: /* ISAR3. */ - return 0x01111110; + return cpu->id_isar3; case 0xd70: /* ISAR4. */ - return 0x01310102; + return cpu->id_isar4; + case 0xd74: /* ISAR5. */ + return cpu->id_isar5; /* TODO: Implement debug registers. */ case 0xd90: /* MPU_TYPE */ /* Unified MPU; if the MPU is not present this value is zero */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 89ccdeae12..d796085be9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1146,6 +1146,20 @@ static void cortex_m3_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M); cpu->midr = 0x410fc231; cpu->pmsav7_dregion = 8; + cpu->id_pfr0 = 0x00000030; + cpu->id_pfr1 = 0x00000200; + cpu->id_dfr0 = 0x00100000; + cpu->id_afr0 = 0x00000000; + cpu->id_mmfr0 = 0x00000030; + cpu->id_mmfr1 = 0x00000000; + cpu->id_mmfr2 = 0x00000000; + cpu->id_mmfr3 = 0x00000000; + cpu->id_isar0 = 0x01141110; + cpu->id_isar1 = 0x02111000; + cpu->id_isar2 = 0x21112231; + cpu->id_isar3 = 0x01111110; + cpu->id_isar4 = 0x01310102; + cpu->id_isar5 = 0x00000000; } static void cortex_m4_initfn(Object *obj) @@ -1157,6 +1171,20 @@ static void cortex_m4_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); cpu->midr = 0x410fc240; /* r0p0 */ cpu->pmsav7_dregion = 8; + cpu->id_pfr0 = 0x00000030; + cpu->id_pfr1 = 0x00000200; + cpu->id_dfr0 = 0x00100000; + cpu->id_afr0 = 0x00000000; + cpu->id_mmfr0 = 0x00000030; + cpu->id_mmfr1 = 0x00000000; + cpu->id_mmfr2 = 0x00000000; + cpu->id_mmfr3 = 0x00000000; + cpu->id_isar0 = 0x01141110; + cpu->id_isar1 = 0x02111000; + cpu->id_isar2 = 0x21112231; + cpu->id_isar3 = 0x01111110; + cpu->id_isar4 = 0x01310102; + cpu->id_isar5 = 0x00000000; } static void arm_v7m_class_init(ObjectClass *oc, void *data) From patchwork Fri Feb 9 16:58:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 127865 Delivered-To: patches@linaro.org Received: by 10.46.124.24 with SMTP id x24csp802134ljc; Fri, 9 Feb 2018 08:58:14 -0800 (PST) X-Google-Smtp-Source: AH8x224F4YPXQcwNJKjydMpYHZFcGXVU5+FugtN5UHHiS3CmD0RSWbNUO0HR3Rwu28X6ghSEOUF/ X-Received: by 10.28.194.137 with SMTP id s131mr2986030wmf.3.1518195493925; Fri, 09 Feb 2018 08:58:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518195493; cv=none; d=google.com; s=arc-20160816; b=HrP8N1LqzVjdb/9yvP2JjnaiI0F3TIlGuPl4k4C22fDTdB12U0IvCO4c1Khn5Li3Xd H3GUkmj9ysNYCtB+bfphJbnDM3+OEj7ja1tQNW5B4WcHMCuV5QmUt08DjwhwSG14xgMj WNLeO2Pcpp6deuAltOcBOJ0Fp5BVF5EtcLKarI0jCVgJyQcgKJHpZVx+w6GCIPRZhvd2 zSB246BmJdSjuD+AT+Oy9Zd9XkSws9x8X97d1Q4+1Aw93x9lpY0qrM19nmxVxU9HRcDa tv354r8DQb9WAv/aWsD8t0sntK++9z+JGgdrUQDB70EUmmWYe2U3jHWuSdtCJJboqf+x kWLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=FUh6YGRZJt0fIcLf6srobD9JR+wnm0STumkuBDvc77g=; b=d8brcW9dMEtPk22nomcjBUYp74H2VGufUg70kVfFLmQZhiji10VYDfBmJ+LF8SxXWu XMUJycvQorntjHJJQmxlv3YUvk1uEZUQmrf9dQYDlUOjcIMDvg8lFnkEyAPgpNC0evB2 e6n3253ByzMR8lEvRfnXrGn9s8CwiGsLIgVHvLvhWH5MTp6Y/H6OYyQEvf4qTrroY4Pi sQRXGGdlET9FXGasVVb9Xla5vwT2M8c0yO8GiYEXXG0jm1PBmdm3CkV/sk87U0YWtLC4 SXGZrvH03RkIHqvHJ1FLaq5nu18mZrbaXp1KZquQSxrBkbsEcCL4rl0A3o0pH2353Jy7 tzRA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id v62si1811102wmd.208.2018.02.09.08.58.13 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 09 Feb 2018 08:58:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ekC05-0002zZ-El; Fri, 09 Feb 2018 16:58:13 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH v2 02/11] hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling Date: Fri, 9 Feb 2018 16:58:01 +0000 Message-Id: <20180209165810.6668-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180209165810.6668-1-peter.maydell@linaro.org> References: <20180209165810.6668-1-peter.maydell@linaro.org> The PENDNMISET/CLR bits in the ICSR should be RAZ/WI from NonSecure state if the AIRCR.BFHFNMINS bit is zero. We had misimplemented this as making the bits RAZ/WI from both Secure and NonSecure states. Fix this bug by checking attrs.secure so that Secure code can pend and unpend NMIs. Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.16.1 Reviewed-by: Richard Henderson diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 63da0fee34..06b9598fbe 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -830,8 +830,8 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) } } /* NMIPENDSET */ - if ((cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) && - s->vectors[ARMV7M_EXCP_NMI].pending) { + if ((attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) + && s->vectors[ARMV7M_EXCP_NMI].pending) { val |= (1 << 31); } /* ISRPREEMPT: RES0 when halting debug not implemented */ @@ -1193,7 +1193,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, break; } case 0xd04: /* Interrupt Control State (ICSR) */ - if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { + if (attrs.secure || cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { if (value & (1 << 31)) { armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false); } else if (value & (1 << 30) && From patchwork Fri Feb 9 16:58:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 127866 Delivered-To: patches@linaro.org Received: by 10.46.124.24 with SMTP id x24csp802141ljc; Fri, 9 Feb 2018 08:58:14 -0800 (PST) X-Google-Smtp-Source: AH8x225sjEuCMCf5p/Z+P1veVd2T3RXa68jX9XIk33SiUgTNoq8HN+igNu885ZJ9/ZIu1Wd0zBl2 X-Received: by 10.28.10.6 with SMTP id 6mr2535007wmk.1.1518195494576; Fri, 09 Feb 2018 08:58:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518195494; cv=none; d=google.com; s=arc-20160816; b=sFa2cEb581T5wf4y2yd37Jenpa+tV3NCftsfSa53+uiWTmh98z0hzaHP0Q9nROo4j8 yArFEhZk421YvMW5PB9n1jFMhfUKEzIx9Vl4BdK0iqWEuESfjrZHnAzsUjcEWypTsrHL UideiR5AMrrKtqsxpeTkSDmuHwfN/QgPJk7AzggURiSYYSHnvncVqJbo5bi9oEJItEBk D2pRV6rgjuvzfIPRSW8YrfKg8mysgp5pmGCOn/nz8F7higPybqjDRbq6ZRx63l3V+Ivc gC5kPehfywLOuXlRW7BNJ94KujKUsvCVnNmhVF+QlSUT7vaUxPr+Aienx/Rmoo3ett6n fowQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=ryLvpalX9lQiwK3dkujoCkEwiM9hw3XksDW0xnO8TUk=; b=gYoA6gscxVhUNQHdLV5PBsmCZ7241oS2MxsrCQ8ihWnYSDgIuwPilDIQZADy3d+tVd 0Umv2aVbahURRGqvybJmzNNPGp6D96vQ7lXrXYyGVRKUDlitDG5bTi/yTu8ww9ri/cF2 UPydONBLHKuGvuSMbon4nKPW4ZSpfHOraRxEBFI32xNsPv2wOr79TpictSgCteui0O3l FDLLY7AwULN8rl9P/rKiI0m26YmogqV+RZYfv9IYNjC3Owpb8CJDscd0bcbHWJD7bkvG oJHMMV0R5QRgQ5WDglJ3HhJsduRtEIvwDyvdrDyV3wHVywIC5NmaLiN7Az0YkxOXOqfl Rcvg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id n10si1676709wma.106.2018.02.09.08.58.14 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 09 Feb 2018 08:58:14 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ekC06-0002zo-4w; Fri, 09 Feb 2018 16:58:14 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH v2 03/11] hw/intc/armv7m_nvic: Implement M profile cache maintenance ops Date: Fri, 9 Feb 2018 16:58:02 +0000 Message-Id: <20180209165810.6668-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180209165810.6668-1-peter.maydell@linaro.org> References: <20180209165810.6668-1-peter.maydell@linaro.org> For M profile cores, cache maintenance operations are done by writing to special registers in the system register space. For QEMU, cache operations are always NOPs, since we don't implement the cache. Implementing these explicitly avoids a spurious LOG_GUEST_ERROR when the guest uses them. Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.16.1 Reviewed-by: Richard Henderson diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 06b9598fbe..74b25ce92c 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1594,6 +1594,18 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, } break; } + case 0xf50: /* ICIALLU */ + case 0xf58: /* ICIMVAU */ + case 0xf5c: /* DCIMVAC */ + case 0xf60: /* DCISW */ + case 0xf64: /* DCCMVAU */ + case 0xf68: /* DCCMVAC */ + case 0xf6c: /* DCCSW */ + case 0xf70: /* DCCIMVAC */ + case 0xf74: /* DCCISW */ + case 0xf78: /* BPIALL */ + /* Cache and branch predictor maintenance: for QEMU these always NOP */ + break; default: bad_offset: qemu_log_mask(LOG_GUEST_ERROR, From patchwork Fri Feb 9 16:58:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 127867 Delivered-To: patches@linaro.org Received: by 10.46.124.24 with SMTP id x24csp802155ljc; Fri, 9 Feb 2018 08:58:15 -0800 (PST) X-Google-Smtp-Source: AH8x225uIbn2HTojVrTH7AxTfMMeZdP5JkjdXZZWbmBtufDs8mkcKT6Z5aUU7KYvGP2R/Ql/QkOv X-Received: by 10.223.139.91 with SMTP id v27mr2894366wra.180.1518195495385; Fri, 09 Feb 2018 08:58:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518195495; cv=none; d=google.com; s=arc-20160816; b=sqm0ZVQglV59zNXpfLBcKHV72m2+zegs0IUOeuan2r7imoqwPUltZTg9x5r4v4COKL iIoJvhewB+kVhwup24TmpxPodewFv583d/PWfHdEarIAH3mQRd8UytUEJ/q6g+yCSfkW Rg9s0qzbWuNqn/3jG/gzpuh4Uz84YeGWra06fSgH9xPXi/qXklseJ2k5aY0yjCULJaeW qqy2Mm+KfsKloAEd9uBxyWQFLXgbhP1LZSD8g9jNwukejFo25Ahlc7as7YnQT65IoVTH JUEc+NC/mw6MpLy6g4U4szlYAYSYyn3D2PCUqq2H8hJGwlcaIzHq0xgSRbp3EuZpqQYo DmmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=Ec7mIdSwcJgfdIlW71xx0VmWQ297zJiYxFWj8SDvo8g=; b=AdbeA2KpmDpdxwCIJ0wMWB/bRXqZxhgoLgIPvPqQsKX4Tg4ZrpgSBKDzWdxjcEMNH0 fy2Pk4TblZy9fRNaOZHLY8XHiZHvyBCZSRr9ltSk3X7tUVqBePtsF/Mkpz8zhzM74R4S NOoRToRc26TPNoLdlBAmwptNdXFSZ+c2OJo75I6IpcuOYBKdQSafXw1Pm7KTGy1JU9ls Iq2lq4wE5geUevHOiTb5fivfBVoVer4NTXFXrG2J8KLMRvyoNMaiqyPz4+jRtAYGDXCG iPN1gext8oqDKE9pWVSHr5/eAhfOahvS6y+LvyKfUr5l7sk3gIfZfM8LGb460zevwJnQ KjHw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id l16si2110349wrl.33.2018.02.09.08.58.15 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 09 Feb 2018 08:58:15 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ekC06-000303-RW; Fri, 09 Feb 2018 16:58:14 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH v2 04/11] hw/intc/armv7m_nvic: Implement v8M CPPWR register Date: Fri, 9 Feb 2018 16:58:03 +0000 Message-Id: <20180209165810.6668-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180209165810.6668-1-peter.maydell@linaro.org> References: <20180209165810.6668-1-peter.maydell@linaro.org> The Coprocessor Power Control Register (CPPWR) is new in v8M. It allows software to control whether coprocessors are allowed to power down and lose their state. QEMU doesn't have any notion of power control, so we choose the IMPDEF option of making the whole register RAZ/WI (indicating that no coprocessors can ever power down and lose state). Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.16.1 Reviewed-by: Richard Henderson diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 74b25ce92c..eb49fd77c7 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -776,6 +776,14 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) switch (offset) { case 4: /* Interrupt Control Type. */ return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1; + case 0xc: /* CPPWR */ + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { + goto bad_offset; + } + /* We make the IMPDEF choice that nothing can ever go into a + * non-retentive power state, which allows us to RAZ/WI this. + */ + return 0; case 0x380 ... 0x3bf: /* NVIC_ITNS */ { int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ; @@ -1175,6 +1183,12 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, ARMCPU *cpu = s->cpu; switch (offset) { + case 0xc: /* CPPWR */ + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { + goto bad_offset; + } + /* Make the IMPDEF choice to RAZ/WI this. */ + break; case 0x380 ... 0x3bf: /* NVIC_ITNS */ { int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ; From patchwork Fri Feb 9 16:58:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 127868 Delivered-To: patches@linaro.org Received: by 10.46.124.24 with SMTP id x24csp802177ljc; Fri, 9 Feb 2018 08:58:17 -0800 (PST) X-Google-Smtp-Source: AH8x22491ZZNIt0h70vyWg7jK0gaNgWGGxecLTbxp6VQpevJEC/6KTa43SvlPmtfKjIc/PgZ9k1l X-Received: by 10.28.105.80 with SMTP id e77mr2734161wmc.123.1518195497112; Fri, 09 Feb 2018 08:58:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518195497; cv=none; d=google.com; s=arc-20160816; b=Ec0OwnmccIDW2HEW7OwRwqB6Q94LqE7OW+LsKDUdWEJDqqWCeQIdosv1T1eRNlBN6n pRlbmVjfajfOfKLFuAwAu3CBtBQFY3eelfY4xxz800flAuXOQC2f67i6KFH/EOyLzBGA IlnSm8i43DJfSPwTVhpF78qhRHpseKdVQDbe8nwep8O7J7Cy3AlZu7jv6ZkmPrkfTOJ8 nVVL0+q97n5xGutpWxA0dZssbHh0uL1g8u08ZUYAcIlmSjIWFejc8H76rKdPHzhI9Exu TRvs65uBL68btPXqsR1gRxDCGj27tHyF0PR2kEIAhT9vqjrfLz7JL90KcrNMVCV0w8AF 0pAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=oilZFdbngdoZgrErTwbIFe/9tviyhfuHlkhAqjSzA50=; b=YOTkjptMKYZSI8rQaxV7b0Lya82gvQDFNhcUT4FJ66iQA6LlTtnPI2Rh2eNjbSOMez VDMe87ihJpQYzhKs/uflfiXCZWVC+PKUNhwT4XV+Q/KbMklfDFbXpE5VuLxEY7xzOwU+ +2AXOvTJhnAD2y/wKEwvgQp9EienrzJ8lcXojrs1d/ufK6J8zhZPWjuZx99ics14Ogkl si5ZpJXdIvJ4g3xIdGBcTFFoUHAY4MQY6sgm5xrhV3u9radbneGn74gilll0IWQuHsjl kCZ2h1azryR/sKCZNFDpK4xQ4o1OPuiIfPCIo7GK+XDRL9mTWI459AjVS3u1CYfY97Q2 9tKg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id d30si2129838wra.341.2018.02.09.08.58.16 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 09 Feb 2018 08:58:17 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ekC08-00030O-K7; Fri, 09 Feb 2018 16:58:16 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH v2 05/11] hw/intc/armv7m_nvic: Implement cache ID registers Date: Fri, 9 Feb 2018 16:58:04 +0000 Message-Id: <20180209165810.6668-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180209165810.6668-1-peter.maydell@linaro.org> References: <20180209165810.6668-1-peter.maydell@linaro.org> M profile cores have a similar setup for cache ID registers to A profile: * Cache Level ID Register (CLIDR) is a fixed value * Cache Type Register (CTR) is a fixed value * Cache Size ID Registers (CCSIDR) are a bank of registers; which one you see is selected by the Cache Size Selection Register (CSSELR) The only difference is that they're in the NVIC memory mapped register space rather than being coprocessor registers. Implement the M profile view of them. Since neither Cortex-M3 nor Cortex-M4 implement caches, we don't need to update their init functions and can leave the ctr/clidr/ccsidr[] fields in their ARMCPU structs at zero. Newer cores (like the Cortex-M33) will want to be able to set these ID registers to non-zero values, though. Signed-off-by: Peter Maydell --- v1->v2 changes: use FIELD() to define some constants; add compile-time assert that we won't index outside cssidr[] --- target/arm/cpu.h | 26 ++++++++++++++++++++++++++ hw/intc/armv7m_nvic.c | 16 ++++++++++++++++ target/arm/machine.c | 36 ++++++++++++++++++++++++++++++++++++ 3 files changed, 78 insertions(+) -- 2.16.1 Reviewed-by: Richard Henderson diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 521444a5a1..4c1b9e9814 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -496,6 +496,7 @@ typedef struct CPUARMState { uint32_t faultmask[M_REG_NUM_BANKS]; uint32_t aircr; /* only holds r/w state if security extn implemented */ uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ + uint32_t csselr[M_REG_NUM_BANKS]; } v7m; /* Information associated with an exception about to be taken: @@ -1325,6 +1326,23 @@ FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) +/* v7M CLIDR bits */ +FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) +FIELD(V7M_CLIDR, LOUIS, 21, 3) +FIELD(V7M_CLIDR, LOC, 24, 3) +FIELD(V7M_CLIDR, LOUU, 27, 3) +FIELD(V7M_CLIDR, ICB, 30, 2) + +FIELD(V7M_CSSELR, IND, 0, 1) +FIELD(V7M_CSSELR, LEVEL, 1, 3) +/* We use the combination of InD and Level to index into cpu->ccsidr[]; + * define a mask for this and check that it doesn't permit running off + * the end of the array. + */ +FIELD(V7M_CSSELR, INDEX, 0, 4) + +QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); + /* If adding a feature bit which corresponds to a Linux ELF * HWCAP bit, remember to update the feature-bit-to-hwcap * mapping in linux-user/elfload.c:get_elf_hwcap(). @@ -2485,6 +2503,14 @@ static inline int arm_debug_target_el(CPUARMState *env) } } +static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) +{ + /* If all the CLIDR.Ctypem bits are 0 there are no caches, and + * CSSELR is RAZ/WI. + */ + return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; +} + static inline bool aa64_generate_debug_exceptions(CPUARMState *env) { if (arm_is_secure(env)) { diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index eb49fd77c7..040f3380ec 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1025,6 +1025,17 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) return cpu->id_isar4; case 0xd74: /* ISAR5. */ return cpu->id_isar5; + case 0xd78: /* CLIDR */ + return cpu->clidr; + case 0xd7c: /* CTR */ + return cpu->ctr; + case 0xd80: /* CSSIDR */ + { + int idx = cpu->env.v7m.csselr[attrs.secure] & R_V7M_CSSELR_INDEX_MASK; + return cpu->ccsidr[idx]; + } + case 0xd84: /* CSSELR */ + return cpu->env.v7m.csselr[attrs.secure]; /* TODO: Implement debug registers. */ case 0xd90: /* MPU_TYPE */ /* Unified MPU; if the MPU is not present this value is zero */ @@ -1385,6 +1396,11 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, qemu_log_mask(LOG_UNIMP, "NVIC: Aux fault status registers unimplemented\n"); break; + case 0xd84: /* CSSELR */ + if (!arm_v7m_csselr_razwi(cpu)) { + cpu->env.v7m.csselr[attrs.secure] = value & R_V7M_CSSELR_INDEX_MASK; + } + break; case 0xd90: /* MPU_TYPE */ return; /* RO */ case 0xd94: /* MPU_CTRL */ diff --git a/target/arm/machine.c b/target/arm/machine.c index 2c8b43062f..cae63c2f98 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -191,6 +191,41 @@ static const VMStateDescription vmstate_m_faultmask_primask = { } }; +/* CSSELR is in a subsection because we didn't implement it previously. + * Migration from an old implementation will leave it at zero, which + * is OK since the only CPUs in the old implementation make the + * register RAZ/WI. + * Since there was no version of QEMU which implemented the CSSELR for + * just non-secure, we transfer both banks here rather than putting + * the secure banked version in the m-security subsection. + */ +static bool csselr_vmstate_validate(void *opaque, int version_id) +{ + ARMCPU *cpu = opaque; + + return cpu->env.v7m.csselr[M_REG_NS] <= R_V7M_CSSELR_INDEX_MASK + && cpu->env.v7m.csselr[M_REG_S] <= R_V7M_CSSELR_INDEX_MASK; +} + +static bool m_csselr_needed(void *opaque) +{ + ARMCPU *cpu = opaque; + + return !arm_v7m_csselr_razwi(cpu); +} + +static const VMStateDescription vmstate_m_csselr = { + .name = "cpu/m/csselr", + .version_id = 1, + .minimum_version_id = 1, + .needed = m_csselr_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(env.v7m.csselr, ARMCPU, M_REG_NUM_BANKS), + VMSTATE_VALIDATE("CSSELR is valid", csselr_vmstate_validate), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_m = { .name = "cpu/m", .version_id = 4, @@ -212,6 +247,7 @@ static const VMStateDescription vmstate_m = { }, .subsections = (const VMStateDescription*[]) { &vmstate_m_faultmask_primask, + &vmstate_m_csselr, NULL } }; From patchwork Fri Feb 9 16:58:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 127869 Delivered-To: patches@linaro.org Received: by 10.46.124.24 with SMTP id x24csp802190ljc; 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[2001:8b0:1d0::2]) by mx.google.com with ESMTPS id n188si1833643wmd.49.2018.02.09.08.58.17 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 09 Feb 2018 08:58:17 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ekC09-00030g-Bi; Fri, 09 Feb 2018 16:58:17 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH v2 06/11] hw/intc/armv7m_nvic: Implement SCR Date: Fri, 9 Feb 2018 16:58:05 +0000 Message-Id: <20180209165810.6668-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180209165810.6668-1-peter.maydell@linaro.org> References: <20180209165810.6668-1-peter.maydell@linaro.org> We were previously making the system control register (SCR) just RAZ/WI. Although we don't implement the functionality this register controls, we should at least provide the state, including the banked state for v8M. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 7 +++++++ hw/intc/armv7m_nvic.c | 12 ++++++++---- target/arm/machine.c | 12 ++++++++++++ 3 files changed, 27 insertions(+), 4 deletions(-) -- 2.16.1 Reviewed-by: Richard Henderson diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4c1b9e9814..cfa92c477b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -497,6 +497,7 @@ typedef struct CPUARMState { uint32_t aircr; /* only holds r/w state if security extn implemented */ uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ uint32_t csselr[M_REG_NUM_BANKS]; + uint32_t scr[M_REG_NUM_BANKS]; } v7m; /* Information associated with an exception about to be taken: @@ -1258,6 +1259,12 @@ FIELD(V7M_CCR, STKALIGN, 9, 1) FIELD(V7M_CCR, DC, 16, 1) FIELD(V7M_CCR, IC, 17, 1) +/* V7M SCR bits */ +FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) +FIELD(V7M_SCR, SLEEPDEEP, 2, 1) +FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) +FIELD(V7M_SCR, SEVONPEND, 4, 1) + /* V7M AIRCR bits */ FIELD(V7M_AIRCR, VECTRESET, 0, 1) FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 040f3380ec..ea3b7cce14 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -863,8 +863,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) } return val; case 0xd10: /* System Control. */ - /* TODO: Implement SLEEPONEXIT. */ - return 0; + return cpu->env.v7m.scr[attrs.secure]; case 0xd14: /* Configuration Control. */ /* The BFHFNMIGN bit is the only non-banked bit; we * keep it in the non-secure copy of the register. @@ -1285,8 +1284,13 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, } break; case 0xd10: /* System Control. */ - /* TODO: Implement control registers. */ - qemu_log_mask(LOG_UNIMP, "NVIC: SCR unimplemented\n"); + /* We don't implement deep-sleep so these bits are RAZ/WI. + * The other bits in the register are banked. + * QEMU's implementation ignores SEVONPEND and SLEEPONEXIT, which + * is architecturally permitted. + */ + value &= ~(R_V7M_SCR_SLEEPDEEP_MASK | R_V7M_SCR_SLEEPDEEPS_MASK); + cpu->env.v7m.scr[attrs.secure] = value; break; case 0xd14: /* Configuration Control. */ /* Enforce RAZ/WI on reserved and must-RAZ/WI bits */ diff --git a/target/arm/machine.c b/target/arm/machine.c index cae63c2f98..30fb1454a6 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -226,6 +226,16 @@ static const VMStateDescription vmstate_m_csselr = { } }; +static const VMStateDescription vmstate_m_scr = { + .name = "cpu/m/scr", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(env.v7m.scr[M_REG_NS], ARMCPU), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_m = { .name = "cpu/m", .version_id = 4, @@ -248,6 +258,7 @@ static const VMStateDescription vmstate_m = { .subsections = (const VMStateDescription*[]) { &vmstate_m_faultmask_primask, &vmstate_m_csselr, + &vmstate_m_scr, NULL } }; @@ -411,6 +422,7 @@ static const VMStateDescription vmstate_m_security = { VMSTATE_UINT32(env.sau.rnr, ARMCPU), VMSTATE_VALIDATE("SAU_RNR is valid", sau_rnr_vmstate_validate), VMSTATE_UINT32(env.sau.ctrl, ARMCPU), + VMSTATE_UINT32(env.v7m.scr[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; From patchwork Fri Feb 9 16:58:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 127871 Delivered-To: patches@linaro.org Received: by 10.46.124.24 with SMTP id x24csp802194ljc; Fri, 9 Feb 2018 08:58:18 -0800 (PST) X-Google-Smtp-Source: AH8x227893ILDQgrQToEysjcWW3xLkguEMW7dPuRlwEKBMM1FD6i5XqGYL1ZKA9/FVX8G8o+bQ7b X-Received: by 10.28.71.198 with SMTP id m67mr2850071wmi.40.1518195498553; Fri, 09 Feb 2018 08:58:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518195498; cv=none; d=google.com; s=arc-20160816; b=NePHzFMJSTcqASeGijXGSKYXAJvIfL0zpoPpKt+cnMzo9lFLjV23KRWnr3qKudKFD/ 2pIpPnA48N4rAnj2Rcbt1/pDeK8KgDPZeOry+l+OKFWYiKd2VrYvkqGMv3AF4dS0+adw NMJIxbLzFUQ92DALSrpQ+aHBCnPx4QpZAApgLVeN4r6FSua5KBkyvV8Iift9yn9b/Kvj zWZS04oXioOl3d/UXEegHrnlzcGafr1n/LjRPhTPSOxPym7GkcGzX5pAtuJXMSqN9pQF 0xAHwORN8wWLHMYiflHKXpNxZU1CJvIQErvnIn0+OJ70bDLQMzWJgletxIsonpjeDjNd YHwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=gPZBOWG62Ml3ABPlHSWpZm/7Y3tm7VBFmIMMS/caH1M=; b=tFgQFou1a565stGxs2l6ZY4Xb2u5Db9uIIsoxh1Fys5Rn16H8LLaBN/kfhbCrNQcqW A2sPY4YYRvHmw7FIo2DMQmMFiDodWP3MmsWjKdwpoZCqF1QV3XdFy5RJNZZFd0qKRx1Z ptFWUzC0/iZQTSaZB/HzsyWAIwgpqk5aAhq2apOxn7C/oTpAIDtXUemaWWmnA8Vn4dkt 5cnjDFbQVMikLWzdUxMw57xcNUo7IOClkN7hdbUdw4eH3I0mNQY5WSOtsIokvra7XSqZ BE41UJo6pyPJPm9ck3l549gtUdkcpzrSU9ZNfd15LAH1dSu34ZBHVSXH/ctZGYndpDyC guzg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id f17si2007735wrh.40.2018.02.09.08.58.18 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 09 Feb 2018 08:58:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ekC0A-00030x-4G; Fri, 09 Feb 2018 16:58:18 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH v2 07/11] target/arm: Implement writing to CONTROL_NS for v8M Date: Fri, 9 Feb 2018 16:58:06 +0000 Message-Id: <20180209165810.6668-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180209165810.6668-1-peter.maydell@linaro.org> References: <20180209165810.6668-1-peter.maydell@linaro.org> In commit 50f11062d4c896 we added support for MSR/MRS access to the NS banked special registers, but we forgot to implement the support for writing to CONTROL_NS. Correct the omission. Signed-off-by: Peter Maydell --- target/arm/helper.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.16.1 Reviewed-by: Richard Henderson diff --git a/target/arm/helper.c b/target/arm/helper.c index 180ab75458..7c1dcb0330 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10519,6 +10519,16 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) } env->v7m.faultmask[M_REG_NS] = val & 1; return; + case 0x94: /* CONTROL_NS */ + if (!env->v7m.secure) { + return; + } + write_v7m_control_spsel_for_secstate(env, + val & R_V7M_CONTROL_SPSEL_MASK, + M_REG_NS); + env->v7m.control[M_REG_NS] &= ~R_V7M_CONTROL_NPRIV_MASK; + env->v7m.control[M_REG_NS] |= val & R_V7M_CONTROL_NPRIV_MASK; + return; case 0x98: /* SP_NS */ { /* This gives the non-secure SP selected based on whether we're From patchwork Fri Feb 9 16:58:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 127872 Delivered-To: patches@linaro.org Received: by 10.46.124.24 with SMTP id x24csp802204ljc; Fri, 9 Feb 2018 08:58:19 -0800 (PST) X-Google-Smtp-Source: AH8x226fjKSD3ftNoW5V2znshdV4rbjol37APKwNsss/j+OebBZj3TdTCbpLUjx/6kLLJQ3HrVpc X-Received: by 10.223.197.67 with SMTP id s3mr2877755wrf.239.1518195499294; Fri, 09 Feb 2018 08:58:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518195499; cv=none; d=google.com; s=arc-20160816; b=AKRCqQqlXLWoeKyq4JG4XrHJgZ4FAJiXufhH3iUNBSEr89ndmTTq0fN8roknyx2tih ZmPt5SXALrHGYY/BdQ2h7DnLb9ii0U5D9eUm4j9UXuuqUyHTC/qrc8TRuRTa6kUC8THV JTOkQ4pmGwD+eRtxK2aqipSMR6apO8YvjqhOoI1QjTHkxMjXrHm+xQG/8bYueeBQRSKf YpIjcFIizlWLbtcs1ErMSZ0dX8b+dPxRQiY4G1rHoTAxnySr0p+aHthalpDcZhPuMPsn PoQge4ivmNSNbgic9zEYMicJwmCNIrzrpIgP1iqThATTEHvjlavblLjuORMR8c9ojGw3 CtSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=fW+o3X2yhpfLWKA90r3Rw7yTLrwIWhhLNnYdCwyW9kw=; b=udTQYtgDXmK1au/JcNiScH5V6bhvxCmb/Znu9Az0a0GuALnRfzGmRC5+9tDZKREhej gA9DxKGjPgMhSdDhiROa3SPCQJnPrbZ81bmZ/CALN5+kmUiDOgeGeX+mQmd1AE9gQzYb XIBNnWkF/aZA4f+iASRy24MHizSsupF0AqLiAvDLVNCjkhZt8yrhNXFncSeZ3azljtax 06tb9oxvp1xXdlaaiLNmBwZ6/PSh5ovOu4C9fetP0LlPu6pNhwkaY6KkASbUNll65tO5 g8zi8nFIKStCtE1q6tdQk8FUYTR5ORAV2K7x7vSUfrS2DFwmMisgfpt9kdufPZTpEcou BOgw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id q5si1892259wre.233.2018.02.09.08.58.19 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 09 Feb 2018 08:58:19 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ekC0A-00031D-RR; Fri, 09 Feb 2018 16:58:18 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH v2 08/11] hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions Date: Fri, 9 Feb 2018 16:58:07 +0000 Message-Id: <20180209165810.6668-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180209165810.6668-1-peter.maydell@linaro.org> References: <20180209165810.6668-1-peter.maydell@linaro.org> MIME-Version: 1.0 In many of the NVIC registers relating to interrupts, we have to convert from a byte offset within a register set into the number of the first interrupt which is affected. We were getting this wrong for: * reads of NVIC_ISPR, NVIC_ISER, NVIC_ICPR, NVIC_ICER, NVIC_IABR -- in all these cases we were missing the "* 8" needed to convert from the byte offset to the interrupt number (since all these registers use one bit per interrupt) * writes of NVIC_IPR had the opposite problem of a spurious "* 8" (since these registers use one byte per interrupt) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- hw/intc/armv7m_nvic.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.16.1 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index ea3b7cce14..c51151fa8a 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1724,7 +1724,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, /* fall through */ case 0x180 ... 0x1bf: /* NVIC Clear enable */ val = 0; - startvec = offset - 0x180 + NVIC_FIRST_IRQ; /* vector # */ + startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ; /* vector # */ for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { if (s->vectors[startvec + i].enabled && @@ -1738,7 +1738,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, /* fall through */ case 0x280 ... 0x2bf: /* NVIC Clear pend */ val = 0; - startvec = offset - 0x280 + NVIC_FIRST_IRQ; /* vector # */ + startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */ for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { if (s->vectors[startvec + i].pending && (attrs.secure || s->itns[startvec + i])) { @@ -1748,7 +1748,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, break; case 0x300 ... 0x33f: /* NVIC Active */ val = 0; - startvec = offset - 0x300 + NVIC_FIRST_IRQ; /* vector # */ + startvec = 8 * (offset - 0x300) + NVIC_FIRST_IRQ; /* vector # */ for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { if (s->vectors[startvec + i].active && @@ -1863,7 +1863,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, case 0x300 ... 0x33f: /* NVIC Active */ return MEMTX_OK; /* R/O */ case 0x400 ... 0x5ef: /* NVIC Priority */ - startvec = 8 * (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */ + startvec = (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */ for (i = 0; i < size && startvec + i < s->num_irq; i++) { if (attrs.secure || s->itns[startvec + i]) { From patchwork Fri Feb 9 16:58:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 127874 Delivered-To: patches@linaro.org Received: by 10.46.124.24 with SMTP id x24csp802219ljc; Fri, 9 Feb 2018 08:58:20 -0800 (PST) X-Google-Smtp-Source: AH8x22641TMF1mH6N7leUmAh15jTyWUORpKhTquJV+YneP4WHN0D/MNF8sI7e5D/iasJ3gDQjDdn X-Received: by 10.28.227.70 with SMTP id a67mr2778861wmh.46.1518195500014; Fri, 09 Feb 2018 08:58:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518195500; cv=none; d=google.com; s=arc-20160816; b=kZ9BbbyCWtXTlwYajfXqwW6RlAl6C0VTtfeh/PjsMVn8Y3YWvdjvMvjUUyw63xCGb9 eRVkNYApvwqCq3MrRLv3rYq5U7w7WMRDqXbqf34KpZ4o354gQgmeWjdw+56qdZOLke6m Wg79AGdJYg2M9ayM9cFFB/jNXEf4a0do82gFt6pDzu19OK9TO/8tNWey50Zuhpmwkvsh C49aI6TUeVU6BCHSI1a1GXkCRkvyCfRnmDcPRK4V30hHBWUR+EtYp3kuNA6CEnC0sXEN 4FXoWnx9GOGfC2noQkkKWzQqUygKKzeHEluif5PgmK0OXpxV5css4YLlu5EqVh1OW5oZ q5WA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=kOs0l740S7EYdlPDNB9WaKoetr+mQfo05LmniM8iPR8=; b=FhDThbrom7H8vVAM1oezs/buQpJtu0ivvUalmoW6a+3szRzv4t6VV4XZyWPqFz5d1i jymsuZ/us7kA8TB57U5/LTXCkyW815pxLQiUl9tUf0LeuvPyriU70/+mx43BvuFc5grV 9ULzYCq/nXrWWnSn+x69DQI4vOeOGrITgXnIU3KmXkVGu531rNK6O26SzKKxNvcJ3ghX Rm4eJff/+oBDN6+XHKjLb3+AUnQjlr3dF/fMQR1njpKHVLHqMLgk8pG/R/EnG0hN6dCc Rpuc++ew2So7IGnEOuZv3Nm1W6txjIdA3BnMTSngLaa3cuxDCjelpwO0SbsxjVuMjIzQ 9I5w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id a1si1986292wrd.360.2018.02.09.08.58.19 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 09 Feb 2018 08:58:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ekC0B-00031W-Id; Fri, 09 Feb 2018 16:58:19 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH v2 09/11] target/arm: Add AIRCR to vmstate struct Date: Fri, 9 Feb 2018 16:58:08 +0000 Message-Id: <20180209165810.6668-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180209165810.6668-1-peter.maydell@linaro.org> References: <20180209165810.6668-1-peter.maydell@linaro.org> In commit commit 3b2e934463121 we added support for the AIRCR register holding state, but forgot to add it to the vmstate structs. Since it only holds r/w state if the security extension is implemented, we can just add it to vmstate_m_security. Signed-off-by: Peter Maydell --- target/arm/machine.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.16.1 Reviewed-by: Richard Henderson diff --git a/target/arm/machine.c b/target/arm/machine.c index 30fb1454a6..25cdf4d581 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -423,6 +423,10 @@ static const VMStateDescription vmstate_m_security = { VMSTATE_VALIDATE("SAU_RNR is valid", sau_rnr_vmstate_validate), VMSTATE_UINT32(env.sau.ctrl, ARMCPU), VMSTATE_UINT32(env.v7m.scr[M_REG_S], ARMCPU), + /* AIRCR is not secure-only, but our implementation is R/O if the + * security extension is unimplemented, so we migrate it here. + */ + VMSTATE_UINT32(env.v7m.aircr, ARMCPU), VMSTATE_END_OF_LIST() } }; From patchwork Fri Feb 9 16:58:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 127873 Delivered-To: patches@linaro.org Received: by 10.46.124.24 with SMTP id x24csp802229ljc; Fri, 9 Feb 2018 08:58:20 -0800 (PST) X-Google-Smtp-Source: AH8x224cQmFswkpn6rUW3GFt7ivmJHBZ8FAI9Vq5xgzTgrJaC+RZICz5hB3ItQjdlwFqeLjEZl7H X-Received: by 10.223.208.141 with SMTP id y13mr3238150wrh.31.1518195500720; Fri, 09 Feb 2018 08:58:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518195500; cv=none; d=google.com; s=arc-20160816; b=lMtjIHmky602q8eV6GoeUVHpwoqM1FE/f8s1rpx9Zozer2oN6iNqvSUXsvD/XVWbYp 70HWEMaM+vANO2sibBBV4jKkTD1JNQ/BzaG6wJYFz32tOBez7M/Zw8iEBegl0bFPVWQi q7kW2Gi6A2FeIpHGF5CGr+g2sfjRUrI+RkR2YseWrSjx9h8//8x8pmUGy6SsDPdywWrr d05XaPUIeenuScDQ1pTJG6Ejl3KTKNq/+bKsP2CQwnedjcLsJzBvMxHJcw1jz8Fk4VyC GEKcZOuPNVfAiePo9ynYa68vS8bpiMK0Y0+0otbg1M14vBkt/rjgfha8QeZ+YeGwiLtu FKCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=JnNwmIwtiCiIK6QGhT96KwxMNxVw+pKDg+tKYJ7M/UU=; b=TQdokwzPDjW51BbvQ4e67DehCoXMq2r26qKsiBrwyGK1PbKRpvQaHkC7W1S0GCcURB OBxMbzksiJlzFMzIpW10iXZlTpw8PRsoNSCofc8T6VrV8UEfr0XMgtfXa+vf+oN4x9GS rjgJ+rOANGccwXcjQqDldmlaUL9I4o6s3s+efcCiPCtPfnpJS6IWIywJIrzvAuPutD7q BnF5jxMSUdfT2nhXCAPgcQ/v2MB3a8u0//EvFPpWvJ7hB0OdJAhZNsQDORM0RD1DIQqP Q45pFJgzpSisRRLqDoo9wGkTpIo9B+PKa5ROgdfvYY5NK6w+wPLNsVgsDdLY70hKqoht TJ6g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id o29si1966763wro.142.2018.02.09.08.58.20 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 09 Feb 2018 08:58:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ekC0C-00031o-8l; Fri, 09 Feb 2018 16:58:20 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH v2 10/11] target/arm: Migrate v7m.other_sp Date: Fri, 9 Feb 2018 16:58:09 +0000 Message-Id: <20180209165810.6668-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180209165810.6668-1-peter.maydell@linaro.org> References: <20180209165810.6668-1-peter.maydell@linaro.org> In commit abc24d86cc0364f we accidentally broke migration of the stack pointer value for the mode (process, handler) the CPU is not currently running as. (The commit correctly removed the no-longer-used v7m.current_sp flag from the VMState but also deleted the still very much in use v7m.other_sp SP value field.) Add a subsection to migrate it again. (We don't need to care about trying to retain compatibility with pre-abc24d86cc0364f versions of QEMU, because that commit bumped the version_id and we've since bumped it again a couple of times.) Signed-off-by: Peter Maydell --- target/arm/machine.c | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.16.1 Reviewed-by: Richard Henderson diff --git a/target/arm/machine.c b/target/arm/machine.c index 25cdf4d581..1a20d6c36c 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -236,6 +236,16 @@ static const VMStateDescription vmstate_m_scr = { } }; +static const VMStateDescription vmstate_m_other_sp = { + .name = "cpu/m/other-sp", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(env.v7m.other_sp, ARMCPU), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_m = { .name = "cpu/m", .version_id = 4, @@ -259,6 +269,7 @@ static const VMStateDescription vmstate_m = { &vmstate_m_faultmask_primask, &vmstate_m_csselr, &vmstate_m_scr, + &vmstate_m_other_sp, NULL } }; From patchwork Fri Feb 9 16:58:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 127875 Delivered-To: patches@linaro.org Received: by 10.46.124.24 with SMTP id x24csp802240ljc; Fri, 9 Feb 2018 08:58:21 -0800 (PST) X-Google-Smtp-Source: AH8x224LFNEEZYFb2JdD2soJJgcCS6NZdE3n3KAVaSActmEfttBWuF7gUdIIfaHvz+CtcSTFqlcA X-Received: by 10.28.157.139 with SMTP id g133mr2734549wme.114.1518195501502; Fri, 09 Feb 2018 08:58:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518195501; cv=none; d=google.com; s=arc-20160816; b=FpQG1qFoTAmJMPfqR8VdTY4P3rJUBhrO++mgllOQH2yLsHbHURv6AA5RD+62Exut6Q aDYqvjx8j9qpxLLP6M+6YJLhXWXQabD8Kvl3yKrr1nrgMRWykzsa3jAPX14ba/qvCaPK eXy/OQF+F3IqxD4lMnsOCIzR0a0RjTXhou3+aesm3bEn34f0+X+tN9Ypmu1yAMFGcIUV zJX62ypj+8cn2Ct1YWa733I/wHzED26tiDaTJl//E+qIsrB2JX0m4s2GiuH7bWtTVTSG EgLSuRSd1KCagZlIDl0pzWCvdeGFNCgrLai1rsjq1RN/2GZrdJBgjOTlsNOGPGCPj3On 3ymQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=iX5+4KX0QoNuJTEmYUrR8SSTKVzn1S4JAWUtVaPRap8=; b=wYYRZHmDZiTRCxgrmMByWHZmuyNRN4mFlSEezAIPU66UeDRFL+yNYPoEOFwW6Hcinz Fz0VkgzlZqWSF43qUecuyb91oIYNEj9K2XCGK8zW1TZ2VUJx2BMK8oD0x0pKp/X56z54 dJJZ5cmBkFDtb+ltOfhXcIhDhGrcJqBKotHn1ep3mmbp2uE3ByOrP9GrCtwFwkrkmK+E blLlfBc5+FsrdRwPauOic85v1kduqkdjhMysp9KUtwRVeLQ7yWwISZsj314HsbUc6//G 7xRMypVijJ2DR/HjlAXIfHyi64dwBAfE9xsLrX4YONUurkr+u4DHK4NMmJUGxDIq16/G W6Dw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 32si2093709wrl.204.2018.02.09.08.58.21 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 09 Feb 2018 08:58:21 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ekC0D-000323-1T; Fri, 09 Feb 2018 16:58:21 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH v2 11/11] target/arm: Implement v8M MSPLIM and PSPLIM registers Date: Fri, 9 Feb 2018 16:58:10 +0000 Message-Id: <20180209165810.6668-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180209165810.6668-1-peter.maydell@linaro.org> References: <20180209165810.6668-1-peter.maydell@linaro.org> The v8M architecture includes hardware support for enforcing stack pointer limits. We don't implement this behaviour yet, but provide the MSPLIM and PSPLIM stack pointer limit registers as reads-as-written, so that when we do implement the checks in future this won't break guest migration. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 ++ target/arm/helper.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ target/arm/machine.c | 21 +++++++++++++++++++++ 3 files changed, 69 insertions(+) -- 2.16.1 Reviewed-by: Richard Henderson diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cfa92c477b..3ef523ddbd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -498,6 +498,8 @@ typedef struct CPUARMState { uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ uint32_t csselr[M_REG_NUM_BANKS]; uint32_t scr[M_REG_NUM_BANKS]; + uint32_t msplim[M_REG_NUM_BANKS]; + uint32_t psplim[M_REG_NUM_BANKS]; } v7m; /* Information associated with an exception about to be taken: diff --git a/target/arm/helper.c b/target/arm/helper.c index 7c1dcb0330..03b1a3fd92 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10415,6 +10415,16 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) return 0; } return env->v7m.other_ss_psp; + case 0x8a: /* MSPLIM_NS */ + if (!env->v7m.secure) { + return 0; + } + return env->v7m.msplim[M_REG_NS]; + case 0x8b: /* PSPLIM_NS */ + if (!env->v7m.secure) { + return 0; + } + return env->v7m.psplim[M_REG_NS]; case 0x90: /* PRIMASK_NS */ if (!env->v7m.secure) { return 0; @@ -10456,6 +10466,16 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) return v7m_using_psp(env) ? env->v7m.other_sp : env->regs[13]; case 9: /* PSP */ return v7m_using_psp(env) ? env->regs[13] : env->v7m.other_sp; + case 10: /* MSPLIM */ + if (!arm_feature(env, ARM_FEATURE_V8)) { + goto bad_reg; + } + return env->v7m.msplim[env->v7m.secure]; + case 11: /* PSPLIM */ + if (!arm_feature(env, ARM_FEATURE_V8)) { + goto bad_reg; + } + return env->v7m.psplim[env->v7m.secure]; case 16: /* PRIMASK */ return env->v7m.primask[env->v7m.secure]; case 17: /* BASEPRI */ @@ -10464,6 +10484,7 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) case 19: /* FAULTMASK */ return env->v7m.faultmask[env->v7m.secure]; default: + bad_reg: qemu_log_mask(LOG_GUEST_ERROR, "Attempt to read unknown special" " register %d\n", reg); return 0; @@ -10501,6 +10522,18 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) } env->v7m.other_ss_psp = val; return; + case 0x8a: /* MSPLIM_NS */ + if (!env->v7m.secure) { + return; + } + env->v7m.msplim[M_REG_NS] = val & ~7; + return; + case 0x8b: /* PSPLIM_NS */ + if (!env->v7m.secure) { + return; + } + env->v7m.psplim[M_REG_NS] = val & ~7; + return; case 0x90: /* PRIMASK_NS */ if (!env->v7m.secure) { return; @@ -10580,6 +10613,18 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) env->v7m.other_sp = val; } break; + case 10: /* MSPLIM */ + if (!arm_feature(env, ARM_FEATURE_V8)) { + goto bad_reg; + } + env->v7m.msplim[env->v7m.secure] = val & ~7; + break; + case 11: /* PSPLIM */ + if (!arm_feature(env, ARM_FEATURE_V8)) { + goto bad_reg; + } + env->v7m.psplim[env->v7m.secure] = val & ~7; + break; case 16: /* PRIMASK */ env->v7m.primask[env->v7m.secure] = val & 1; break; @@ -10612,6 +10657,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK; break; default: + bad_reg: qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special" " register %d\n", reg); return; diff --git a/target/arm/machine.c b/target/arm/machine.c index 1a20d6c36c..2e28d086bd 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -246,6 +246,26 @@ static const VMStateDescription vmstate_m_other_sp = { } }; +static bool m_v8m_needed(void *opaque) +{ + ARMCPU *cpu = opaque; + CPUARMState *env = &cpu->env; + + return arm_feature(env, ARM_FEATURE_M) && arm_feature(env, ARM_FEATURE_V8); +} + +static const VMStateDescription vmstate_m_v8m = { + .name = "cpu/m/v8m", + .version_id = 1, + .minimum_version_id = 1, + .needed = m_v8m_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(env.v7m.msplim, ARMCPU, M_REG_NUM_BANKS), + VMSTATE_UINT32_ARRAY(env.v7m.psplim, ARMCPU, M_REG_NUM_BANKS), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_m = { .name = "cpu/m", .version_id = 4, @@ -270,6 +290,7 @@ static const VMStateDescription vmstate_m = { &vmstate_m_csselr, &vmstate_m_scr, &vmstate_m_other_sp, + &vmstate_m_v8m, NULL } };