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[209.51.188.17]) by mx.google.com with ESMTPS id a5si8004725ybp.116.2020.12.18.02.26.56 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 18 Dec 2020 02:26:56 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:51730 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqCyN-0006Wm-Pj for patch@linaro.org; Fri, 18 Dec 2020 05:26:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43896) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kqCvs-0002wX-SW for qemu-devel@nongnu.org; Fri, 18 Dec 2020 05:24:20 -0500 Received: from mout.kundenserver.de ([212.227.17.13]:41353) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kqCvp-000741-H3 for qemu-devel@nongnu.org; Fri, 18 Dec 2020 05:24:20 -0500 Received: from localhost.localdomain ([82.252.144.198]) by mrelayeu.kundenserver.de (mreue109 [212.227.15.183]) with ESMTPSA (Nemesis) id 1M9WqY-1kkjHv1aZI-005YnI; Fri, 18 Dec 2020 11:24:15 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 11/14] linux-user/sparc: Correct sparc64_get/set_context() FPU handling Date: Fri, 18 Dec 2020 11:24:04 +0100 Message-Id: <20201218102407.597566-12-laurent@vivier.eu> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201218102407.597566-1-laurent@vivier.eu> References: <20201218102407.597566-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:tAA8wzpmcyTJvwGHlgOvaKxlvdE0g2SF7CMassFbzX1PMAMdj4K haISmeZscM90+XOik+FLruL+p5MaO/p0NzkYO3EIeeIAbIxzOMi/cDPdbUhKoCvo9gfa+fH ppik7UmnlV5jrEUWladWNOL4kN309vXCeDw7tPueKjB/QBNkDbRRRFzLftgPjUzb4XZ6bkb 2GYyyI+DXcFtReQjm8wfg== X-UI-Out-Filterresults: notjunk:1; V03:K0:Y55u4TcnwEY=:x3+GQFQNpKep3YgaCxKES8 P+YtFIgafhvsqRcu8cwKbTJJcYifSBYwnNWc1x1y0rYoTZl0CkQcCFCxjqN5HKFXPqrhvdYpz VNj7YTzvLIschvi43KYNxSNYDPWpMsHjfiF26txqu5AMY/WKu7kMtRcW8paiH7j4UaXT9/McK Oas3Noc97xXcLrIVdhv160sWZN4rhKhsNXnnUcTw9aEI/F6fjzf2ltjN7e3ZXLwsYfj06WsJg izPc9YjxIy3DMy8t9RObeKbHF+hV1Sg6Wg9BIjrd2N3sOr586iASW6Qg5/1Z8e5h82OwlGgKH n9vkRgb4TnU6awfJossq8B4XQe0dWytVSen/pRaBlohST1VKbVDYjxs5p7mZ/p2082MIwxUy1 2sXbh6+/DosC0UmqFLTEARehVIx6SaVxPgXuIhPae2Q5LlOVTTrtRDLNmF6Pd Received-SPF: none client-ip=212.227.17.13; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell The handling of the FPU state in sparc64_get_context() and sparc64_set_context() is not the same as what the kernel actually does: we unconditionally read and write the FP registers and the FSR, GSR and FPRS, but the kernel logic is more complicated: * in get_context the kernel has code for saving FPU registers, but it is hidden inside an "if (fenab) condition and the fenab flag is always set to 0 (inside an "#if 1" which has been in the kernel for over 15 years). So the effect is that the FPU state part is always written as zeroes. * in set_context the kernel looks at the fenab field in the structure from the guest, and only restores the state if it is set; it also looks at the structure's FPRS to see whether either the upper or lower or both halves of the register file have valid data. Bring our implementations into line with the kernel: * in get_context: - clear the entire target_ucontext at the top of the function (as the kernel does) - then don't write the FPU state, so those fields remain zero - this fixes Coverity issue CID 1432305 by deleting the code it was complaining about * in set_context: - check the fenab and the fpsr to decide which parts of the FPU data to restore, if any - instead of setting the FPU registers by doing two 32-bit loads and filling in the .upper and .lower parts of the CPU_Double union separately, just do a 64-bit load of the whole register at once. This fixes Coverity issue CID 1432303 because we now access the dregs[] part of the mcfpu_fregs union rather than the sregs[] part (which is not large enough to actually cover the whole of the data, so we were accessing off the end of sregs[]) We change both functions in a single commit to avoid potentially breaking bisection. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-Id: <20201106152738.26026-2-peter.maydell@linaro.org> [lv: fix FPRS_DU loop s/31/32/] Signed-off-by: Laurent Vivier --- linux-user/sparc/signal.c | 74 +++++++++++++++++++++++---------------- target/sparc/cpu.h | 4 ++- 2 files changed, 46 insertions(+), 32 deletions(-) -- 2.29.2 diff --git a/linux-user/sparc/signal.c b/linux-user/sparc/signal.c index d12adc8e6ff9..0057b48fad93 100644 --- a/linux-user/sparc/signal.c +++ b/linux-user/sparc/signal.c @@ -402,8 +402,10 @@ void sparc64_set_context(CPUSPARCState *env) abi_ulong ucp_addr; struct target_ucontext *ucp; target_mc_gregset_t *grp; + target_mc_fpu_t *fpup; abi_ulong pc, npc, tstate; unsigned int i; + unsigned char fenab; ucp_addr = env->regwptr[WREG_O0]; if (!lock_user_struct(VERIFY_READ, ucp, ucp_addr, 1)) { @@ -467,26 +469,42 @@ void sparc64_set_context(CPUSPARCState *env) __get_user(env->regwptr[WREG_FP], &(ucp->tuc_mcontext.mc_fp)); __get_user(env->regwptr[WREG_I7], &(ucp->tuc_mcontext.mc_i7)); - /* FIXME this does not match how the kernel handles the FPU in - * its sparc64_set_context implementation. In particular the FPU - * is only restored if fenab is non-zero in: - * __get_user(fenab, &(ucp->tuc_mcontext.mc_fpregs.mcfpu_enab)); - */ - __get_user(env->fprs, &(ucp->tuc_mcontext.mc_fpregs.mcfpu_fprs)); - { - uint32_t *src = ucp->tuc_mcontext.mc_fpregs.mcfpu_fregs.sregs; - for (i = 0; i < 64; i++, src++) { - if (i & 1) { - __get_user(env->fpr[i/2].l.lower, src); - } else { - __get_user(env->fpr[i/2].l.upper, src); + fpup = &ucp->tuc_mcontext.mc_fpregs; + + __get_user(fenab, &(fpup->mcfpu_enab)); + if (fenab) { + abi_ulong fprs; + + /* + * We use the FPRS from the guest only in deciding whether + * to restore the upper, lower, or both banks of the FPU regs. + * The kernel here writes the FPU register data into the + * process's current_thread_info state and unconditionally + * clears FPRS and TSTATE_PEF: this disables the FPU so that the + * next FPU-disabled trap will copy the data out of + * current_thread_info and into the real FPU registers. + * QEMU doesn't need to handle lazy-FPU-state-restoring like that, + * so we always load the data directly into the FPU registers + * and leave FPRS and TSTATE_PEF alone (so the FPU stays enabled). + * Note that because we (and the kernel) always write zeroes for + * the fenab and fprs in sparc64_get_context() none of this code + * will execute unless the guest manually constructed or changed + * the context structure. + */ + __get_user(fprs, &(fpup->mcfpu_fprs)); + if (fprs & FPRS_DL) { + for (i = 0; i < 16; i++) { + __get_user(env->fpr[i].ll, &(fpup->mcfpu_fregs.dregs[i])); + } + } + if (fprs & FPRS_DU) { + for (i = 16; i < 32; i++) { + __get_user(env->fpr[i].ll, &(fpup->mcfpu_fregs.dregs[i])); } } + __get_user(env->fsr, &(fpup->mcfpu_fsr)); + __get_user(env->gsr, &(fpup->mcfpu_gsr)); } - __get_user(env->fsr, - &(ucp->tuc_mcontext.mc_fpregs.mcfpu_fsr)); - __get_user(env->gsr, - &(ucp->tuc_mcontext.mc_fpregs.mcfpu_gsr)); unlock_user_struct(ucp, ucp_addr, 0); return; do_sigsegv: @@ -509,7 +527,9 @@ void sparc64_get_context(CPUSPARCState *env) if (!lock_user_struct(VERIFY_WRITE, ucp, ucp_addr, 0)) { goto do_sigsegv; } - + + memset(ucp, 0, sizeof(*ucp)); + mcp = &ucp->tuc_mcontext; grp = &mcp->mc_gregs; @@ -572,19 +592,11 @@ void sparc64_get_context(CPUSPARCState *env) __put_user(env->regwptr[WREG_FP], &(mcp->mc_fp)); __put_user(env->regwptr[WREG_I7], &(mcp->mc_i7)); - { - uint32_t *dst = ucp->tuc_mcontext.mc_fpregs.mcfpu_fregs.sregs; - for (i = 0; i < 64; i++, dst++) { - if (i & 1) { - __put_user(env->fpr[i/2].l.lower, dst); - } else { - __put_user(env->fpr[i/2].l.upper, dst); - } - } - } - __put_user(env->fsr, &(mcp->mc_fpregs.mcfpu_fsr)); - __put_user(env->gsr, &(mcp->mc_fpregs.mcfpu_gsr)); - __put_user(env->fprs, &(mcp->mc_fpregs.mcfpu_fprs)); + /* + * We don't write out the FPU state. This matches the kernel's + * implementation (which has the code for doing this but + * hidden behind an "if (fenab)" where fenab is always 0). + */ if (err) goto do_sigsegv; diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index b9369398f24b..277254732b93 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -156,7 +156,9 @@ enum { #define PS_IE (1<<1) #define PS_AG (1<<0) /* v9, zero on UA2007 */ -#define FPRS_FEF (1<<2) +#define FPRS_DL (1 << 0) +#define FPRS_DU (1 << 1) +#define FPRS_FEF (1 << 2) #define HS_PRIV (1<<2) #endif From patchwork Fri Dec 18 10:24:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 345450 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp1993083jai; Fri, 18 Dec 2020 02:29:26 -0800 (PST) X-Google-Smtp-Source: ABdhPJz5c9aOH6puSWLkBvnCCmEZ28Ph6UT7Jri6H2hGfsYdnX4nVBa7epWBbjZnhqdYsKIM++SV X-Received: by 2002:a5b:eca:: with SMTP id a10mr4874368ybs.447.1608287366389; Fri, 18 Dec 2020 02:29:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608287366; cv=none; d=google.com; s=arc-20160816; b=Uwk+aFRdT3MEUGDb9EjypexLSJW/Boq657hAyhowDJtvoGYH9ertt0a9wVIX6o0wvQ +D2NEW8+PO3hGR7tM9XZ16ptjDZyg/tP2V/FDCqswEiMGnrGfZ1zojO6hEjdsCVfbKhc zLfVGh0bFQgcB0zefawjE465xwMZ2nrAHBz16eX2PeIIBjIV5A9Wz24HeajWTsyhx/gp v8AxWfFyZTaK42cwD8O9VcSHWKVSsRvGpQm5N7+KtJLGcrgJZTWlHgOgB5JCHlyRkewj 42JPeokCgA3f4iaWbWGPjuDdbL4sBTIYepEhLVXTkUhcdwTukFdHntUOE7vDfBg/FcV0 5opg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from; bh=AUEbRBikd8YLSJ1RPqxuTNZ75m3UMG8Mk4wOgtCzF/8=; b=RJ72shUrigrVaBVU4soOzVPkScZZcZeUQlZPYEJk30drS/3FJ7zHknEeL5WoO3FIda xsbsvl7uW/8Zy5vdbELqRB0wtyE9ya7b3MFdfr4nkydYmz4ey6D+0Hs221PDElXiRhVL JE09VUdXbS8Sodmo8jhKKcWtcKLmFncppEU8YLW0I789xR5+cvVxZfQT4tcAG2TgPe3G RewUO3trgiriEabsWXviOvMolsgMZ1i85AYBZftqSJjvg0t/d9bdk8spK5F5fktFhLLw 7iXIx7l143dbFyPif/Mgg3NuWKh6cumzcakljz/3AlrnugK5xhpzDjBK+JO9KeeEKjZS rtTQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r130si8545242ybr.472.2020.12.18.02.29.26 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 18 Dec 2020 02:29:26 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:60108 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqD0n-0001VP-S1 for patch@linaro.org; Fri, 18 Dec 2020 05:29:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43938) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kqCvu-0002z8-3c for qemu-devel@nongnu.org; Fri, 18 Dec 2020 05:24:22 -0500 Received: from mout.kundenserver.de ([212.227.17.24]:32927) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kqCvq-00074F-0c for qemu-devel@nongnu.org; Fri, 18 Dec 2020 05:24:21 -0500 Received: from localhost.localdomain ([82.252.144.198]) by mrelayeu.kundenserver.de (mreue109 [212.227.15.183]) with ESMTPSA (Nemesis) id 1MS3rB-1kg8pw3gOB-00TUuF; Fri, 18 Dec 2020 11:24:16 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 12/14] linux-user/sparc: Remove unneeded checks of 'err' from sparc64_get_context() Date: Fri, 18 Dec 2020 11:24:05 +0100 Message-Id: <20201218102407.597566-13-laurent@vivier.eu> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201218102407.597566-1-laurent@vivier.eu> References: <20201218102407.597566-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:ZmAq9ybs8O5o28NnMQotEu1ugm4XdPERtwd950RO8gEeC4I8rcD YUcRpcQiQFywXZkcukoicbqYh/sHIk7diteQmJWrCs5UbCdqpezSibVoO3UI460FULRuoqC 6O/fZriYmLZ4x8Wz8D09JT1oLEDTmUkVtRKcaxNYLFHYhYHOkb+O5RkU68WfN78VeUXQdMT zMEyMnHoFxsOptUK/pKVQ== X-UI-Out-Filterresults: notjunk:1; V03:K0:ztmoiu/l2bA=:KI5SRkyExS5Sv0iD3WzIDW R7f+Yi/8EqmncTKNUovIAqI2nvbkpqqfEiswX2Ufew77C6mGS7MgjKJetZvKTlaZ432um/480 rvtJGU1x1lzW9JAk5xauJi/hrnnY3z+AzZKkH7Nzhw3DEicE9yLQYjFpZG7e3lnB/6eaENnBq PCAwyQetCEv54j6KIx/keN4PkUvEFj6g7+coTFSNk9ubzWSmWdk43qQGyNZSWX1OLmPoxsjJ0 r3aEeNgWh5TAasdkDfWWh5svg+YMfBJuG/gzoz0TuKQHELZwjHILbv6LWCnqVZYFEpxqrfMHh ZusrLZ6br+Qp/uBD3nP3GPqOdKNA7iqWvqG7laZ/3BXCD3PwFJKA6XlmU6DGv5T4wR1brbkog Sz0l8it6kYEcotG59GJYX/C8s7xM+rc/f6PN4pJP82R2yLfhzweZImQEVndtMcXUzXBYlaMcW 2csR2wsDbw== Received-SPF: none client-ip=212.227.17.24; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell Unlike the kernel macros, our __get_user() and __put_user() do not return a failure code. Kernel code typically has a style of err |= __get_user(...); err |= __get_user(...); and then checking err at the end. In sparc64_get_context() our version of the code dropped the accumulating into err but left the "if (err) goto do_sigsegv" checks, which will never be taken. Delete unnecessary if()s. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-Id: <20201106152738.26026-3-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier --- linux-user/sparc/signal.c | 4 ---- 1 file changed, 4 deletions(-) -- 2.29.2 diff --git a/linux-user/sparc/signal.c b/linux-user/sparc/signal.c index 0057b48fad93..58b48afe29c9 100644 --- a/linux-user/sparc/signal.c +++ b/linux-user/sparc/signal.c @@ -555,8 +555,6 @@ void sparc64_get_context(CPUSPARCState *env) for (i = 0; i < TARGET_NSIG_WORDS; i++, dst++, src++) { __put_user(*src, dst); } - if (err) - goto do_sigsegv; } /* XXX: tstate must be saved properly */ @@ -598,8 +596,6 @@ void sparc64_get_context(CPUSPARCState *env) * hidden behind an "if (fenab)" where fenab is always 0). */ - if (err) - goto do_sigsegv; unlock_user_struct(ucp, ucp_addr, 1); return; do_sigsegv: From patchwork Fri Dec 18 10:24:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 345448 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp1991502jai; Fri, 18 Dec 2020 02:26:49 -0800 (PST) X-Google-Smtp-Source: ABdhPJxLnTppaJQNNnnSIBAv6aNqdNkFnKRgxl2tCBdFDvoeoi91RHu2zOqI7U94C3a2fzMWDzRG X-Received: by 2002:a25:e910:: with SMTP id n16mr5134832ybd.269.1608287209734; Fri, 18 Dec 2020 02:26:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608287209; cv=none; d=google.com; s=arc-20160816; b=dHJ9fkdIjLr5cpWZu7zKoklihkSJXZwCI1ycNn9oMBqhsC5DRVp/x0HH+X3jqN5rgG yu+WwGqmMriffyTMy7eAFCdBJVvCtAwKm0Skjz94iGrB/yf86xEyEYa7e2LpBaLZBGY9 9wu760BcinNm0iTnUgi9wxKDq7SavGO6hlDfwtt+bEzcnpAJch9PWCMhojuPI9i3JMPu 36/p3vQbQ0okDuBEhyBQM8LrMMbLMzfWX5flSO3f1jy5kb2RDqkBxRkO0MAt8poB9zef h/zX3CIKyRUDfd6SlKsZIzfLNKaE0Jaw4ZC4aX7uB/m6GtG+tsveddVoyxYILDWgT1RA suWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from; bh=mFsk1yrfFHEtR0LD7F+lqC+G8jiRdmtdZJeu+/6yFJk=; b=rBwMThhFj/CG+BRhwp2yQvj6qZaXYwklx/oxD4Dlt+Y1q5id0mOPw393fFY3kKJwJB AqbxDkw/pxnlG7o3mCYrDJbwR30CTEo/Jvj73eFmWUhWABQWizLt7bov8hCOkvWFoQsu y0P3UV1yp7DLG3KHmyxWd09sx9PA+f2XLu57Iqd1ZqVdZjXwVua5eyni89YdICpewfW4 exbLZz+AG6wFmCWWQWOdEjnXgiVebC5HRLyjBamz8bcDKiP0H468sDM/1xmxaS8TNNoI jkx/hihk6NALCsDs4HFpAb+/5yZ+L88CBxaA/QiglXAI61cf7gJUJppa0Yb63ibbA87W foCg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x6si8411418ybo.478.2020.12.18.02.26.49 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 18 Dec 2020 02:26:49 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:51112 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqCyH-0006Hk-6y for patch@linaro.org; Fri, 18 Dec 2020 05:26:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43970) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kqCvv-00032N-OR for qemu-devel@nongnu.org; Fri, 18 Dec 2020 05:24:23 -0500 Received: from mout.kundenserver.de ([217.72.192.74]:42843) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kqCvq-00074d-T6 for qemu-devel@nongnu.org; Fri, 18 Dec 2020 05:24:23 -0500 Received: from localhost.localdomain ([82.252.144.198]) by mrelayeu.kundenserver.de (mreue109 [212.227.15.183]) with ESMTPSA (Nemesis) id 1MRTEp-1kTTNd1fmP-00NV9V; Fri, 18 Dec 2020 11:24:16 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 13/14] linux-user/sparc: Don't restore %g7 in sparc64_set_context() Date: Fri, 18 Dec 2020 11:24:06 +0100 Message-Id: <20201218102407.597566-14-laurent@vivier.eu> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201218102407.597566-1-laurent@vivier.eu> References: <20201218102407.597566-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:bhY+mFh4+79meoAigyLRoy7nfbcBXT9YT0XkjqwgRpkXBO8kAHo cSGLSopnN3QQafTXqtdUu2Ar7boCUawUF1+T5Y9t7Bi78zkUxljAbWi0nlc0CKLw1g6u5Z0 sSjSOhNw5qDQRLLFb2jbJyYzOGOVoKNVS8VpKCjaY2Zspr8VolmcrT+FeS72TEZ/Va7I+v7 7S7SeoZMPSFgvNL1JFy6w== X-UI-Out-Filterresults: notjunk:1; V03:K0:Q2Kw8nzRnxg=:6Ocwacmuloa0YLKVmTV7su HL0kr91dcwog4oqgYwF+N+qB7xLr2cGFgbBkUw7I9gcrQsvxjVgH2zuouNoCMokOLGGXG2nX0 NOKY0DncEQ6DJnZJgTG/qMyXvmYdQyic0DZeyl7s+HP5zMSA3cPqxkYLZAPxLe2tDQUKlyKH/ uTesRmLyyerBLlSI4foLXjnMSZiQHRwFwfwPQUYeoT7AtAr3a7RJNSwheGG7XzTcpTLglHCrX fA9cxBcvDGsEOsXqZjvI84E0GgtQSh9z3Xs8bZlfDm25q+1ljNlp0WnB5QsXTMYXjinwb/VTc AnWHxVRlVFrGCNpReI2oZFj+9ndvJJD7uaGGjaFVahaHzjTqGAlYaotOHyghYYSn1VCaM4r++ A9/tYXZ+efrlW1mCuZMPXt7SuMZLk1ZCBeiLPO24pwN3q6KsI0cpVTGiRjyuIYt4hvUZ8m46u 14+W3K2LzA== Received-SPF: none client-ip=217.72.192.74; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell The kernel does not restore the g7 register in sparc64_set_context(); neither should we. (We still save it in sparc64_get_context().) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-Id: <20201106152738.26026-4-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier --- linux-user/sparc/signal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.29.2 diff --git a/linux-user/sparc/signal.c b/linux-user/sparc/signal.c index 58b48afe29c9..d92e096cafa7 100644 --- a/linux-user/sparc/signal.c +++ b/linux-user/sparc/signal.c @@ -447,7 +447,7 @@ void sparc64_set_context(CPUSPARCState *env) __get_user(env->gregs[4], (&(*grp)[SPARC_MC_G4])); __get_user(env->gregs[5], (&(*grp)[SPARC_MC_G5])); __get_user(env->gregs[6], (&(*grp)[SPARC_MC_G6])); - __get_user(env->gregs[7], (&(*grp)[SPARC_MC_G7])); + /* Skip g7 as that's the thread register in userspace */ /* * Note that unlike the kernel, we didn't need to mess with the From patchwork Fri Dec 18 10:24:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 345451 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp1994241jai; Fri, 18 Dec 2020 02:30:56 -0800 (PST) X-Google-Smtp-Source: ABdhPJxJ2gAADxaNfDkXOJcJJ1diN51Fj5C3Jr2fld6lAN6CDHyw0cserwZX+zruM3heW6zD1VAx X-Received: by 2002:a25:bc0d:: with SMTP id i13mr5087440ybh.358.1608287456408; Fri, 18 Dec 2020 02:30:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608287456; cv=none; d=google.com; s=arc-20160816; b=GiZL3FpyIAHL+s4P1e2oqluTxiIo+LCAsTfpH7UgYXB6XM7dt3N4PPLp+DTtHRQXln +8s6TQgmBEuUtKotJgV5qjOVSCUsIKO8V9yL/mt+uahjSvoFiWnc5f1NaNNZ6YhXcUrd bIGMpTeFDKbquHjJJg818gs1aSw0MXwDlDcw/5fE8zDFMCADg0b4aIXbGEZKehVNx5Wz 0PaXfZgHMvNsY+Hwd2F3onFKuYtHMzctgolO6wUBzhch2a+OzAxyKwg3J/ta9Zr19cC8 w2OLOS24UYzRS7EZBti4K7T2gaEcAbUkQ5zhlsDtObMJYO9e5118zzo7+jd5IrWU5qTV sZjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from; bh=M4qIxIQXPAJUuuw2D/opaTFB1bUAgmadSXKkME91BDc=; b=aapj4k5M4wdDyyY0lPb/HxNWwxidsDFsIvMls/6JQM+OyexdkeLL0waMe9l+vRvq7l ZyG5TofkLiOwl/SnMSt8pm/DpXW1/U2+kJo625S+6NClwaAbOqYcTNXHkZ2CrhOpdOef Aq/az6bfC4EzCE1GndNdgRzSQvsfqcpFEsOG3LsYNEOQbKpoH4M0plaPehkQMQouqKd8 l7VlaLEjl2zYfL+ayYoG0z75t6jSv1e9+y8K2dfy4I2eAGBjL3JGRfV3j3AIJaJGD6OS j3WxGe1UvZGsuCsA/XmdVsyt59HDCxjLBP9K7URu2PeR6NTHlB6dGMxt0iDgclOPDAL1 0M2w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j2si7526387ybg.188.2020.12.18.02.30.56 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 18 Dec 2020 02:30:56 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:39746 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kqD2F-0004ne-LW for patch@linaro.org; Fri, 18 Dec 2020 05:30:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43978) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kqCvw-00033E-4C for qemu-devel@nongnu.org; Fri, 18 Dec 2020 05:24:24 -0500 Received: from mout.kundenserver.de ([217.72.192.75]:43369) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kqCvq-00074i-Vr for qemu-devel@nongnu.org; Fri, 18 Dec 2020 05:24:23 -0500 Received: from localhost.localdomain ([82.252.144.198]) by mrelayeu.kundenserver.de (mreue109 [212.227.15.183]) with ESMTPSA (Nemesis) id 1MmU9X-1kPyrp3bbl-00iQFx; Fri, 18 Dec 2020 11:24:17 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 14/14] linux-user/sparc: Handle tstate in sparc64_get/set_context() Date: Fri, 18 Dec 2020 11:24:07 +0100 Message-Id: <20201218102407.597566-15-laurent@vivier.eu> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201218102407.597566-1-laurent@vivier.eu> References: <20201218102407.597566-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:pIyHsYTh+HsHo3ROoPHIIZFVmmdDt9VfxWKsbQU9GtPva/e2r9C JFjiFG7TExdMFEasjcqJ6PduiAMdudLnmY30Np2QNk3X72XUhyBL0yTHvNcyKOLUSBdwkOZ sLavxvcs3kQzhpDyUJ6soh/IuVWF1F+ue8Um5CO3lctmcaCFrDiD1kShsqGCMLvRZx0Uzv4 Qe2d8N6140vcS50uFVwCw== X-UI-Out-Filterresults: notjunk:1; V03:K0:oT+m3Whhm7o=:8fOxOQ7A6GX3SxVGDKxsvr BKVipxytri2Mxem1bQ4rMTj+xTnFki+VifuDwEfOasY/Qrx+R9LXMK0o6GBAnuS6ZJr+DWNGE mN9SK/4ZW90gsqjnP99R5VhmD672czqfG2LVqvNedznCoccgkb4GL6YL/eAq1gHGHM8GG4hvw Ol+UF/vhq/sM7RnTz8MlDsKyxl7wLD43Pf08wCxOnuXtr89j8Za4A1DxTGiQAKqBN5Zpyz236 bBwwe2pnr09MJoAt4MDx7PG3PCjwqFMtoM1s1onQ4T82ij7NtXYKxRPHwsHuasbK6umU/B94Y KF700yEMLcMAelWyKXg0eIcFVUmxLb33T6AxS6X5BDW6H3tePPrrsUqkQHz0MY6W6C/eXqXZt vNedHFYwNc9AGjYNOKCgPuiWiRNuM+zXE7kCXTZeQZdHrEFygoHjdF/d/0L3d6FJlW9Kc3Zh+ k2VwxlgQRg== Received-SPF: none client-ip=217.72.192.75; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell Correctly implement save/restore of the tstate field in sparc64_get_context() and sparc64_set_context(): * Don't use the CWP value from the guest in set_context * Construct and save a tstate value rather than leaving it as zero in get_context To do this we factor out the "calculate TSTATE value from CPU state" code from sparc_cpu_do_interrupt() into its own sparc64_tstate() function; that in turn requires us to move some of the function prototypes out from inside a CPU_NO_IO_DEFS ifdef guard. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-Id: <20201106152738.26026-5-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier --- linux-user/sparc/signal.c | 7 +++---- target/sparc/cpu.h | 24 ++++++++++++++++++++---- target/sparc/int64_helper.c | 5 +---- 3 files changed, 24 insertions(+), 12 deletions(-) -- 2.29.2 diff --git a/linux-user/sparc/signal.c b/linux-user/sparc/signal.c index d92e096cafa7..d27b7a3af79d 100644 --- a/linux-user/sparc/signal.c +++ b/linux-user/sparc/signal.c @@ -438,9 +438,9 @@ void sparc64_set_context(CPUSPARCState *env) env->npc = npc; __get_user(env->y, &((*grp)[SPARC_MC_Y])); __get_user(tstate, &((*grp)[SPARC_MC_TSTATE])); + /* Honour TSTATE_ASI, TSTATE_ICC and TSTATE_XCC only */ env->asi = (tstate >> 24) & 0xff; - cpu_put_ccr(env, tstate >> 32); - cpu_put_cwp64(env, tstate & 0x1f); + cpu_put_ccr(env, (tstate >> 32) & 0xff); __get_user(env->gregs[1], (&(*grp)[SPARC_MC_G1])); __get_user(env->gregs[2], (&(*grp)[SPARC_MC_G2])); __get_user(env->gregs[3], (&(*grp)[SPARC_MC_G3])); @@ -557,8 +557,7 @@ void sparc64_get_context(CPUSPARCState *env) } } - /* XXX: tstate must be saved properly */ - // __put_user(env->tstate, &((*grp)[SPARC_MC_TSTATE])); + __put_user(sparc64_tstate(env), &((*grp)[SPARC_MC_TSTATE])); __put_user(env->pc, &((*grp)[SPARC_MC_PC])); __put_user(env->npc, &((*grp)[SPARC_MC_NPC])); __put_user(env->y, &((*grp)[SPARC_MC_Y])); diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 277254732b93..4b2290650be4 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -608,10 +608,6 @@ target_ulong cpu_get_psr(CPUSPARCState *env1); void cpu_put_psr(CPUSPARCState *env1, target_ulong val); void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val); #ifdef TARGET_SPARC64 -target_ulong cpu_get_ccr(CPUSPARCState *env1); -void cpu_put_ccr(CPUSPARCState *env1, target_ulong val); -target_ulong cpu_get_cwp64(CPUSPARCState *env1); -void cpu_put_cwp64(CPUSPARCState *env1, int cwp); void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate); void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl); #endif @@ -829,4 +825,24 @@ static inline bool tb_am_enabled(int tb_flags) #endif } +#ifdef TARGET_SPARC64 +/* win_helper.c */ +target_ulong cpu_get_ccr(CPUSPARCState *env1); +void cpu_put_ccr(CPUSPARCState *env1, target_ulong val); +target_ulong cpu_get_cwp64(CPUSPARCState *env1); +void cpu_put_cwp64(CPUSPARCState *env1, int cwp); + +static inline uint64_t sparc64_tstate(CPUSPARCState *env) +{ + uint64_t tstate = (cpu_get_ccr(env) << 32) | + ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | + cpu_get_cwp64(env); + + if (env->def.features & CPU_FEATURE_GL) { + tstate |= (env->gl & 7ULL) << 40; + } + return tstate; +} +#endif + #endif diff --git a/target/sparc/int64_helper.c b/target/sparc/int64_helper.c index ba95bf228cc4..7fb8ab211ca8 100644 --- a/target/sparc/int64_helper.c +++ b/target/sparc/int64_helper.c @@ -131,9 +131,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) } tsptr = cpu_tsptr(env); - tsptr->tstate = (cpu_get_ccr(env) << 32) | - ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | - cpu_get_cwp64(env); + tsptr->tstate = sparc64_tstate(env); tsptr->tpc = env->pc; tsptr->tnpc = env->npc; tsptr->tt = intno; @@ -148,7 +146,6 @@ void sparc_cpu_do_interrupt(CPUState *cs) } if (env->def.features & CPU_FEATURE_GL) { - tsptr->tstate |= (env->gl & 7ULL) << 40; cpu_gl_switch_gregs(env, env->gl + 1); env->gl++; }