From patchwork Sat Mar 25 16:18:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Semwal X-Patchwork-Id: 95978 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp532077qgd; Sat, 25 Mar 2017 09:19:00 -0700 (PDT) X-Received: by 10.98.61.5 with SMTP id k5mr16132713pfa.229.1490458740618; Sat, 25 Mar 2017 09:19:00 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3si6723034pli.62.2017.03.25.09.18.59; Sat, 25 Mar 2017 09:19:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751302AbdCYQS7 (ORCPT + 5 others); Sat, 25 Mar 2017 12:18:59 -0400 Received: from mail-pf0-f170.google.com ([209.85.192.170]:35213 "EHLO mail-pf0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751277AbdCYQS7 (ORCPT ); Sat, 25 Mar 2017 12:18:59 -0400 Received: by mail-pf0-f170.google.com with SMTP id 20so7964926pfk.2 for ; Sat, 25 Mar 2017 09:18:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+Ja33mHEH06j9qL8t4Toqcgu3xamT3bzrV/0zV7Z1X4=; b=kwIfeEt2aUEsLY4+nm8gCVMFxlARk+jjo5ACqaa1ti3OZE2bQRlZ4xPZkaLwEzLLB5 Yu9sTK2EDMq61tKJaLWrl3hKh5MNzL4JA7QlMHFl4fnVNb1oq36QOA9J7AKghFOmRKqO 0j0eYgVFDg8CUCWvcOpnsADOAEgjgUl4DGGb0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+Ja33mHEH06j9qL8t4Toqcgu3xamT3bzrV/0zV7Z1X4=; b=YYzbLlW1DIrXmX4Au5FveY6X+9+CXEkm+YHjgvK8S3oUuN2PentDmji8UsYyL0guFV e1brY+eN0IKVhLkmKEg3c1b1xOsl+UkZT4XH1shYH9F8PKplGyJCH+BAxDAxieD7hbZK 1eJ8zVZQ4Sro0ulPu+RGJVUFVkoY4iKgSMM96lTeXaVcCaEbYAjzNr8/3zGXg+Ys476R /jNgr7KMt2MYH5nLlpZtQxiKPUzmCeTWGzpc0n4znfcNAewN1HHOAhEtGPkA+k1Y4dBI dTeTdrpN5kzWwIgKqEzwopUnEfFR0hRmH5NnvOFClj0LL8bTfmJmqqCDias3xGcsahLI gNeA== X-Gm-Message-State: AFeK/H0/uPn6KeJClTXBYTv65agb7PXr0UBSCJ0xxriZWShs6xH6KekPs2NbeddkfFHSPYje X-Received: by 10.99.101.67 with SMTP id z64mr15570375pgb.78.1490458737322; Sat, 25 Mar 2017 09:18:57 -0700 (PDT) Received: from phantom.lan ([106.51.225.38]) by smtp.gmail.com with ESMTPSA id q194sm11469541pfq.43.2017.03.25.09.18.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 25 Mar 2017 09:18:56 -0700 (PDT) From: Sumit Semwal To: stable@vger.kernel.org Cc: Dan Streetman , Dan Streetman , Boris Ostrovsky , Sasha Levin , Greg Kroah-Hartman , Sumit Semwal Subject: [PATCH for-4.4 01/19] xen: do not re-use pirq number cached in pci device msi msg data Date: Sat, 25 Mar 2017 21:48:01 +0530 Message-Id: <1490458699-24484-2-git-send-email-sumit.semwal@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> References: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Dan Streetman [ Upstream commit c74fd80f2f41d05f350bb478151021f88551afe8 ] Revert the main part of commit: af42b8d12f8a ("xen: fix MSI setup and teardown for PV on HVM guests") That commit introduced reading the pci device's msi message data to see if a pirq was previously configured for the device's msi/msix, and re-use that pirq. At the time, that was the correct behavior. However, a later change to Qemu caused it to call into the Xen hypervisor to unmap all pirqs for a pci device, when the pci device disables its MSI/MSIX vectors; specifically the Qemu commit: c976437c7dba9c7444fb41df45468968aaa326ad ("qemu-xen: free all the pirqs for msi/msix when driver unload") Once Qemu added this pirq unmapping, it was no longer correct for the kernel to re-use the pirq number cached in the pci device msi message data. All Qemu releases since 2.1.0 contain the patch that unmaps the pirqs when the pci device disables its MSI/MSIX vectors. This bug is causing failures to initialize multiple NVMe controllers under Xen, because the NVMe driver sets up a single MSIX vector for each controller (concurrently), and then after using that to talk to the controller for some configuration data, it disables the single MSIX vector and re-configures all the MSIX vectors it needs. So the MSIX setup code tries to re-use the cached pirq from the first vector for each controller, but the hypervisor has already given away that pirq to another controller, and its initialization fails. This is discussed in more detail at: https://lists.xen.org/archives/html/xen-devel/2017-01/msg00447.html Fixes: af42b8d12f8a ("xen: fix MSI setup and teardown for PV on HVM guests") Signed-off-by: Dan Streetman Reviewed-by: Stefano Stabellini Acked-by: Konrad Rzeszutek Wilk Signed-off-by: Boris Ostrovsky Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sumit Semwal --- arch/x86/pci/xen.c | 23 +++++++---------------- 1 file changed, 7 insertions(+), 16 deletions(-) -- 2.7.4 diff --git a/arch/x86/pci/xen.c b/arch/x86/pci/xen.c index c6d6efe..7575f07 100644 --- a/arch/x86/pci/xen.c +++ b/arch/x86/pci/xen.c @@ -231,23 +231,14 @@ static int xen_hvm_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) return 1; for_each_pci_msi_entry(msidesc, dev) { - __pci_read_msi_msg(msidesc, &msg); - pirq = MSI_ADDR_EXT_DEST_ID(msg.address_hi) | - ((msg.address_lo >> MSI_ADDR_DEST_ID_SHIFT) & 0xff); - if (msg.data != XEN_PIRQ_MSI_DATA || - xen_irq_from_pirq(pirq) < 0) { - pirq = xen_allocate_pirq_msi(dev, msidesc); - if (pirq < 0) { - irq = -ENODEV; - goto error; - } - xen_msi_compose_msg(dev, pirq, &msg); - __pci_write_msi_msg(msidesc, &msg); - dev_dbg(&dev->dev, "xen: msi bound to pirq=%d\n", pirq); - } else { - dev_dbg(&dev->dev, - "xen: msi already bound to pirq=%d\n", pirq); + pirq = xen_allocate_pirq_msi(dev, msidesc); + if (pirq < 0) { + irq = -ENODEV; + goto error; } + xen_msi_compose_msg(dev, pirq, &msg); + __pci_write_msi_msg(msidesc, &msg); + dev_dbg(&dev->dev, "xen: msi bound to pirq=%d\n", pirq); irq = xen_bind_pirq_msi_to_irq(dev, msidesc, pirq, (type == PCI_CAP_ID_MSI) ? nvec : 1, (type == PCI_CAP_ID_MSIX) ? From patchwork Sat Mar 25 16:18:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Semwal X-Patchwork-Id: 95979 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp532084qgd; Sat, 25 Mar 2017 09:19:02 -0700 (PDT) X-Received: by 10.84.195.1 with SMTP id i1mr18060905pld.176.1490458742390; Sat, 25 Mar 2017 09:19:02 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3si6723034pli.62.2017.03.25.09.19.02; Sat, 25 Mar 2017 09:19:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751303AbdCYQTC (ORCPT + 5 others); Sat, 25 Mar 2017 12:19:02 -0400 Received: from mail-pg0-f41.google.com ([74.125.83.41]:36062 "EHLO mail-pg0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751277AbdCYQTB (ORCPT ); Sat, 25 Mar 2017 12:19:01 -0400 Received: by mail-pg0-f41.google.com with SMTP id g2so9133216pge.3 for ; Sat, 25 Mar 2017 09:19:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jS19mTwGYrj4XVR7yfhmXcJXGtRsnsqeCPL/4I7RaGs=; b=dmY+UTlQv6iN56qk66JV08HtzYLtd1AKBYylIDOmfPMt0EbJhqU34ybcPtJfA9/1up gs0K6c4ZKTsBp6vCustVZKgJxvM3xiO53utGobkLSM1+Btw6WjfJ3aoiqctY7b2ScCT7 ixh7okOCS0/49vsaZCXmQVJHd0Xgzxh7z4lo4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jS19mTwGYrj4XVR7yfhmXcJXGtRsnsqeCPL/4I7RaGs=; b=nSwvPkR4CGEjb34t7yoH4M8k16IjFI+Ru+i1Dojp0oCAfhqLUYdv6E1edu8Ml2vjyI KKzURELqC2Ax43GMiskTishxxC49ZfyB/mp31TdwnKE6gXXg/LksL8uYGzo791KvgAQm teDF88jvC9jKQDrvNPpFXSbpOkkGokx2ER5BC4wR4KtsISMypLdgMQN7Q/5avpGm/wKk aXyo9Go28HQ3yG5zXALXJBPaD3Nhzez0e860t6khYpPxFHgFQgemJtY6sXqzqfD9eRiD Pa0N5OSrBwhF0e/jkw1xEpF0OBzHATBueEotCsDDR6j4giFYu+om2v81uR9A8JK30Acc cpbA== X-Gm-Message-State: AFeK/H3RLFD1owy8WbcbfF+96dUO0Bk3k6wBTTQ/bUk73s4i2eUYULWoAP+21wcxL+0F6HaC X-Received: by 10.99.67.6 with SMTP id q6mr15396364pga.156.1490458740307; Sat, 25 Mar 2017 09:19:00 -0700 (PDT) Received: from phantom.lan ([106.51.225.38]) by smtp.gmail.com with ESMTPSA id q194sm11469541pfq.43.2017.03.25.09.18.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 25 Mar 2017 09:18:59 -0700 (PDT) From: Sumit Semwal To: stable@vger.kernel.org Cc: Chris J Arges , Jeff Kirsher , Sasha Levin , Greg Kroah-Hartman , Sumit Semwal Subject: [PATCH for-4.4 02/19] igb: Workaround for igb i210 firmware issue Date: Sat, 25 Mar 2017 21:48:02 +0530 Message-Id: <1490458699-24484-3-git-send-email-sumit.semwal@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> References: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Chris J Arges [ Upstream commit 4e684f59d760a2c7c716bb60190783546e2d08a1 ] Sometimes firmware may not properly initialize I347AT4_PAGE_SELECT causing the probe of an igb i210 NIC to fail. This patch adds an addition zeroing of this register during igb_get_phy_id to workaround this issue. Thanks for Jochen Henneberg for the idea and original patch. Signed-off-by: Chris J Arges Tested-by: Aaron Brown Signed-off-by: Jeff Kirsher Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sumit Semwal --- drivers/net/ethernet/intel/igb/e1000_phy.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.7.4 diff --git a/drivers/net/ethernet/intel/igb/e1000_phy.c b/drivers/net/ethernet/intel/igb/e1000_phy.c index 23ec28f..13ad20b 100644 --- a/drivers/net/ethernet/intel/igb/e1000_phy.c +++ b/drivers/net/ethernet/intel/igb/e1000_phy.c @@ -77,6 +77,10 @@ s32 igb_get_phy_id(struct e1000_hw *hw) s32 ret_val = 0; u16 phy_id; + /* ensure PHY page selection to fix misconfigured i210 */ + if (hw->mac.type == e1000_i210) + phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0); + ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); if (ret_val) goto out; From patchwork Sat Mar 25 16:18:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Semwal X-Patchwork-Id: 95980 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp532100qgd; Sat, 25 Mar 2017 09:19:05 -0700 (PDT) X-Received: by 10.84.168.4 with SMTP id e4mr18371093plb.138.1490458745372; Sat, 25 Mar 2017 09:19:05 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3si6723034pli.62.2017.03.25.09.19.05; Sat, 25 Mar 2017 09:19:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751312AbdCYQTF (ORCPT + 5 others); Sat, 25 Mar 2017 12:19:05 -0400 Received: from mail-pf0-f170.google.com ([209.85.192.170]:34101 "EHLO mail-pf0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751277AbdCYQTE (ORCPT ); Sat, 25 Mar 2017 12:19:04 -0400 Received: by mail-pf0-f170.google.com with SMTP id p189so7998947pfp.1 for ; Sat, 25 Mar 2017 09:19:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CtDz0hyTqGfhP+bze3GLi0dvewdC27HU+qmWY6h08fI=; b=UofBbIq/K3/oIoantzTbsChci0Kw/dlDMsnfvwe0u/Ls76vEZlFXB8mlLYwH90Z/f8 ZKbOGwUoNTrgOA6EUwGV1nLw/Zq9fT3R+XV8i03yhB1eXn6e4aUYraTsO6/yj4E25D5P NW7l2iFOjY9ha/QxJP3jLAnNdK1TAzAumasjo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CtDz0hyTqGfhP+bze3GLi0dvewdC27HU+qmWY6h08fI=; b=rLNDY0ddtSRefH045Qq+H0PzuFPRRvON0rmZ8rgnBne3j+6LGb34oHlyzxeV4hu3CK TrFctmAsjBo2qVWyl7kP4nnHaian/bh9tN52J13Q+lDhGjk9HoLAtmj9DVoUg+PSwqjh GyGRlWogEbsRRw+B0Rpbve54lx/ZGBNEdcjYk5KwcxrWvj44+J6IFtDVsbRLiWBdogLG Tn75viWXKa2702WQCAueSQknJO2o/Ko1zXlRImhR/BndMb8dYjOaXE63nPsmiApFAOiP L///I01+r23Kp6/uvmZ9gy1PXCDeKLexQoWVVBLMrNfZ3lOnesXTrEJx5v6YJ1xj3Ttp +zvA== X-Gm-Message-State: AFeK/H03H9G4mHXorymlVLOSJYiGDieJbegoP9W42R+3PIxVPlVyE5ZYGG5Po1i8XPLNcvRA X-Received: by 10.84.174.131 with SMTP id r3mr18586173plb.136.1490458743303; Sat, 25 Mar 2017 09:19:03 -0700 (PDT) Received: from phantom.lan ([106.51.225.38]) by smtp.gmail.com with ESMTPSA id q194sm11469541pfq.43.2017.03.25.09.19.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 25 Mar 2017 09:19:02 -0700 (PDT) From: Sumit Semwal To: stable@vger.kernel.org Cc: Todd Fujinaka , Jeff Kirsher , Sasha Levin , Greg Kroah-Hartman , Sumit Semwal Subject: [PATCH for-4.4 03/19] igb: add i211 to i210 PHY workaround Date: Sat, 25 Mar 2017 21:48:03 +0530 Message-Id: <1490458699-24484-4-git-send-email-sumit.semwal@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> References: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Todd Fujinaka [ Upstream commit 5bc8c230e2a993b49244f9457499f17283da9ec7 ] i210 and i211 share the same PHY but have different PCI IDs. Don't forget i211 for any i210 workarounds. Signed-off-by: Todd Fujinaka Tested-by: Aaron Brown Signed-off-by: Jeff Kirsher Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sumit Semwal --- drivers/net/ethernet/intel/igb/e1000_phy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/net/ethernet/intel/igb/e1000_phy.c b/drivers/net/ethernet/intel/igb/e1000_phy.c index 13ad20b..afaa98d 100644 --- a/drivers/net/ethernet/intel/igb/e1000_phy.c +++ b/drivers/net/ethernet/intel/igb/e1000_phy.c @@ -78,7 +78,7 @@ s32 igb_get_phy_id(struct e1000_hw *hw) u16 phy_id; /* ensure PHY page selection to fix misconfigured i210 */ - if (hw->mac.type == e1000_i210) + if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0); ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); From patchwork Sat Mar 25 16:18:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Semwal X-Patchwork-Id: 95981 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp532119qgd; Sat, 25 Mar 2017 09:19:09 -0700 (PDT) X-Received: by 10.98.60.20 with SMTP id j20mr16230792pfa.128.1490458749730; Sat, 25 Mar 2017 09:19:09 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3si6723034pli.62.2017.03.25.09.19.09; Sat, 25 Mar 2017 09:19:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751319AbdCYQTJ (ORCPT + 5 others); Sat, 25 Mar 2017 12:19:09 -0400 Received: from mail-pg0-f41.google.com ([74.125.83.41]:34967 "EHLO mail-pg0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751309AbdCYQTJ (ORCPT ); Sat, 25 Mar 2017 12:19:09 -0400 Received: by mail-pg0-f41.google.com with SMTP id t143so9186332pgb.2 for ; Sat, 25 Mar 2017 09:19:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zltS76OQubzWAQGYvnRjWLd918OiUgM3BKWJ0VS3VUY=; b=FlYV6Hf9KxWWsy0Hkd6r4CvslEtkvogoAYBan8Dqi9pjZ5O2j5JZxBCd7MLFh9If0f t+4qsIbcCYiQaazBFIiIC0JKGg17qWUP8KYB7F95mPZoQ6ceM81iFy1KRFos0bGfSPDu anaNaeULCJhCppY6nOq573x6IZMw04Mj9jWwk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zltS76OQubzWAQGYvnRjWLd918OiUgM3BKWJ0VS3VUY=; b=Ctk0OBFzabQyO95ZSGFBqU1ias45OqwMqIkaAqgi7ZTe0izG3g21+4c+n6tTD0lzCJ E3q7QC1ed3CXFf0RdNh6pTz35bC1nazoCJVsAUuw8vUkqISjG2W4rgpVegyP1tmAigYw r7poiQzAP9l/j6hX4OiUK0YtPpz/sDsbAF3Y6wLe7rA808qvGzdHS6lp5AMnTyGl3SeC Rc6acplL1Q8KtYmVkTq9xT9uI+hUsuiMWwtr/7DW2dwpk3Dr295wrVN32ncuKwjLi8N9 d5U3JSgzBxM32wAkU9nMwbPEoR6ajHU+MyncaCfbm1BjZdfCKX+ehuPAaGQnejtRENUu 0PmQ== X-Gm-Message-State: AFeK/H0K/XmuFpZNxXI5mBxWno5Fky6bvFTRWfUy4YRcQqrwfBPcYhqLXEkRCRY625A23Gtk X-Received: by 10.84.217.216 with SMTP id d24mr18067614plj.80.1490458747160; Sat, 25 Mar 2017 09:19:07 -0700 (PDT) Received: from phantom.lan ([106.51.225.38]) by smtp.gmail.com with ESMTPSA id q194sm11469541pfq.43.2017.03.25.09.19.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 25 Mar 2017 09:19:06 -0700 (PDT) From: Sumit Semwal To: stable@vger.kernel.org Cc: Vitaly Kuznetsov , devel@linuxdriverproject.org, Haiyang Zhang , Thomas Gleixner , Ingo Molnar , Sasha Levin , Greg Kroah-Hartman , Sumit Semwal Subject: [PATCH for-4.4 04/19] x86/hyperv: Handle unknown NMIs on one CPU when unknown_nmi_panic Date: Sat, 25 Mar 2017 21:48:04 +0530 Message-Id: <1490458699-24484-5-git-send-email-sumit.semwal@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> References: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Vitaly Kuznetsov [ Upstream commit 59107e2f48831daedc46973ce4988605ab066de3 ] There is a feature in Hyper-V ('Debug-VM --InjectNonMaskableInterrupt') which injects NMI to the guest. We may want to crash the guest and do kdump on this NMI by enabling unknown_nmi_panic. To make kdump succeed we need to allow the kdump kernel to re-establish VMBus connection so it will see VMBus devices (storage, network,..). To properly unload VMBus making it possible to start over during kdump we need to do the following: - Send an 'unload' message to the hypervisor. This can be done on any CPU so we do this the crashing CPU. - Receive the 'unload finished' reply message. WS2012R2 delivers this message to the CPU which was used to establish VMBus connection during module load and this CPU may differ from the CPU sending 'unload'. Receiving a VMBus message means the following: - There is a per-CPU slot in memory for one message. This slot can in theory be accessed by any CPU. - We get an interrupt on the CPU when a message was placed into the slot. - When we read the message we need to clear the slot and signal the fact to the hypervisor. In case there are more messages to this CPU pending the hypervisor will deliver the next message. The signaling is done by writing to an MSR so this can only be done on the appropriate CPU. To avoid doing cross-CPU work on crash we have vmbus_wait_for_unload() function which checks message slots for all CPUs in a loop waiting for the 'unload finished' messages. However, there is an issue which arises when these conditions are met: - We're crashing on a CPU which is different from the one which was used to initially contact the hypervisor. - The CPU which was used for the initial contact is blocked with interrupts disabled and there is a message pending in the message slot. In this case we won't be able to read the 'unload finished' message on the crashing CPU. This is reproducible when we receive unknown NMIs on all CPUs simultaneously: the first CPU entering panic() will proceed to crash and all other CPUs will stop themselves with interrupts disabled. The suggested solution is to handle unknown NMIs for Hyper-V guests on the first CPU which gets them only. This will allow us to rely on VMBus interrupt handler being able to receive the 'unload finish' message in case it is delivered to a different CPU. The issue is not reproducible on WS2016 as Debug-VM delivers NMI to the boot CPU only, WS2012R2 and earlier Hyper-V versions are affected. Signed-off-by: Vitaly Kuznetsov Acked-by: K. Y. Srinivasan Cc: devel@linuxdriverproject.org Cc: Haiyang Zhang Link: http://lkml.kernel.org/r/20161202100720.28121-1-vkuznets@redhat.com Signed-off-by: Thomas Gleixner Signed-off-by: Ingo Molnar Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sumit Semwal --- arch/x86/kernel/cpu/mshyperv.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) -- 2.7.4 diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c index cfc4a96..83b5f7a 100644 --- a/arch/x86/kernel/cpu/mshyperv.c +++ b/arch/x86/kernel/cpu/mshyperv.c @@ -30,6 +30,7 @@ #include #include #include +#include struct ms_hyperv_info ms_hyperv; EXPORT_SYMBOL_GPL(ms_hyperv); @@ -157,6 +158,26 @@ static unsigned char hv_get_nmi_reason(void) return 0; } +#ifdef CONFIG_X86_LOCAL_APIC +/* + * Prior to WS2016 Debug-VM sends NMIs to all CPUs which makes + * it dificult to process CHANNELMSG_UNLOAD in case of crash. Handle + * unknown NMI on the first CPU which gets it. + */ +static int hv_nmi_unknown(unsigned int val, struct pt_regs *regs) +{ + static atomic_t nmi_cpu = ATOMIC_INIT(-1); + + if (!unknown_nmi_panic) + return NMI_DONE; + + if (atomic_cmpxchg(&nmi_cpu, -1, raw_smp_processor_id()) != -1) + return NMI_HANDLED; + + return NMI_DONE; +} +#endif + static void __init ms_hyperv_init_platform(void) { /* @@ -182,6 +203,9 @@ static void __init ms_hyperv_init_platform(void) printk(KERN_INFO "HyperV: LAPIC Timer Frequency: %#x\n", lapic_timer_frequency); } + + register_nmi_handler(NMI_UNKNOWN, hv_nmi_unknown, NMI_FLAG_FIRST, + "hv_nmi_unknown"); #endif if (ms_hyperv.features & HV_X64_MSR_TIME_REF_COUNT_AVAILABLE) From patchwork Sat Mar 25 16:18:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Semwal X-Patchwork-Id: 95982 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp532125qgd; Sat, 25 Mar 2017 09:19:12 -0700 (PDT) X-Received: by 10.84.197.131 with SMTP id n3mr18362973pld.43.1490458752298; Sat, 25 Mar 2017 09:19:12 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3si6723034pli.62.2017.03.25.09.19.12; Sat, 25 Mar 2017 09:19:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751339AbdCYQTM (ORCPT + 5 others); Sat, 25 Mar 2017 12:19:12 -0400 Received: from mail-pg0-f45.google.com ([74.125.83.45]:34808 "EHLO mail-pg0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751309AbdCYQTL (ORCPT ); Sat, 25 Mar 2017 12:19:11 -0400 Received: by mail-pg0-f45.google.com with SMTP id 21so9212281pgg.1 for ; Sat, 25 Mar 2017 09:19:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ObiQCHNzvTtSBLtXsuBgnkHnMfoknUeSeJVAfQttlYg=; b=RPjTJuAi+nOfveSjVpS1T+5nETqiHsvOuMS03Lwkbcg59g50CNgg+w/u58Fn1iwI1h VeosrMja1cOpqmV5MWSKVddQ01U3s8XRB/aYqE7dZNlNjDI0FxHcsWrtDwcDF/JYflTE PfCfXK8BcMOSrbc2MRequ1SKI/VM9UkCELrtY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ObiQCHNzvTtSBLtXsuBgnkHnMfoknUeSeJVAfQttlYg=; b=c9p4isi+iw261VziatknHfdlZ2zkuAxOvfk3LtMZuuF7hunCcDqJlOHCC9gc3AnvTG JHXwFW402vc3jeDi6AWkh8TNSIIrBCMHzSq14jiAM4JaHp0U4WrzGsG2J+46INyH7lXs MtvHVE/08pdSxOpMIVhraPoRCVjJZ/burJZQp5LNpWSAYWmUpzwnfN//IkUjFMq8wY// q3i7Y42CAHkN2z5v42eVHJr2su6ORdZd0DBImF4U008dTuKVwPHSiie7/E8uKfrcmhLK 3vGaf1MijRr7acnfaFAjeEX7O0qfL5+lr7gX3b1s9EGFQMSEyox/+S+BEiXs1JvqggmV gkWQ== X-Gm-Message-State: AFeK/H2ANenSLUJgKwt0DJ+MPdd5ua26Qo1o8r4BbQ4ttKOA08FhLG0CcWlLszA1IpCZA7if X-Received: by 10.84.238.22 with SMTP id u22mr18544748plk.137.1490458750052; Sat, 25 Mar 2017 09:19:10 -0700 (PDT) Received: from phantom.lan ([106.51.225.38]) by smtp.gmail.com with ESMTPSA id q194sm11469541pfq.43.2017.03.25.09.19.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 25 Mar 2017 09:19:08 -0700 (PDT) From: Sumit Semwal To: stable@vger.kernel.org Cc: Bjorn Helgaas , Sasha Levin , Greg Kroah-Hartman , Sumit Semwal Subject: [PATCH for-4.4 05/19] PCI: Separate VF BAR updates from standard BAR updates Date: Sat, 25 Mar 2017 21:48:05 +0530 Message-Id: <1490458699-24484-6-git-send-email-sumit.semwal@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> References: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Bjorn Helgaas [ Upstream commit 6ffa2489c51da77564a0881a73765ea2169f955d ] Previously pci_update_resource() used the same code path for updating standard BARs and VF BARs in SR-IOV capabilities. Split the VF BAR update into a new pci_iov_update_resource() internal interface, which makes it simpler to compute the BAR address (we can get rid of pci_resource_bar() and pci_iov_resource_bar()). This patch: - Renames pci_update_resource() to pci_std_update_resource(), - Adds pci_iov_update_resource(), - Makes pci_update_resource() a wrapper that calls the appropriate one, No functional change intended. Signed-off-by: Bjorn Helgaas Reviewed-by: Gavin Shan Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sumit Semwal --- drivers/pci/iov.c | 50 +++++++++++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci.h | 1 + drivers/pci/setup-res.c | 13 +++++++++++-- 3 files changed, 62 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index 31f31d4..a6b1001 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -572,6 +572,56 @@ int pci_iov_resource_bar(struct pci_dev *dev, int resno) 4 * (resno - PCI_IOV_RESOURCES); } +/** + * pci_iov_update_resource - update a VF BAR + * @dev: the PCI device + * @resno: the resource number + * + * Update a VF BAR in the SR-IOV capability of a PF. + */ +void pci_iov_update_resource(struct pci_dev *dev, int resno) +{ + struct pci_sriov *iov = dev->is_physfn ? dev->sriov : NULL; + struct resource *res = dev->resource + resno; + int vf_bar = resno - PCI_IOV_RESOURCES; + struct pci_bus_region region; + u32 new; + int reg; + + /* + * The generic pci_restore_bars() path calls this for all devices, + * including VFs and non-SR-IOV devices. If this is not a PF, we + * have nothing to do. + */ + if (!iov) + return; + + /* + * Ignore unimplemented BARs, unused resource slots for 64-bit + * BARs, and non-movable resources, e.g., those described via + * Enhanced Allocation. + */ + if (!res->flags) + return; + + if (res->flags & IORESOURCE_UNSET) + return; + + if (res->flags & IORESOURCE_PCI_FIXED) + return; + + pcibios_resource_to_bus(dev->bus, ®ion, res); + new = region.start; + new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK; + + reg = iov->pos + PCI_SRIOV_BAR + 4 * vf_bar; + pci_write_config_dword(dev, reg, new); + if (res->flags & IORESOURCE_MEM_64) { + new = region.start >> 16 >> 16; + pci_write_config_dword(dev, reg + 4, new); + } +} + resource_size_t __weak pcibios_iov_resource_alignment(struct pci_dev *dev, int resno) { diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index d390fc1..eda77d1 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -277,6 +277,7 @@ static inline void pci_restore_ats_state(struct pci_dev *dev) int pci_iov_init(struct pci_dev *dev); void pci_iov_release(struct pci_dev *dev); int pci_iov_resource_bar(struct pci_dev *dev, int resno); +void pci_iov_update_resource(struct pci_dev *dev, int resno); resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); void pci_restore_iov_state(struct pci_dev *dev); int pci_iov_bus_range(struct pci_bus *bus); diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index 604011e..ac58c56 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -25,8 +25,7 @@ #include #include "pci.h" - -void pci_update_resource(struct pci_dev *dev, int resno) +static void pci_std_update_resource(struct pci_dev *dev, int resno) { struct pci_bus_region region; bool disable; @@ -110,6 +109,16 @@ void pci_update_resource(struct pci_dev *dev, int resno) pci_write_config_word(dev, PCI_COMMAND, cmd); } +void pci_update_resource(struct pci_dev *dev, int resno) +{ + if (resno <= PCI_ROM_RESOURCE) + pci_std_update_resource(dev, resno); +#ifdef CONFIG_PCI_IOV + else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) + pci_iov_update_resource(dev, resno); +#endif +} + int pci_claim_resource(struct pci_dev *dev, int resource) { struct resource *res = &dev->resource[resource]; From patchwork Sat Mar 25 16:18:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Semwal X-Patchwork-Id: 95983 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp532138qgd; Sat, 25 Mar 2017 09:19:15 -0700 (PDT) X-Received: by 10.98.144.69 with SMTP id a66mr16499285pfe.30.1490458755037; Sat, 25 Mar 2017 09:19:15 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3si6723034pli.62.2017.03.25.09.19.14; Sat, 25 Mar 2017 09:19:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751324AbdCYQTP (ORCPT + 5 others); Sat, 25 Mar 2017 12:19:15 -0400 Received: from mail-pg0-f41.google.com ([74.125.83.41]:36087 "EHLO mail-pg0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751309AbdCYQTO (ORCPT ); Sat, 25 Mar 2017 12:19:14 -0400 Received: by mail-pg0-f41.google.com with SMTP id g2so9134692pge.3 for ; Sat, 25 Mar 2017 09:19:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WOepa1uSvm+lFMRfzU54IIER5gX5Cye56zPgN5hTGPg=; b=SnGui8RlidgppGxp8BPoWfGoHHTAlPR4sL1PbNl5Htr8/k0np6LZSMUhTW4DBRN4JG +D1g4kzYijYoQWZGIJHG62ULmJq9UxhewTmlznZYOBlJ1kcbW159TlntzBybHOnNmj3i y6Qy31dl83wS/Udw8XUuh71it03FCyW035d6U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WOepa1uSvm+lFMRfzU54IIER5gX5Cye56zPgN5hTGPg=; b=d8x3jIbR5R/24scDzodekCaH+YwFSZ0D4hF6JfEcqGhoxgSHYOhWjazvaetEn98vUq W+icuG9YbvcIwdBRPtW9ltSvwz6nYwox2dJkiyNUivnMb4yWfBBF6jUOq9fD6nc9eMrL 2BrwagSMLUbSIu+g6wtphN9pfKfzsXK1KX5eLvHJFVI+Oo928fMipLTTD2s7/l4OFxs7 /+bZ/3dY7HvcFV6lsU4xnVVlSdHnYSFAYWL3PT50YfQ+dBOnWxYnVf0ufsekIOpYpZ3f IW9JxtH05WUeSHd4gIVQjUNtA3zVbw0OebzRKG5iUY2tEl/GBd7KLBGJVL1VBD/zRcuv jdHg== X-Gm-Message-State: AFeK/H1tRqZxarJ1DzGOzqo9oXysK8jqmJbilUrnnDrL22XWURm5VNozI0gS498b9v4tNlVF X-Received: by 10.98.153.198 with SMTP id t67mr15936605pfk.1.1490458752939; Sat, 25 Mar 2017 09:19:12 -0700 (PDT) Received: from phantom.lan ([106.51.225.38]) by smtp.gmail.com with ESMTPSA id q194sm11469541pfq.43.2017.03.25.09.19.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 25 Mar 2017 09:19:11 -0700 (PDT) From: Sumit Semwal To: stable@vger.kernel.org Cc: Bjorn Helgaas , Sasha Levin , Greg Kroah-Hartman , Sumit Semwal Subject: [PATCH for-4.4 06/19] PCI: Remove pci_resource_bar() and pci_iov_resource_bar() Date: Sat, 25 Mar 2017 21:48:06 +0530 Message-Id: <1490458699-24484-7-git-send-email-sumit.semwal@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> References: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Bjorn Helgaas [ Upstream commit 286c2378aaccc7343ebf17ec6cd86567659caf70 ] pci_std_update_resource() only deals with standard BARs, so we don't have to worry about the complications of VF BARs in an SR-IOV capability. Compute the BAR address inline and remove pci_resource_bar(). That makes pci_iov_resource_bar() unused, so remove that as well. Signed-off-by: Bjorn Helgaas Reviewed-by: Gavin Shan Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sumit Semwal --- drivers/pci/iov.c | 18 ------------------ drivers/pci/pci.c | 30 ------------------------------ drivers/pci/pci.h | 6 ------ drivers/pci/setup-res.c | 13 +++++++------ 4 files changed, 7 insertions(+), 60 deletions(-) -- 2.7.4 diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index a6b1001..2f8ea6f 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -555,24 +555,6 @@ void pci_iov_release(struct pci_dev *dev) } /** - * pci_iov_resource_bar - get position of the SR-IOV BAR - * @dev: the PCI device - * @resno: the resource number - * - * Returns position of the BAR encapsulated in the SR-IOV capability. - */ -int pci_iov_resource_bar(struct pci_dev *dev, int resno) -{ - if (resno < PCI_IOV_RESOURCES || resno > PCI_IOV_RESOURCE_END) - return 0; - - BUG_ON(!dev->is_physfn); - - return dev->sriov->pos + PCI_SRIOV_BAR + - 4 * (resno - PCI_IOV_RESOURCES); -} - -/** * pci_iov_update_resource - update a VF BAR * @dev: the PCI device * @resno: the resource number diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index e311a9b..a01e6d5 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4472,36 +4472,6 @@ int pci_select_bars(struct pci_dev *dev, unsigned long flags) } EXPORT_SYMBOL(pci_select_bars); -/** - * pci_resource_bar - get position of the BAR associated with a resource - * @dev: the PCI device - * @resno: the resource number - * @type: the BAR type to be filled in - * - * Returns BAR position in config space, or 0 if the BAR is invalid. - */ -int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type) -{ - int reg; - - if (resno < PCI_ROM_RESOURCE) { - *type = pci_bar_unknown; - return PCI_BASE_ADDRESS_0 + 4 * resno; - } else if (resno == PCI_ROM_RESOURCE) { - *type = pci_bar_mem32; - return dev->rom_base_reg; - } else if (resno < PCI_BRIDGE_RESOURCES) { - /* device specific resource */ - *type = pci_bar_unknown; - reg = pci_iov_resource_bar(dev, resno); - if (reg) - return reg; - } - - dev_err(&dev->dev, "BAR %d: invalid resource\n", resno); - return 0; -} - /* Some architectures require additional programming to enable VGA */ static arch_set_vga_state_t arch_set_vga_state; diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index eda77d1..c43e448 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -232,7 +232,6 @@ bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, int pci_setup_device(struct pci_dev *dev); int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, struct resource *res, unsigned int reg); -int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type); void pci_configure_ari(struct pci_dev *dev); void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head); @@ -276,7 +275,6 @@ static inline void pci_restore_ats_state(struct pci_dev *dev) #ifdef CONFIG_PCI_IOV int pci_iov_init(struct pci_dev *dev); void pci_iov_release(struct pci_dev *dev); -int pci_iov_resource_bar(struct pci_dev *dev, int resno); void pci_iov_update_resource(struct pci_dev *dev, int resno); resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); void pci_restore_iov_state(struct pci_dev *dev); @@ -291,10 +289,6 @@ static inline void pci_iov_release(struct pci_dev *dev) { } -static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno) -{ - return 0; -} static inline void pci_restore_iov_state(struct pci_dev *dev) { } diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index ac58c56..674e76c 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -32,7 +32,6 @@ static void pci_std_update_resource(struct pci_dev *dev, int resno) u16 cmd; u32 new, check, mask; int reg; - enum pci_bar_type type; struct resource *res = dev->resource + resno; if (dev->is_virtfn) { @@ -66,14 +65,16 @@ static void pci_std_update_resource(struct pci_dev *dev, int resno) else mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; - reg = pci_resource_bar(dev, resno, &type); - if (!reg) - return; - if (type != pci_bar_unknown) { + if (resno < PCI_ROM_RESOURCE) { + reg = PCI_BASE_ADDRESS_0 + 4 * resno; + } else if (resno == PCI_ROM_RESOURCE) { if (!(res->flags & IORESOURCE_ROM_ENABLE)) return; + + reg = dev->rom_base_reg; new |= PCI_ROM_ADDRESS_ENABLE; - } + } else + return; /* * We can't update a 64-bit BAR atomically, so when possible, From patchwork Sat Mar 25 16:18:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Semwal X-Patchwork-Id: 95984 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp532148qgd; Sat, 25 Mar 2017 09:19:18 -0700 (PDT) X-Received: by 10.84.238.207 with SMTP id l15mr18269990pln.90.1490458757971; Sat, 25 Mar 2017 09:19:17 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3si6723034pli.62.2017.03.25.09.19.17; Sat, 25 Mar 2017 09:19:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751340AbdCYQTS (ORCPT + 5 others); Sat, 25 Mar 2017 12:19:18 -0400 Received: from mail-pg0-f49.google.com ([74.125.83.49]:33376 "EHLO mail-pg0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751309AbdCYQTR (ORCPT ); Sat, 25 Mar 2017 12:19:17 -0400 Received: by mail-pg0-f49.google.com with SMTP id n5so1546472pgh.0 for ; Sat, 25 Mar 2017 09:19:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=j3ms49jibrKmty+yBxTcO8/vx6pxhMSjywAq45SEIdI=; b=BWw9AincOK/BaIFakp4I8JpzMRD/o7xdvlToeuuOywymLki6xQf42niHpzPDPSx7Mv WRt6kKVtA0qFxJOqpVXX3jpCJcAqHL62ATQrozYgcwGNIlq6nO3VwpgjglqLb7Tr6EYG kjq4/XOekl/rj7D2LV1RN+ZScpnZ05pEW+Fx0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=j3ms49jibrKmty+yBxTcO8/vx6pxhMSjywAq45SEIdI=; b=INC612+qutV/MpaLfUHUDyHMkqZ1dJnhwaxO1mLnTA/j//6s4LFhRu1ZooYy0MXe/0 6hmpllZ5+EGT+c1a/loH6FoL+Mt8Q7gEjwBJdcyl5gtJ4MO04VUzmYobyH7EpIbsvOc2 Dm5MMnMZYMQGCVGsnBFBfnfDnrAyH59wVvXY9ZeFN5zanWO2d/jSvls/yvaZEmXz1Cy+ bjGn9qC+OPeiqxmMYYG3Vy65tefPZRHI2rTJr9PONIq+QPwjTf8VC0QpCiQGQXUZ+7Xq J2q+vZd9X5kxhrP/6Xq5Q/GfykaLsFt+/U9oYM4Z08Au0StfSIgTaALVNN4yqvxFELqT UtSA== X-Gm-Message-State: AFeK/H3w5Pj8cJWYlBdkqkahHwDDhzyQcBzJEZijd+1X/0mSd6xLvJeupl/mRFzZQWXrmENj X-Received: by 10.98.107.194 with SMTP id g185mr16043136pfc.22.1490458755899; Sat, 25 Mar 2017 09:19:15 -0700 (PDT) Received: from phantom.lan ([106.51.225.38]) by smtp.gmail.com with ESMTPSA id q194sm11469541pfq.43.2017.03.25.09.19.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 25 Mar 2017 09:19:14 -0700 (PDT) From: Sumit Semwal To: stable@vger.kernel.org Cc: Bjorn Helgaas , Sasha Levin , Greg Kroah-Hartman , Sumit Semwal Subject: [PATCH for-4.4 07/19] PCI: Add comments about ROM BAR updating Date: Sat, 25 Mar 2017 21:48:07 +0530 Message-Id: <1490458699-24484-8-git-send-email-sumit.semwal@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> References: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Bjorn Helgaas [ Upstream commit 0b457dde3cf8b7c76a60f8e960f21bbd4abdc416 ] pci_update_resource() updates a hardware BAR so its address matches the kernel's struct resource UNLESS it's a disabled ROM BAR. We only update those when we enable the ROM. It's not obvious from the code why ROM BARs should be handled specially. Apparently there are Matrox devices with defective ROM BARs that read as zero when disabled. That means that if pci_enable_rom() reads the disabled BAR, sets PCI_ROM_ADDRESS_ENABLE (without re-inserting the address), and writes it back, it would enable the ROM at address zero. Add comments and references to explain why we can't make the code look more rational. The code changes are from 755528c860b0 ("Ignore disabled ROM resources at setup") and 8085ce084c0f ("[PATCH] Fix PCI ROM mapping"). Link: https://lkml.org/lkml/2005/8/30/138 Signed-off-by: Bjorn Helgaas Reviewed-by: Gavin Shan Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman [sumits: minor fixup in rom.c for 4.4.y] Signed-off-by: Sumit Semwal --- drivers/pci/rom.c | 5 +++++ drivers/pci/setup-res.c | 6 ++++++ 2 files changed, 11 insertions(+) -- 2.7.4 diff --git a/drivers/pci/rom.c b/drivers/pci/rom.c index eb0ad53..3eea7fc 100644 --- a/drivers/pci/rom.c +++ b/drivers/pci/rom.c @@ -31,6 +31,11 @@ int pci_enable_rom(struct pci_dev *pdev) if (!res->flags) return -1; + /* + * Ideally pci_update_resource() would update the ROM BAR address, + * and we would only set the enable bit here. But apparently some + * devices have buggy ROM BARs that read as zero when disabled. + */ pcibios_resource_to_bus(pdev->bus, ®ion, res); pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr); rom_addr &= ~PCI_ROM_ADDRESS_MASK; diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index 674e76c..d1ba5e0 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -68,6 +68,12 @@ static void pci_std_update_resource(struct pci_dev *dev, int resno) if (resno < PCI_ROM_RESOURCE) { reg = PCI_BASE_ADDRESS_0 + 4 * resno; } else if (resno == PCI_ROM_RESOURCE) { + + /* + * Apparently some Matrox devices have ROM BARs that read + * as zero when disabled, so don't update ROM BARs unless + * they're enabled. See https://lkml.org/lkml/2005/8/30/138. + */ if (!(res->flags & IORESOURCE_ROM_ENABLE)) return; From patchwork Sat Mar 25 16:18:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Semwal X-Patchwork-Id: 95985 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp532155qgd; Sat, 25 Mar 2017 09:19:20 -0700 (PDT) X-Received: by 10.84.230.131 with SMTP id e3mr18891256plk.100.1490458760615; Sat, 25 Mar 2017 09:19:20 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3si6723034pli.62.2017.03.25.09.19.20; Sat, 25 Mar 2017 09:19:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751343AbdCYQTU (ORCPT + 5 others); Sat, 25 Mar 2017 12:19:20 -0400 Received: from mail-pf0-f178.google.com ([209.85.192.178]:34125 "EHLO mail-pf0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751309AbdCYQTU (ORCPT ); Sat, 25 Mar 2017 12:19:20 -0400 Received: by mail-pf0-f178.google.com with SMTP id p189so8000310pfp.1 for ; Sat, 25 Mar 2017 09:19:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IT6as62xM3A0yVHJHzGnsgVAuPGKco1oVx+KKVZ+qoc=; b=UoaN/NO/vLJVwRAGjRyl4S3VIfPVeoSXPp4VkV+QHLqCfzaFOzvlh7MtewiNXj7jrR SZEyZTZ/kvdEEC9ebAW7JZkfCVACcMAB5E8nEs1r1skAhVHazAFreKbzP+aS+BVEqpkt bnYA/v6XcbMFHQpegIwM7MP5WNDVB4CU7OyHw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IT6as62xM3A0yVHJHzGnsgVAuPGKco1oVx+KKVZ+qoc=; b=EcuXx2wI3al7DA0cIPUTRa4VkTxjAuIgCzdQGuOJk22YYePej7vbgDwtYrUqnPGm7k SSpwrFQQVjkCYOSnxfb2OS40UKGh4m91xrn54LaTsdP+qv9hh9G1KQP4i28Sw5JUDNB3 LK2LQsYSDbKjlp/CB2RLfSwoy75/y0P0SLgRY8o2Bm4imAwhe2Zx++Yfx0OMBa2ncaV3 8MFDxsbqLqP9ukLRUkUMKsoSXu4M6c7wv0oa8DEdh+d3WmKjJ86ulFlK8sx4TxzbcZMh IeyOsH+OVSntAP/HVZHV5lA+bdUr23QxHhqoZRKYlpQ/9gP/n9H2jg+Eu7LlC1riT7na dP9g== X-Gm-Message-State: AFeK/H0Ymrjl8T3gjB1W7Us9EKfMO1sRy/d0EmKzA41G4rGysDbUKJliyosEDAD5MTUQCRxq X-Received: by 10.99.50.70 with SMTP id y67mr15185823pgy.109.1490458758641; Sat, 25 Mar 2017 09:19:18 -0700 (PDT) Received: from phantom.lan ([106.51.225.38]) by smtp.gmail.com with ESMTPSA id q194sm11469541pfq.43.2017.03.25.09.19.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 25 Mar 2017 09:19:17 -0700 (PDT) From: Sumit Semwal To: stable@vger.kernel.org Cc: Bjorn Helgaas , Sasha Levin , Greg Kroah-Hartman , Sumit Semwal Subject: [PATCH for-4.4 08/19] PCI: Decouple IORESOURCE_ROM_ENABLE and PCI_ROM_ADDRESS_ENABLE Date: Sat, 25 Mar 2017 21:48:08 +0530 Message-Id: <1490458699-24484-9-git-send-email-sumit.semwal@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> References: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Bjorn Helgaas [ Upstream commit 7a6d312b50e63f598f5b5914c4fd21878ac2b595 ] Remove the assumption that IORESOURCE_ROM_ENABLE == PCI_ROM_ADDRESS_ENABLE. PCI_ROM_ADDRESS_ENABLE is the ROM enable bit defined by the PCI spec, so if we're reading or writing a BAR register value, that's what we should use. IORESOURCE_ROM_ENABLE is a corresponding bit in struct resource flags. Signed-off-by: Bjorn Helgaas Reviewed-by: Gavin Shan Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sumit Semwal --- drivers/pci/probe.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 71d9a6d..b83df94 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -226,7 +226,8 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK; } } else { - res->flags |= (l & IORESOURCE_ROM_ENABLE); + if (l & PCI_ROM_ADDRESS_ENABLE) + res->flags |= IORESOURCE_ROM_ENABLE; l64 = l & PCI_ROM_ADDRESS_MASK; sz64 = sz & PCI_ROM_ADDRESS_MASK; mask64 = (u32)PCI_ROM_ADDRESS_MASK; From patchwork Sat Mar 25 16:18:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Semwal X-Patchwork-Id: 95986 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp532169qgd; Sat, 25 Mar 2017 09:19:23 -0700 (PDT) X-Received: by 10.99.103.133 with SMTP id b127mr15441737pgc.29.1490458763780; Sat, 25 Mar 2017 09:19:23 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3si6723034pli.62.2017.03.25.09.19.23; Sat, 25 Mar 2017 09:19:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751344AbdCYQTX (ORCPT + 5 others); Sat, 25 Mar 2017 12:19:23 -0400 Received: from mail-pf0-f170.google.com ([209.85.192.170]:35251 "EHLO mail-pf0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751309AbdCYQTX (ORCPT ); Sat, 25 Mar 2017 12:19:23 -0400 Received: by mail-pf0-f170.google.com with SMTP id 20so7967199pfk.2 for ; Sat, 25 Mar 2017 09:19:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tCJgzT8thrFblqINa63Jp71LYcx4lHGWafqBVNird9U=; b=gtqzr93hza+YuoRSVgbrUZl8kyncl70KGaB2Hw11wDQ6HysYt3it/HqTuZ6D3V64yx McwKLzQM7OzZHxibaSmUr4uTpPy2ZmnFC0cLSKm0I8JUygK/Xw+Idw4yGSb/JuxXpXU4 LPKbbtlFcz7xo7UkYYqGx5KlzmbcF98xDSUvM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tCJgzT8thrFblqINa63Jp71LYcx4lHGWafqBVNird9U=; b=Ryv5b/gq6++axyF8cmWdNNbpFUKR9VfuAZ785Ric04rvvpM6zdHmitEs73XzF0Wshk oIxQvb9GkbU6DkZZ/IKTs6lJkzzTpNYexT5z1OFsqAgqAapJ86LUxTqWo+OQCeiF8Tze F3Jbiq0daX0ePKOV7x3r2TVoNj6wzmqJ/7u1++pZU4yxzmdLt74+5FTo7ogbwiOHiRt0 tbr+yjruzwudxyAb/kko072qDuBeiL37780XibD/pWJBomWQo3VbwtneGyD3lFIlMSV+ PcYOsxNU269wT7L0UCoHtD78LBa51l6X2DcTuo3N2JBDqwdp4OfrCbPU0BHJ69y/l+Tw ESBg== X-Gm-Message-State: AFeK/H1pMAKlKhvjDOi7GI9kN9IeCmS9Lu308br06hH6XLoQC7qDtPLtfXFqjbF59k4DmQQW X-Received: by 10.84.173.4 with SMTP id o4mr18493469plb.106.1490458761859; Sat, 25 Mar 2017 09:19:21 -0700 (PDT) Received: from phantom.lan ([106.51.225.38]) by smtp.gmail.com with ESMTPSA id q194sm11469541pfq.43.2017.03.25.09.19.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 25 Mar 2017 09:19:20 -0700 (PDT) From: Sumit Semwal To: stable@vger.kernel.org Cc: Bjorn Helgaas , Sasha Levin , Greg Kroah-Hartman , Sumit Semwal Subject: [PATCH for-4.4 09/19] PCI: Don't update VF BARs while VF memory space is enabled Date: Sat, 25 Mar 2017 21:48:09 +0530 Message-Id: <1490458699-24484-10-git-send-email-sumit.semwal@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> References: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Bjorn Helgaas [ Upstream commit 546ba9f8f22f71b0202b6ba8967be5cc6dae4e21 ] If we update a VF BAR while it's enabled, there are two potential problems: 1) Any driver that's using the VF has a cached BAR value that is stale after the update, and 2) We can't update 64-bit BARs atomically, so the intermediate state (new lower dword with old upper dword) may conflict with another device, and an access by a driver unrelated to the VF may cause a bus error. Warn about attempts to update VF BARs while they are enabled. This is a programming error, so use dev_WARN() to get a backtrace. Signed-off-by: Bjorn Helgaas Reviewed-by: Gavin Shan Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sumit Semwal --- drivers/pci/iov.c | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.7.4 diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index 2f8ea6f..47c46d0 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -567,6 +567,7 @@ void pci_iov_update_resource(struct pci_dev *dev, int resno) struct resource *res = dev->resource + resno; int vf_bar = resno - PCI_IOV_RESOURCES; struct pci_bus_region region; + u16 cmd; u32 new; int reg; @@ -578,6 +579,13 @@ void pci_iov_update_resource(struct pci_dev *dev, int resno) if (!iov) return; + pci_read_config_word(dev, iov->pos + PCI_SRIOV_CTRL, &cmd); + if ((cmd & PCI_SRIOV_CTRL_VFE) && (cmd & PCI_SRIOV_CTRL_MSE)) { + dev_WARN(&dev->dev, "can't update enabled VF BAR%d %pR\n", + vf_bar, res); + return; + } + /* * Ignore unimplemented BARs, unused resource slots for 64-bit * BARs, and non-movable resources, e.g., those described via From patchwork Sat Mar 25 16:18:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Semwal X-Patchwork-Id: 95987 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp532178qgd; Sat, 25 Mar 2017 09:19:26 -0700 (PDT) X-Received: by 10.98.160.84 with SMTP id r81mr16228378pfe.71.1490458766896; Sat, 25 Mar 2017 09:19:26 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3si6723034pli.62.2017.03.25.09.19.26; Sat, 25 Mar 2017 09:19:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751350AbdCYQT0 (ORCPT + 5 others); Sat, 25 Mar 2017 12:19:26 -0400 Received: from mail-pg0-f50.google.com ([74.125.83.50]:36108 "EHLO mail-pg0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751309AbdCYQT0 (ORCPT ); Sat, 25 Mar 2017 12:19:26 -0400 Received: by mail-pg0-f50.google.com with SMTP id g2so9136064pge.3 for ; Sat, 25 Mar 2017 09:19:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=phNXz8ra/bu9p7BVAO8iJTRFr/rtrqkH/boy78OBUuw=; b=heyrAUZz2Zh2s8vFjsXcop0xs9HLd1NWRRe9LCUYG7bx3qjfcbBoiZ8Oit128mAvLP T5EP4nOpwzCNo6AnTzqiqicXcUYeWhesk/XnHJVgZ39gUGA8MM/x0YXsc/GGBngAmYY9 +bRrKpa+Ve7ZjMoEC4gSa1yX29nJp1Zc7+Mh4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=phNXz8ra/bu9p7BVAO8iJTRFr/rtrqkH/boy78OBUuw=; b=UzaNvdSAxTGmfjBV+ShVEjNN9MU16g7cko5jkBngzm9chYCZZKCMb/Ysn59Uoxy1HE 3MjNCQr+HdYmEdxAbs0Aly8K8ydor9WlVQZ39dra7a52CaD6J1DUTyA7TBtoQU0SnjJl yQarNxro+UHF2hjLA/A6nfcmdm5W1UyYgfWlVDLFJwCg8nQyS8/mTwwWJv12qRbhXL3i StnX9V35KGNyhDVsGd7EXHfJO3vfqkpUpz28kv2e0srr5gO4ETUi0RurnRXasGjaJiQk uZpKZXCxxEG8HOLhWSBqZBOCl4deGR5mWhh3yH7A7sY3gvPWn79ZRIqbAn6HlF4rPhSm U0SQ== X-Gm-Message-State: AFeK/H1KfnQhuwKO2pKMIIxVx88ZKx9mqKkIQLVVmdQ8aphJrGQYXdTcXFx+ep109DjLF8u/ X-Received: by 10.98.19.156 with SMTP id 28mr15702257pft.208.1490458764807; Sat, 25 Mar 2017 09:19:24 -0700 (PDT) Received: from phantom.lan ([106.51.225.38]) by smtp.gmail.com with ESMTPSA id q194sm11469541pfq.43.2017.03.25.09.19.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 25 Mar 2017 09:19:23 -0700 (PDT) From: Sumit Semwal To: stable@vger.kernel.org Cc: Bjorn Helgaas , Sasha Levin , Greg Kroah-Hartman , Sumit Semwal Subject: [PATCH for-4.4 10/19] PCI: Update BARs using property bits appropriate for type Date: Sat, 25 Mar 2017 21:48:10 +0530 Message-Id: <1490458699-24484-11-git-send-email-sumit.semwal@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> References: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Bjorn Helgaas [ Upstream commit 45d004f4afefdd8d79916ee6d97a9ecd94bb1ffe ] The BAR property bits (0-3 for memory BARs, 0-1 for I/O BARs) are supposed to be read-only, but we do save them in res->flags and include them when updating the BAR. Mask the I/O property bits with ~PCI_BASE_ADDRESS_IO_MASK (0x3) instead of PCI_REGION_FLAG_MASK (0xf) to make it obvious that we can't corrupt bits 2-3 of I/O addresses. Use PCI_ROM_ADDRESS_MASK for ROM BARs. This means we'll only check the top 21 bits (instead of the 28 bits we used to check) of a ROM BAR to see if the update was successful. Signed-off-by: Bjorn Helgaas Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sumit Semwal --- drivers/pci/setup-res.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) -- 2.7.4 diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index d1ba5e0..032a6b1 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -58,12 +58,17 @@ static void pci_std_update_resource(struct pci_dev *dev, int resno) return; pcibios_resource_to_bus(dev->bus, ®ion, res); + new = region.start; - new = region.start | (res->flags & PCI_REGION_FLAG_MASK); - if (res->flags & IORESOURCE_IO) + if (res->flags & IORESOURCE_IO) { mask = (u32)PCI_BASE_ADDRESS_IO_MASK; - else + new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK; + } else if (resno == PCI_ROM_RESOURCE) { + mask = (u32)PCI_ROM_ADDRESS_MASK; + } else { mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; + new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK; + } if (resno < PCI_ROM_RESOURCE) { reg = PCI_BASE_ADDRESS_0 + 4 * resno; From patchwork Sat Mar 25 16:18:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Semwal X-Patchwork-Id: 95988 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp532187qgd; Sat, 25 Mar 2017 09:19:29 -0700 (PDT) X-Received: by 10.98.64.129 with SMTP id f1mr15851562pfd.123.1490458769858; Sat, 25 Mar 2017 09:19:29 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3si6723034pli.62.2017.03.25.09.19.29; Sat, 25 Mar 2017 09:19:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751354AbdCYQT3 (ORCPT + 5 others); Sat, 25 Mar 2017 12:19:29 -0400 Received: from mail-pf0-f169.google.com ([209.85.192.169]:36617 "EHLO mail-pf0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751309AbdCYQT3 (ORCPT ); Sat, 25 Mar 2017 12:19:29 -0400 Received: by mail-pf0-f169.google.com with SMTP id o126so7965424pfb.3 for ; Sat, 25 Mar 2017 09:19:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=N8tq9x2SmgonydooiQtRGbVuo6DG+qhER+VBJeTK2Pk=; b=NgCA2jgwqn4SGLQju8e7QLMhQCb5ej4a8XKL082Ktq9rtHh9pCi2GF8Nk5bHAyvG/O NpBuhc62V6rXnvZ3mpLkwF6mp/KjbBNliHf2+W+TNxGLpRjSY8g2k2xAfC9/RyxZ1s96 xE7Xl81DrxGpN320ptl4HQElOhHQcOoLD7jyw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=N8tq9x2SmgonydooiQtRGbVuo6DG+qhER+VBJeTK2Pk=; b=QHPTDzJgnwdd4b3iKgzcYEfw41nWSqi27n7rCf4sICwnajyFnFbIQghkDGSp0jyvKW ju2V4xvxznJwzIRbWQIb/9hKWGgdvzKWKSF1B7214HliKP8KUAHwG/KzxSGzsybB/vz/ FPjPzfU97YmXTpYBIW0UOXhpGLyV0cU1AJqeaL6CytwZEdyMBk7gpiRDPTpEQqOi2Wtr qAdJXhLSY6aDFGYWoXb43hN/FbSYNLr0dwY9fOdYSK4TDy09AVVEubttkj9CWbNhVjwb JX2+qleZ4fZFu4un4guW6qTNt3Ju4amoFTsEeLXvQnJ1n73Vbzd7FkUJRcIFr9KYahyn bMYA== X-Gm-Message-State: AFeK/H1QC1coKuyfiqv7w09yxvGQyci4caHJtvwk1AItMepgqU5HNr6cdUBVQB3liYmrFWX+ X-Received: by 10.84.217.149 with SMTP id p21mr18342173pli.18.1490458767945; Sat, 25 Mar 2017 09:19:27 -0700 (PDT) Received: from phantom.lan ([106.51.225.38]) by smtp.gmail.com with ESMTPSA id q194sm11469541pfq.43.2017.03.25.09.19.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 25 Mar 2017 09:19:26 -0700 (PDT) From: Sumit Semwal To: stable@vger.kernel.org Cc: Bjorn Helgaas , Sasha Levin , Greg Kroah-Hartman , Sumit Semwal Subject: [PATCH for-4.4 11/19] PCI: Ignore BAR updates on virtual functions Date: Sat, 25 Mar 2017 21:48:11 +0530 Message-Id: <1490458699-24484-12-git-send-email-sumit.semwal@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> References: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Bjorn Helgaas [ Upstream commit 63880b230a4af502c56dde3d4588634c70c66006 ] VF BARs are read-only zero, so updating VF BARs will not have any effect. See the SR-IOV spec r1.1, sec 3.4.1.11. We already ignore these updates because of 70675e0b6a1a ("PCI: Don't try to restore VF BARs"); this merely restructures it slightly to make it easier to split updates for standard and SR-IOV BARs. Signed-off-by: Bjorn Helgaas Reviewed-by: Gavin Shan Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sumit Semwal --- drivers/pci/pci.c | 4 ---- drivers/pci/setup-res.c | 5 ++--- 2 files changed, 2 insertions(+), 7 deletions(-) -- 2.7.4 diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index a01e6d5..0e53488 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -519,10 +519,6 @@ static void pci_restore_bars(struct pci_dev *dev) { int i; - /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */ - if (dev->is_virtfn) - return; - for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) pci_update_resource(dev, i); } diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index 032a6b1..2506296 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -34,10 +34,9 @@ static void pci_std_update_resource(struct pci_dev *dev, int resno) int reg; struct resource *res = dev->resource + resno; - if (dev->is_virtfn) { - dev_warn(&dev->dev, "can't update VF BAR%d\n", resno); + /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */ + if (dev->is_virtfn) return; - } /* * Ignore resources for unimplemented BARs and unused resource slots From patchwork Sat Mar 25 16:18:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Semwal X-Patchwork-Id: 95989 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp532200qgd; Sat, 25 Mar 2017 09:19:33 -0700 (PDT) X-Received: by 10.84.230.230 with SMTP id e93mr18482477plk.187.1490458773219; Sat, 25 Mar 2017 09:19:33 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3si6723034pli.62.2017.03.25.09.19.33; Sat, 25 Mar 2017 09:19:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751355AbdCYQTd (ORCPT + 5 others); Sat, 25 Mar 2017 12:19:33 -0400 Received: from mail-pf0-f178.google.com ([209.85.192.178]:36621 "EHLO mail-pf0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751309AbdCYQTc (ORCPT ); Sat, 25 Mar 2017 12:19:32 -0400 Received: by mail-pf0-f178.google.com with SMTP id o126so7965708pfb.3 for ; Sat, 25 Mar 2017 09:19:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ap6SFIPRbKON2L/qtwLgwrUxMB5xNoDWf4AlHxHnNkw=; b=d4x42KAQLC4v3LqxjK/g34CE9J9KZoB9olurkwWRpWyK0o9DTOAm/ui+pkmLon3Yus 396kndxaxwT9yfivhibZoaWamVbJJGwjm4bfqjAlXd8aSdPrKz1k6N8BmTTAilPQ35dZ 77mJGc2qMN0iL9fYdNn5H+OGWT6dDIh35gPq4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ap6SFIPRbKON2L/qtwLgwrUxMB5xNoDWf4AlHxHnNkw=; b=q074wac1011sl5zc0mFv39h42E1q+PzWJhkP//QxBgSrwxPCNik71UQh4qZDdz3PIS YtVdITICSI+3U1CfclwePCGVSGWr9uFQgWAwd1KNkhiKLzFHnxCbXZWXz8cC2ylDG2Ur X2qAbcEIxsSPhWnDGGD+y/ILfzoWDMUirWHaR8ehG9XgTisld6bacf1DkIo+zmdJ5ZTB MTti1WTkhBw4asY+9ljpDfRZN93j5FiaAU+jLHmIYRgvwCrce3ntIwqIYqBK9jlxW3IE 7JKsA/7qmTqm2MG1NtbFoqkDSL3c0F28y62bPvR5p2YwXzPFSLdBUS8tl5eS8VfCZULB riCg== X-Gm-Message-State: AFeK/H2ECpWjXBTU/A7XPAi9Ec/DwjIx1SxMWl+gJiRJoYk9Q8HiUOtCpG6u7RqfuNqwaAiQ X-Received: by 10.84.135.34 with SMTP id 31mr18798923pli.50.1490458770871; Sat, 25 Mar 2017 09:19:30 -0700 (PDT) Received: from phantom.lan ([106.51.225.38]) by smtp.gmail.com with ESMTPSA id q194sm11469541pfq.43.2017.03.25.09.19.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 25 Mar 2017 09:19:29 -0700 (PDT) From: Sumit Semwal To: stable@vger.kernel.org Cc: Gavin Shan , Bjorn Helgaas , Sasha Levin , Greg Kroah-Hartman , Sumit Semwal Subject: [PATCH for-4.4 12/19] PCI: Do any VF BAR updates before enabling the BARs Date: Sat, 25 Mar 2017 21:48:12 +0530 Message-Id: <1490458699-24484-13-git-send-email-sumit.semwal@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> References: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Gavin Shan [ Upstream commit f40ec3c748c6912f6266c56a7f7992de61b255ed ] Previously we enabled VFs and enable their memory space before calling pcibios_sriov_enable(). But pcibios_sriov_enable() may update the VF BARs: for example, on PPC PowerNV we may change them to manage the association of VFs to PEs. Because 64-bit BARs cannot be updated atomically, it's unsafe to update them while they're enabled. The half-updated state may conflict with other devices in the system. Call pcibios_sriov_enable() before enabling the VFs so any BAR updates happen while the VF BARs are disabled. [bhelgaas: changelog] Tested-by: Carol Soto Signed-off-by: Gavin Shan Signed-off-by: Bjorn Helgaas Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sumit Semwal --- drivers/pci/iov.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) -- 2.7.4 diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index 47c46d0..3575277 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -303,13 +303,6 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn) return rc; } - pci_iov_set_numvfs(dev, nr_virtfn); - iov->ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE; - pci_cfg_access_lock(dev); - pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl); - msleep(100); - pci_cfg_access_unlock(dev); - iov->initial_VFs = initial; if (nr_virtfn < initial) initial = nr_virtfn; @@ -320,6 +313,13 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn) goto err_pcibios; } + pci_iov_set_numvfs(dev, nr_virtfn); + iov->ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE; + pci_cfg_access_lock(dev); + pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl); + msleep(100); + pci_cfg_access_unlock(dev); + for (i = 0; i < initial; i++) { rc = virtfn_add(dev, i, 0); if (rc) From patchwork Sat Mar 25 16:18:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Semwal X-Patchwork-Id: 95990 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp532210qgd; Sat, 25 Mar 2017 09:19:36 -0700 (PDT) X-Received: by 10.98.201.77 with SMTP id k74mr16185694pfg.74.1490458776055; Sat, 25 Mar 2017 09:19:36 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3si6723034pli.62.2017.03.25.09.19.35; Sat, 25 Mar 2017 09:19:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751359AbdCYQTg (ORCPT + 5 others); Sat, 25 Mar 2017 12:19:36 -0400 Received: from mail-pg0-f50.google.com ([74.125.83.50]:33829 "EHLO mail-pg0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751309AbdCYQTf (ORCPT ); Sat, 25 Mar 2017 12:19:35 -0400 Received: by mail-pg0-f50.google.com with SMTP id 21so9214851pgg.1 for ; Sat, 25 Mar 2017 09:19:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=n5OwpQ+t8u1+jZ0qTOzFWC0MdRvtnECTRownmQq0/CU=; b=ULjLBAhn3dC2jgiWB2bbi2vWFZu0/M6RYcYn3O0SIVsApkoRKUB9vUZXx9zrpTcCFH LT+THI2+VEL9ib48+yfUusaKZpJPh3y0RJn4sWAy8mqyQG5jNiy88cYHYLTQOcCdd0Kj UdWUfxHUS/Cd6ylvkOWbKwzeyd9nOXnRgJozI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=n5OwpQ+t8u1+jZ0qTOzFWC0MdRvtnECTRownmQq0/CU=; b=oNOMI+Huq+ceX7csHm2Y8ILTULwpzKxLFg/3zR20ILuMm+FZld6GBLbqKUOfG6zXMd RpBvs9lXu/4H/lS88ZQ3tCuWZlwVmp7rACqbOTaZa3wqhB+W2gWXE09PsY6gPJyEOvOQ /BHVPAzLCsuLSIhFWkvBeX/Gf8D/vMXI0a1rCr6LeZIKZ29aJjx7FXzxos9ljENgy0Mw +siGyooU7pub9kn7+iuI1lWinIDCIAXzUEGt48XJEnpv7D6lKmFIvUuP6O21Ar6MozMH YT8yICjXs+dY7LGktw7gclY80dknq1r0+93D007EHzfN4gUlrltcuLzyeQFMmgpX3zNq oZSQ== X-Gm-Message-State: AFeK/H3S8cOxHcUHQTnwv0vJLQHqbWc+PiZaJBLeR+B6Eyc/a89d9G5ZTD1+RqPoMzJ9yY3S X-Received: by 10.84.236.76 with SMTP id h12mr11356907pln.110.1490458773976; Sat, 25 Mar 2017 09:19:33 -0700 (PDT) Received: from phantom.lan ([106.51.225.38]) by smtp.gmail.com with ESMTPSA id q194sm11469541pfq.43.2017.03.25.09.19.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 25 Mar 2017 09:19:32 -0700 (PDT) From: Sumit Semwal To: stable@vger.kernel.org Cc: Alexey Kardashevskiy , Michael Ellerman , Sasha Levin , Greg Kroah-Hartman , Sumit Semwal Subject: [PATCH for-4.4 13/19] vfio/spapr: Postpone allocation of userspace version of TCE table Date: Sat, 25 Mar 2017 21:48:13 +0530 Message-Id: <1490458699-24484-14-git-send-email-sumit.semwal@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> References: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Alexey Kardashevskiy [ Upstream commit 39701e56f5f16ea0cf8fc9e8472e645f8de91d23 ] The iommu_table struct manages a hardware TCE table and a vmalloc'd table with corresponding userspace addresses. Both are allocated when the default DMA window is created and this happens when the very first group is attached to a container. As we are going to allow the userspace to configure container in one memory context and pas container fd to another, we have to postpones such allocations till a container fd is passed to the destination user process so we would account locked memory limit against the actual container user constrainsts. This postpones the it_userspace array allocation till it is used first time for mapping. The unmapping patch already checks if the array is allocated. Signed-off-by: Alexey Kardashevskiy Reviewed-by: David Gibson Acked-by: Alex Williamson Signed-off-by: Michael Ellerman Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sumit Semwal --- drivers/vfio/vfio_iommu_spapr_tce.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) -- 2.7.4 diff --git a/drivers/vfio/vfio_iommu_spapr_tce.c b/drivers/vfio/vfio_iommu_spapr_tce.c index 0582b72..1a9f18b 100644 --- a/drivers/vfio/vfio_iommu_spapr_tce.c +++ b/drivers/vfio/vfio_iommu_spapr_tce.c @@ -511,6 +511,12 @@ static long tce_iommu_build_v2(struct tce_container *container, unsigned long hpa; enum dma_data_direction dirtmp; + if (!tbl->it_userspace) { + ret = tce_iommu_userspace_view_alloc(tbl); + if (ret) + return ret; + } + for (i = 0; i < pages; ++i) { struct mm_iommu_table_group_mem_t *mem = NULL; unsigned long *pua = IOMMU_TABLE_USERSPACE_ENTRY(tbl, @@ -584,15 +590,6 @@ static long tce_iommu_create_table(struct tce_container *container, WARN_ON(!ret && !(*ptbl)->it_ops->free); WARN_ON(!ret && ((*ptbl)->it_allocated_size != table_size)); - if (!ret && container->v2) { - ret = tce_iommu_userspace_view_alloc(*ptbl); - if (ret) - (*ptbl)->it_ops->free(*ptbl); - } - - if (ret) - decrement_locked_vm(table_size >> PAGE_SHIFT); - return ret; } @@ -1064,10 +1061,7 @@ static int tce_iommu_take_ownership(struct tce_container *container, if (!tbl || !tbl->it_map) continue; - rc = tce_iommu_userspace_view_alloc(tbl); - if (!rc) - rc = iommu_take_ownership(tbl); - + rc = iommu_take_ownership(tbl); if (rc) { for (j = 0; j < i; ++j) iommu_release_ownership( From patchwork Sat Mar 25 16:18:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Semwal X-Patchwork-Id: 95991 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp532221qgd; Sat, 25 Mar 2017 09:19:39 -0700 (PDT) X-Received: by 10.84.254.5 with SMTP id b5mr4374216plm.76.1490458779776; Sat, 25 Mar 2017 09:19:39 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3si6723034pli.62.2017.03.25.09.19.39; Sat, 25 Mar 2017 09:19:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751360AbdCYQTj (ORCPT + 5 others); Sat, 25 Mar 2017 12:19:39 -0400 Received: from mail-pg0-f44.google.com ([74.125.83.44]:33836 "EHLO mail-pg0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751309AbdCYQTj (ORCPT ); Sat, 25 Mar 2017 12:19:39 -0400 Received: by mail-pg0-f44.google.com with SMTP id 21so9215198pgg.1 for ; Sat, 25 Mar 2017 09:19:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TNT7O0QLCWISB3yrKCiC49+Bd7risWClwuoDPwXayaQ=; b=ZkqYyRAQPdKqJXv7zKeuLB3f6nSDIaozaTafca9OBtNAwMgOOnI75qiBq9eaxrsHuM uMA67vU7k8yAurUgrh0yUSRZ3sbtYu54kEG/I4GU0LMPlaVcGv2N7vq6rdFUuAjniyNc uIqlFVNYQriGpLEXqXHwt3ke0muHb51M25Vc0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TNT7O0QLCWISB3yrKCiC49+Bd7risWClwuoDPwXayaQ=; b=Q7lQd7avj3/kGZRh+3AKsQG6KRobJycHZ9lTXIlxLyO4vAXjYLY3QWjMwkM/Ndxm2/ zzEaW6gG/q/kqpqqHW0PlPpyP86yVnfMCTULrh7WgpUugB9Frjfv+B5yazB04+kNybJg Is4/tS9ZwrAsKvcoo+ELOgKO4mnTwDHRB8LaxBrzuRyGMCq7DlZu6LyO49FLQUsjaEGy 8CjeDIP66Az3r7OWqyPI2YxF8HZsuCf2vUcXRTnz4pA0vJ6nnEmuHYk1Qk8biCJHjiKK /wZEvyhwFJWt0FPexvQWUlxjz/GQLh5DpXdrETTrxPiFjJ8j9WxOB0K7m41VBGU9tLjs /zig== X-Gm-Message-State: AFeK/H0OS2yjXFvJeokCMV4c7G1HcpqM7CGuQfvBECCGzcN4/9yUwCP/2E8ZBMhN1uHpbi7d X-Received: by 10.99.238.69 with SMTP id n5mr15558972pgk.38.1490458777603; Sat, 25 Mar 2017 09:19:37 -0700 (PDT) Received: from phantom.lan ([106.51.225.38]) by smtp.gmail.com with ESMTPSA id q194sm11469541pfq.43.2017.03.25.09.19.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 25 Mar 2017 09:19:36 -0700 (PDT) From: Sumit Semwal To: stable@vger.kernel.org Cc: Mauricio Faria de Oliveira , Brahadambal Srinivasan , Jens Axboe , Sasha Levin , Greg Kroah-Hartman , Sumit Semwal Subject: [PATCH for-4.4 14/19] block: allow WRITE_SAME commands with the SG_IO ioctl Date: Sat, 25 Mar 2017 21:48:14 +0530 Message-Id: <1490458699-24484-15-git-send-email-sumit.semwal@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> References: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Mauricio Faria de Oliveira [ Upstream commit 25cdb64510644f3e854d502d69c73f21c6df88a9 ] The WRITE_SAME commands are not present in the blk_default_cmd_filter write_ok list, and thus are failed with -EPERM when the SG_IO ioctl() is executed without CAP_SYS_RAWIO capability (e.g., unprivileged users). [ sg_io() -> blk_fill_sghdr_rq() > blk_verify_command() -> -EPERM ] The problem can be reproduced with the sg_write_same command # sg_write_same --num 1 --xferlen 512 /dev/sda # # capsh --drop=cap_sys_rawio -- -c \ 'sg_write_same --num 1 --xferlen 512 /dev/sda' Write same: pass through os error: Operation not permitted # For comparison, the WRITE_VERIFY command does not observe this problem, since it is in that list: # capsh --drop=cap_sys_rawio -- -c \ 'sg_write_verify --num 1 --ilen 512 --lba 0 /dev/sda' # So, this patch adds the WRITE_SAME commands to the list, in order for the SG_IO ioctl to finish successfully: # capsh --drop=cap_sys_rawio -- -c \ 'sg_write_same --num 1 --xferlen 512 /dev/sda' # That case happens to be exercised by QEMU KVM guests with 'scsi-block' devices (qemu "-device scsi-block" [1], libvirt "" [2]), which employs the SG_IO ioctl() and runs as an unprivileged user (libvirt-qemu). In that scenario, when a filesystem (e.g., ext4) performs its zero-out calls, which are translated to write-same calls in the guest kernel, and then into SG_IO ioctls to the host kernel, SCSI I/O errors may be observed in the guest: [...] sd 0:0:0:0: [sda] tag#0 FAILED Result: hostbyte=DID_OK driverbyte=DRIVER_SENSE [...] sd 0:0:0:0: [sda] tag#0 Sense Key : Aborted Command [current] [...] sd 0:0:0:0: [sda] tag#0 Add. Sense: I/O process terminated [...] sd 0:0:0:0: [sda] tag#0 CDB: Write Same(10) 41 00 01 04 e0 78 00 00 08 00 [...] blk_update_request: I/O error, dev sda, sector 17096824 Links: [1] http://git.qemu.org/?p=qemu.git;a=commit;h=336a6915bc7089fb20fea4ba99972ad9a97c5f52 [2] https://libvirt.org/formatdomain.html#elementsDisks (see 'disk' -> 'device') Signed-off-by: Mauricio Faria de Oliveira Signed-off-by: Brahadambal Srinivasan Reported-by: Manjunatha H R Reviewed-by: Christoph Hellwig Signed-off-by: Jens Axboe Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sumit Semwal --- block/scsi_ioctl.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.7.4 diff --git a/block/scsi_ioctl.c b/block/scsi_ioctl.c index 0774799..c6fee74 100644 --- a/block/scsi_ioctl.c +++ b/block/scsi_ioctl.c @@ -182,6 +182,9 @@ static void blk_set_cmd_filter_defaults(struct blk_cmd_filter *filter) __set_bit(WRITE_16, filter->write_ok); __set_bit(WRITE_LONG, filter->write_ok); __set_bit(WRITE_LONG_2, filter->write_ok); + __set_bit(WRITE_SAME, filter->write_ok); + __set_bit(WRITE_SAME_16, filter->write_ok); + __set_bit(WRITE_SAME_32, filter->write_ok); __set_bit(ERASE, filter->write_ok); __set_bit(GPCMD_MODE_SELECT_10, filter->write_ok); __set_bit(MODE_SELECT, filter->write_ok); From patchwork Sat Mar 25 16:18:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Semwal X-Patchwork-Id: 95992 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp532237qgd; Sat, 25 Mar 2017 09:19:43 -0700 (PDT) X-Received: by 10.98.58.7 with SMTP id h7mr16109264pfa.234.1490458783384; Sat, 25 Mar 2017 09:19:43 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[209.132.180.67]) by mx.google.com with ESMTP id r3si6723034pli.62.2017.03.25.09.19.46; Sat, 25 Mar 2017 09:19:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751364AbdCYQTq (ORCPT + 5 others); Sat, 25 Mar 2017 12:19:46 -0400 Received: from mail-pf0-f176.google.com ([209.85.192.176]:34165 "EHLO mail-pf0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751309AbdCYQTp (ORCPT ); Sat, 25 Mar 2017 12:19:45 -0400 Received: by mail-pf0-f176.google.com with SMTP id p189so8002680pfp.1 for ; Sat, 25 Mar 2017 09:19:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8DEhyLKBDQCZGGKBYXyziKmBumwTrnOxxVQ2RjMNEbw=; b=jZ3TpCzEKitdEeQENX3BCP+FKC9G0EkI8J3XTrUrjplC8SFe8AgEugwhjYLGyw7d8j tSBcG0HopQsOfb4+bAsJcEj2vWxxZDVd2QNWw2JR2+0dEOyA0BsGv9EIGu7kbiszmXBC Ne7LEeGLj/5ovOynGOxE2SByQT8CUEl9YDfwg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8DEhyLKBDQCZGGKBYXyziKmBumwTrnOxxVQ2RjMNEbw=; b=cpvDmN3tRaUkRpVxLxG8vCFA+Ua2m6A1pZdQu7nNRk61LG1anTogikFJbP+z+ztj4D gyMBbrjp3OfSUX82lfgq4eWVFXaPmy5bL5lsOxBgIdnSnABXrQjDDpq0MKQ/iXa95Sgv vKIXMoMcNNQ5bBj7Ev9VsfCj13MxwmjurQms6oIob1uYu3hdMgG1fPx0fbkNGlq2PBmh C6iZcSsPFtafgiNbmDndBM3vd5P6cUOlLO4DP/N2a4qIp61Q9Jqq29t4Qz/vC7puNZZl ZkE2ar2gyM17JvdmEkPM9mV4BYhBqrh8OnMqI6VAKVlFeFjAVxyMM1LVE8N9NPDSblfx ULpw== X-Gm-Message-State: AFeK/H1rfWDWX1rw2owMtfeKjOJQmKBX+//p1OCLBKRWMlk6+3P2uxFhkiVPj4xlgPgXjwGP X-Received: by 10.99.45.2 with SMTP id t2mr15411197pgt.209.1490458784283; Sat, 25 Mar 2017 09:19:44 -0700 (PDT) Received: from phantom.lan ([106.51.225.38]) by smtp.gmail.com with ESMTPSA id q194sm11469541pfq.43.2017.03.25.09.19.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 25 Mar 2017 09:19:43 -0700 (PDT) From: Sumit Semwal To: stable@vger.kernel.org Cc: Henrik Ingo , Laurent Pinchart , Mauro Carvalho Chehab , Sasha Levin , Greg Kroah-Hartman , Sumit Semwal Subject: [PATCH for-4.4 16/19] uvcvideo: uvc_scan_fallback() for webcams with broken chain Date: Sat, 25 Mar 2017 21:48:16 +0530 Message-Id: <1490458699-24484-17-git-send-email-sumit.semwal@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> References: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Henrik Ingo [ Upstream commit e950267ab802c8558f1100eafd4087fd039ad634 ] Some devices have invalid baSourceID references, causing uvc_scan_chain() to fail, but if we just take the entities we can find and put them together in the most sensible chain we can think of, turns out they do work anyway. Note: This heuristic assumes there is a single chain. At the time of writing, devices known to have such a broken chain are - Acer Integrated Camera (5986:055a) - Realtek rtl157a7 (0bda:57a7) Signed-off-by: Henrik Ingo Signed-off-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sumit Semwal --- drivers/media/usb/uvc/uvc_driver.c | 118 +++++++++++++++++++++++++++++++++++-- 1 file changed, 112 insertions(+), 6 deletions(-) -- 2.7.4 diff --git a/drivers/media/usb/uvc/uvc_driver.c b/drivers/media/usb/uvc/uvc_driver.c index 5cefca9..885f689 100644 --- a/drivers/media/usb/uvc/uvc_driver.c +++ b/drivers/media/usb/uvc/uvc_driver.c @@ -1595,6 +1595,114 @@ static const char *uvc_print_chain(struct uvc_video_chain *chain) return buffer; } +static struct uvc_video_chain *uvc_alloc_chain(struct uvc_device *dev) +{ + struct uvc_video_chain *chain; + + chain = kzalloc(sizeof(*chain), GFP_KERNEL); + if (chain == NULL) + return NULL; + + INIT_LIST_HEAD(&chain->entities); + mutex_init(&chain->ctrl_mutex); + chain->dev = dev; + v4l2_prio_init(&chain->prio); + + return chain; +} + +/* + * Fallback heuristic for devices that don't connect units and terminals in a + * valid chain. + * + * Some devices have invalid baSourceID references, causing uvc_scan_chain() + * to fail, but if we just take the entities we can find and put them together + * in the most sensible chain we can think of, turns out they do work anyway. + * Note: This heuristic assumes there is a single chain. + * + * At the time of writing, devices known to have such a broken chain are + * - Acer Integrated Camera (5986:055a) + * - Realtek rtl157a7 (0bda:57a7) + */ +static int uvc_scan_fallback(struct uvc_device *dev) +{ + struct uvc_video_chain *chain; + struct uvc_entity *iterm = NULL; + struct uvc_entity *oterm = NULL; + struct uvc_entity *entity; + struct uvc_entity *prev; + + /* + * Start by locating the input and output terminals. We only support + * devices with exactly one of each for now. + */ + list_for_each_entry(entity, &dev->entities, list) { + if (UVC_ENTITY_IS_ITERM(entity)) { + if (iterm) + return -EINVAL; + iterm = entity; + } + + if (UVC_ENTITY_IS_OTERM(entity)) { + if (oterm) + return -EINVAL; + oterm = entity; + } + } + + if (iterm == NULL || oterm == NULL) + return -EINVAL; + + /* Allocate the chain and fill it. */ + chain = uvc_alloc_chain(dev); + if (chain == NULL) + return -ENOMEM; + + if (uvc_scan_chain_entity(chain, oterm) < 0) + goto error; + + prev = oterm; + + /* + * Add all Processing and Extension Units with two pads. The order + * doesn't matter much, use reverse list traversal to connect units in + * UVC descriptor order as we build the chain from output to input. This + * leads to units appearing in the order meant by the manufacturer for + * the cameras known to require this heuristic. + */ + list_for_each_entry_reverse(entity, &dev->entities, list) { + if (entity->type != UVC_VC_PROCESSING_UNIT && + entity->type != UVC_VC_EXTENSION_UNIT) + continue; + + if (entity->num_pads != 2) + continue; + + if (uvc_scan_chain_entity(chain, entity) < 0) + goto error; + + prev->baSourceID[0] = entity->id; + prev = entity; + } + + if (uvc_scan_chain_entity(chain, iterm) < 0) + goto error; + + prev->baSourceID[0] = iterm->id; + + list_add_tail(&chain->list, &dev->chains); + + uvc_trace(UVC_TRACE_PROBE, + "Found a video chain by fallback heuristic (%s).\n", + uvc_print_chain(chain)); + + return 0; + +error: + kfree(chain); + return -EINVAL; +} + /* * Scan the device for video chains and register video devices. * @@ -1617,15 +1725,10 @@ static int uvc_scan_device(struct uvc_device *dev) if (term->chain.next || term->chain.prev) continue; - chain = kzalloc(sizeof(*chain), GFP_KERNEL); + chain = uvc_alloc_chain(dev); if (chain == NULL) return -ENOMEM; - INIT_LIST_HEAD(&chain->entities); - mutex_init(&chain->ctrl_mutex); - chain->dev = dev; - v4l2_prio_init(&chain->prio); - term->flags |= UVC_ENTITY_FLAG_DEFAULT; if (uvc_scan_chain(chain, term) < 0) { @@ -1639,6 +1742,9 @@ static int uvc_scan_device(struct uvc_device *dev) list_add_tail(&chain->list, &dev->chains); } + if (list_empty(&dev->chains)) + uvc_scan_fallback(dev); + if (list_empty(&dev->chains)) { uvc_printk(KERN_INFO, "No valid video chain found.\n"); return -1; From patchwork Sat Mar 25 16:18:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Semwal X-Patchwork-Id: 95994 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp532270qgd; Sat, 25 Mar 2017 09:19:49 -0700 (PDT) X-Received: by 10.84.168.4 with SMTP id e4mr18373843plb.138.1490458789814; Sat, 25 Mar 2017 09:19:49 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Wysocki" , Sasha Levin , Greg Kroah-Hartman , Sumit Semwal Subject: [PATCH for-4.4 17/19] ACPI / blacklist: add _REV quirks for Dell Precision 5520 and 3520 Date: Sat, 25 Mar 2017 21:48:17 +0530 Message-Id: <1490458699-24484-18-git-send-email-sumit.semwal@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> References: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Alex Hung [ Upstream commit 9523b9bf6dceef6b0215e90b2348cd646597f796 ] Precision 5520 and 3520 either hang at login and during suspend or reboot. It turns out that that adding them to acpi_rev_dmi_table[] helps to work around those issues. Signed-off-by: Alex Hung [ rjw: Changelog ] Signed-off-by: Rafael J. Wysocki Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sumit Semwal --- drivers/acpi/blacklist.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.7.4 diff --git a/drivers/acpi/blacklist.c b/drivers/acpi/blacklist.c index 96809cd..b2e9395 100644 --- a/drivers/acpi/blacklist.c +++ b/drivers/acpi/blacklist.c @@ -346,6 +346,22 @@ static struct dmi_system_id acpi_osi_dmi_table[] __initdata = { DMI_MATCH(DMI_PRODUCT_NAME, "XPS 13 9343"), }, }, + { + .callback = dmi_enable_rev_override, + .ident = "DELL Precision 5520", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "Precision 5520"), + }, + }, + { + .callback = dmi_enable_rev_override, + .ident = "DELL Precision 3520", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3520"), + }, + }, #endif {} }; From patchwork Sat Mar 25 16:18:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Semwal X-Patchwork-Id: 95995 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp532290qgd; Sat, 25 Mar 2017 09:19:53 -0700 (PDT) X-Received: by 10.99.136.199 with SMTP id l190mr15326553pgd.92.1490458792925; Sat, 25 Mar 2017 09:19:52 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Wysocki" , Sasha Levin , Greg Kroah-Hartman , Sumit Semwal Subject: [PATCH for-4.4 18/19] ACPI / blacklist: Make Dell Latitude 3350 ethernet work Date: Sat, 25 Mar 2017 21:48:18 +0530 Message-Id: <1490458699-24484-19-git-send-email-sumit.semwal@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> References: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Michael Pobega [ Upstream commit 708f5dcc21ae9b35f395865fc154b0105baf4de4 ] The Dell Latitude 3350's ethernet card attempts to use a reserved IRQ (18), resulting in ACPI being unable to enable the ethernet. Adding it to acpi_rev_dmi_table[] helps to work around this problem. Signed-off-by: Michael Pobega [ rjw: Changelog ] Signed-off-by: Rafael J. Wysocki Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sumit Semwal --- drivers/acpi/blacklist.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.7.4 diff --git a/drivers/acpi/blacklist.c b/drivers/acpi/blacklist.c index b2e9395..2f24b57 100644 --- a/drivers/acpi/blacklist.c +++ b/drivers/acpi/blacklist.c @@ -362,6 +362,18 @@ static struct dmi_system_id acpi_osi_dmi_table[] __initdata = { DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3520"), }, }, + /* + * Resolves a quirk with the Dell Latitude 3350 that + * causes the ethernet adapter to not function. + */ + { + .callback = dmi_enable_rev_override, + .ident = "DELL Latitude 3350", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "Latitude 3350"), + }, + }, #endif {} }; From patchwork Sat Mar 25 16:18:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Semwal X-Patchwork-Id: 95996 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp532301qgd; Sat, 25 Mar 2017 09:19:56 -0700 (PDT) X-Received: by 10.84.238.198 with SMTP id l6mr2024060pln.180.1490458796031; Sat, 25 Mar 2017 09:19:56 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3si6723034pli.62.2017.03.25.09.19.55; Sat, 25 Mar 2017 09:19:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751369AbdCYQT4 (ORCPT + 5 others); Sat, 25 Mar 2017 12:19:56 -0400 Received: from mail-pg0-f51.google.com ([74.125.83.51]:33863 "EHLO mail-pg0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751309AbdCYQTz (ORCPT ); Sat, 25 Mar 2017 12:19:55 -0400 Received: by mail-pg0-f51.google.com with SMTP id 21so9216782pgg.1 for ; Sat, 25 Mar 2017 09:19:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hJPf7RJxau8VbD3E7u+sG2cCpRhrCdqE2BZU50yPUsE=; b=gRXAQWMgUTd9haZ5pM91LZXnKvpyhfX6H6xWvEFOOXqVndXSoTtv02yKk0dhHO29Kq q04kTJbS5opyJs9scXvYj3gP093DCLrJ3l+UlBCeTB7zEmBil7MDJls/oyYpXSvIEwsx ISSnIKtJ6F0IG6cEpBqpP0PiXZaigHVgGflZc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hJPf7RJxau8VbD3E7u+sG2cCpRhrCdqE2BZU50yPUsE=; b=lF556mwhJQVXCd4JLZQkEHpJrJjtJMRwGLwZEdzfnT0nF4oqlpVaGpQobEFUsNCLVf 8JkRlRQR/D9+llmKH6hHhW6DWABi3c9K26arGPehhkijtFKLiFcb2hEkXZNjol+lihsm qqJx5T1G0G1rDTfqydGXsvBARI+KUep6cwV6PQg6DjiCv8IuqtUGfZziXd3dvAsw3LaB MUsemBmpMIttem2u+0Cms0KvstQRwIz3ysNB7pS9BF5JvyQC0fXPfwQ2ihXo3gU79viR owmJmlz6gzmmkiA/eeB4y+Q8PAC59huysfZhWW1p9dgVeR2G/51BcB9UlNK2raQL1Tl9 Szvg== X-Gm-Message-State: AFeK/H2AbeTbzY/2cQtSibeQSWpYO71IE9GEgTBvFmuq4EHU0KYVXkl0VZ+3IRo46a7g6zbM X-Received: by 10.99.61.201 with SMTP id k192mr15489127pga.68.1490458793914; Sat, 25 Mar 2017 09:19:53 -0700 (PDT) Received: from phantom.lan ([106.51.225.38]) by smtp.gmail.com with ESMTPSA id q194sm11469541pfq.43.2017.03.25.09.19.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 25 Mar 2017 09:19:52 -0700 (PDT) From: Sumit Semwal To: stable@vger.kernel.org Cc: Gabriel Krisman Bertazi , Greg Kroah-Hartman , Sasha Levin , Sumit Semwal Subject: [PATCH for-4.4 19/19] serial: 8250_pci: Detach low-level driver during PCI error recovery Date: Sat, 25 Mar 2017 21:48:19 +0530 Message-Id: <1490458699-24484-20-git-send-email-sumit.semwal@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> References: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Gabriel Krisman Bertazi [ Upstream commit f209fa03fc9d131b3108c2e4936181eabab87416 ] During a PCI error recovery, like the ones provoked by EEH in the ppc64 platform, all IO to the device must be blocked while the recovery is completed. Current 8250_pci implementation only suspends the port instead of detaching it, which doesn't prevent incoming accesses like TIOCMGET and TIOCMSET calls from reaching the device. Those end up racing with the EEH recovery, crashing it. Similar races were also observed when opening the device and when shutting it down during recovery. This patch implements a more robust IO blockage for the 8250_pci recovery by unregistering the port at the beginning of the procedure and re-adding it afterwards. Since the port is detached from the uart layer, we can be sure that no request will make through to the device during recovery. This is similar to the solution used by the JSM serial driver. I thank Peter Hurley for valuable input on this one over one year ago. Signed-off-by: Gabriel Krisman Bertazi Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sumit Semwal --- drivers/tty/serial/8250/8250_pci.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) -- 2.7.4 diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c index 5b24ffd..83ff172 100644 --- a/drivers/tty/serial/8250/8250_pci.c +++ b/drivers/tty/serial/8250/8250_pci.c @@ -57,6 +57,7 @@ struct serial_private { unsigned int nr; void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES]; struct pci_serial_quirk *quirk; + const struct pciserial_board *board; int line[0]; }; @@ -4058,6 +4059,7 @@ pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) } } priv->nr = i; + priv->board = board; return priv; err_deinit: @@ -4068,7 +4070,7 @@ err_out: } EXPORT_SYMBOL_GPL(pciserial_init_ports); -void pciserial_remove_ports(struct serial_private *priv) +void pciserial_detach_ports(struct serial_private *priv) { struct pci_serial_quirk *quirk; int i; @@ -4088,7 +4090,11 @@ void pciserial_remove_ports(struct serial_private *priv) quirk = find_quirk(priv->dev); if (quirk->exit) quirk->exit(priv->dev); +} +void pciserial_remove_ports(struct serial_private *priv) +{ + pciserial_detach_ports(priv); kfree(priv); } EXPORT_SYMBOL_GPL(pciserial_remove_ports); @@ -5819,7 +5825,7 @@ static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, return PCI_ERS_RESULT_DISCONNECT; if (priv) - pciserial_suspend_ports(priv); + pciserial_detach_ports(priv); pci_disable_device(dev); @@ -5844,9 +5850,18 @@ static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) static void serial8250_io_resume(struct pci_dev *dev) { struct serial_private *priv = pci_get_drvdata(dev); + const struct pciserial_board *board; - if (priv) - pciserial_resume_ports(priv); + if (!priv) + return; + + board = priv->board; + kfree(priv); + priv = pciserial_init_ports(dev, board); + + if (!IS_ERR(priv)) { + pci_set_drvdata(dev, priv); + } } static const struct pci_error_handlers serial8250_err_handler = {