From patchwork Wed Feb 14 03:49:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 128304 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp186135ljc; Tue, 13 Feb 2018 19:50:29 -0800 (PST) X-Google-Smtp-Source: AH8x2256nkl5RrYIf79xgBU3I08DQj+UobnjLFPCEQ2ZUzWEBug6RcnDfe9/DUSOd9nmixTd0jHJ X-Received: by 10.99.5.197 with SMTP id 188mr2756638pgf.196.1518580229487; Tue, 13 Feb 2018 19:50:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518580229; cv=none; d=google.com; s=arc-20160816; b=zWwgmNFe1Q4KpmpwPilDQZ622veGMV3zze54OlAn1OSfONPwOSgo2OK7iJkMFMK3gz WD/jhmkSRFEqSs2AU4BtktVN2GvFsiPU5tIyH/FPxPM5TpjyMG5E1qTSdNzYwrb80rck 8WMjD6NaR+fZHZvaaG7nMuDAin9XF8f606BHaxmD+/1Jye7xPdrJp262jJlyWGaozajc J6toVG5F+QhABkpQ9Ok9H40DI/eYSzRZ2dtgde5LPC8kpRNvbyJVvpihegpJ2y8+fluY rgOz/FTCuk5DTY/NWVEuEQYqrNaHrlYs8GFpeYfrp3bGUcEbiQ1c6eYvnQC+InfAYWU4 r29w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:to:from:dkim-signature:arc-authentication-results; bh=j+e8zjGL/a6pJXiUE2ARCYfYacO85JK3k9DrZe8f2Ks=; b=K1ExILic3+G/G+yq4E9fpQd1eotJ3yE9TP9DHWaB9aeY7SyE2yldMc2lAN8pPzYqsU TG7Z5+TAFTWtq7DSJR0maYr8sspaSZOyBmmvUvDP0gbmRC63FmdTfzxcAGfa84Xy0tny hnzM023PLIfj427ZP5L7z0MGzeYK5+9fO7/7C5oxU1FAv2/D56LsuNwNfWW/RRVCeloW LYBZQclxVbDwNGPfFWnWSPda09ewlwPT999ZKSz7Yn1BrqRWceXJYKDUhPNcNn50c8qc Io61lqDzb/CVH1c2SzVyWCCmL4kr7Z/uSq4alFrS46VJoww2eshNPQwOSHvoy2GHbrci pDqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GtULeT8s; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l22si7519778pgn.578.2018.02.13.19.50.29; Tue, 13 Feb 2018 19:50:29 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GtULeT8s; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966817AbeBNDu0 (ORCPT + 28 others); Tue, 13 Feb 2018 22:50:26 -0500 Received: from mail-qk0-f194.google.com ([209.85.220.194]:37697 "EHLO mail-qk0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S966671AbeBNDuW (ORCPT ); Tue, 13 Feb 2018 22:50:22 -0500 Received: by mail-qk0-f194.google.com with SMTP id c128so25121145qkb.4 for ; Tue, 13 Feb 2018 19:50:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=j+e8zjGL/a6pJXiUE2ARCYfYacO85JK3k9DrZe8f2Ks=; b=GtULeT8sxJgms2pt1eTTQNgh9S4jvjONOdjsrW06OLJtKdfvSSeTNOmAwZE42/5095 j+luss3DLpEeLonvkE4IBLVFffjeHYSOdXKOMcOy4O2MH0HVVjWw8JtNjIYZrib+97gF peuAm2tbvWo0al1JKRXuX9tkHWeN1sAFltDlU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=j+e8zjGL/a6pJXiUE2ARCYfYacO85JK3k9DrZe8f2Ks=; b=DU8u6YUf0uSjJYGhH4MvT8QjdrUkikRc4xiFiNfUXqHrcTKxkEbeDTcufFk9c80oOq 04ufxNuNgJMrQJSg8UaBLNNaweMzLqn5/zrh0EmlozuyFaI+QiW8ai1yUYCM3ZC//F0U 9oSp5FScFgg7PenpVUJr67w8wJ0jZW9/B45gqd1HOTBa4mC4sWKFnZRfjB+4Yo8gfN2I hNsfICxJ/90/1mw7UAth3GYu1o24MsED/mVWcoUIUzUwLjy/j91pXv3jd6WU8TBYS3g8 rngwuRlb3cdWMStHw6qn02TCk4ogGmEJ0sLs8wc0kMySh59PFidOOTHwxzXWYCeCl6sW OqyQ== X-Gm-Message-State: APf1xPBHZvvSSic8+vjA0vQMne+crTbTRPU39SXKXSs2TJvyRToGaA+w k3Yj1F4i9NIwFwR/VGrHW8jJgQ== X-Received: by 10.55.95.4 with SMTP id t4mr5624127qkb.102.1518580221842; Tue, 13 Feb 2018 19:50:21 -0800 (PST) Received: from localhost.localdomain ([45.77.212.61]) by smtp.gmail.com with ESMTPSA id h45sm8913800qtc.34.2018.02.13.19.50.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 13 Feb 2018 19:50:20 -0800 (PST) From: Leo Yan To: Rob Herring , Mark Rutland , Wei Xu , Jassi Brar , Leo Yan , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Kaihua Zhong , Guodong Xu , Haojian Zhuang Subject: [PATCH RESEND v5 1/3] dt-bindings: mailbox: Introduce Hi3660 controller binding Date: Wed, 14 Feb 2018 11:49:49 +0800 Message-Id: <1518580191-26451-2-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1518580191-26451-1-git-send-email-leo.yan@linaro.org> References: <1518580191-26451-1-git-send-email-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Introduce a binding for the Hi3660 mailbox controller, the mailbox is used within application processor (AP), communication processor (CP), HIFI and MCU, etc. Acked-by: Rob Herring Signed-off-by: Leo Yan --- .../bindings/mailbox/hisilicon,hi3660-mailbox.txt | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt -- 1.9.1 diff --git a/Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt b/Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt new file mode 100644 index 0000000..3e5b453 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt @@ -0,0 +1,51 @@ +Hisilicon Hi3660 Mailbox Controller + +Hisilicon Hi3660 mailbox controller supports up to 32 channels. Messages +are passed between processors, including application & communication +processors, MCU, HIFI, etc. Each channel is unidirectional and accessed +by using MMIO registers; it supports maximum to 8 words message. + +Controller +---------- + +Required properties: +- compatible: : Shall be "hisilicon,hi3660-mbox" +- reg: : Offset and length of the device's register set +- #mbox-cells: : Must be 3 + <&phandle channel dst_irq ack_irq> + phandle : Label name of controller + channel : Channel number + dst_irq : Remote interrupt vector + ack_irq : Local interrupt vector + +- interrupts: : Contains the two IRQ lines for mailbox. + +Example: + +mailbox: mailbox@e896b000 { + compatible = "hisilicon,hi3660-mbox"; + reg = <0x0 0xe896b000 0x0 0x1000>; + interrupts = <0x0 0xc0 0x4>, + <0x0 0xc1 0x4>; + #mbox-cells = <3>; +}; + +Client +------ + +Required properties: +- compatible : See the client docs +- mboxes : Standard property to specify a Mailbox (See ./mailbox.txt) + Cells must match 'mbox-cells' (See Controller docs above) + +Optional properties +- mbox-names : Name given to channels seen in the 'mboxes' property. + +Example: + +stub_clock: stub_clock@e896b500 { + compatible = "hisilicon,hi3660-stub-clk"; + reg = <0x0 0xe896b500 0x0 0x0100>; + #clock-cells = <1>; + mboxes = <&mailbox 13 3 0>; +}; From patchwork Wed Feb 14 03:49:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 128305 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp186210ljc; Tue, 13 Feb 2018 19:50:37 -0800 (PST) X-Google-Smtp-Source: AH8x226o0E6dSMkgZl3KyJDDaP3a8BrWU2bahOizgsRgYLV9TExzUplBw3o6WhqFJvuQVeEcR/pv X-Received: by 10.99.108.72 with SMTP id h69mr2709588pgc.302.1518580237011; Tue, 13 Feb 2018 19:50:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518580237; cv=none; d=google.com; s=arc-20160816; b=fyrJTg13k5dOn6YzIdF0UZu81oaAmfCckhor0YIdUO8H4BvpxQF8vzbGX3jWppJOzE nW+ltmReLrT3DqBxt93TrywE0M1Kx69gN1q02uzfKKbT1SweHHj4oWdDrEVHauYeuxzp 5TL6gUU16smnRreLbOWhwrRrLHPo9sEDvIFnGmOXPyG02Xwyo0imgRKtOcwv/h54csia TOcePjSF+2FKTwfpMv+NhvMiDqERIjrG7zMwwjxFH40AE+zxOmvSgVQ2ARg+Kfco000u 7wY2C1Dab3nFsOixGBDTjjbnE7BsFZf96RJg5ynXPpypsrTpKcrC0dX8PUgnGhRJYYKF 996w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=whqJd5nk5GgCTDp98JfhTUG6ERrapL06Eum4V67M9QU=; b=zzRljkptfwtStR+tGCArxHAoiiNtzWGPdW1mOfwkIIj/haDjvUmoHsYMZ1PbLVKQfF f2mFYsp44BXbRytjRbAxhH7qH/XYvKYJtnSmZz8wvvfXZ/nB43wnDu8m3GOPEYN2ARy5 Oir8u5Tow1Kssk8dTHeRlGfiD56aR/r6MjWnHl1MjtK0nNBSbe+KJnrw5pUL11PLp8kO 4XNcn2Q5qVx5OsH4OLw9M2DRJ0FITokFnrQsy6m2rlViEYhRAIkNRiA7WIv3qXIEgomw vJOZyGmI9br9saz7/Hr+frsHoNIzh+qwz5sy+NkPMn6WdiebFyxmcIM9KP+dp2pE/klw OULA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SwqC0Jbo; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s9si403897pgr.373.2018.02.13.19.50.36; Tue, 13 Feb 2018 19:50:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SwqC0Jbo; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966833AbeBNDue (ORCPT + 28 others); Tue, 13 Feb 2018 22:50:34 -0500 Received: from mail-qt0-f195.google.com ([209.85.216.195]:37933 "EHLO mail-qt0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S966671AbeBNDu2 (ORCPT ); Tue, 13 Feb 2018 22:50:28 -0500 Received: by mail-qt0-f195.google.com with SMTP id k13so6212477qtg.5 for ; Tue, 13 Feb 2018 19:50:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=whqJd5nk5GgCTDp98JfhTUG6ERrapL06Eum4V67M9QU=; b=SwqC0JboxSfSHDU4oENFkPY3rxv6rLI8aWns72/173G5DrxA9PMWw3dMizuXlxoHfE is2DrVKd07a82OCl0PfY2S/JDVLhY1kBUez8y0QSkYD9ZMFmuGNASJVMr3IMi4h7nQ2h 8QW6K/MdVltbSH4jhlt8j3PaLj2+bwcgkVK54= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=whqJd5nk5GgCTDp98JfhTUG6ERrapL06Eum4V67M9QU=; b=K5YgftxrJ6sxdS1XjqHf/BuUHiNXxLbv8QHxuvhMQUSkilrIRrMMV6Ejag3rmGsLpx fr1cIfT73QFVB0nPEsPamRzwJMSUxSOQpIbyFTTJuYr5b0NQVRWfQW2pBSIzoYequC7y JlNsiKSVHnnLy/THYxajnnjIKkGD3LvUhwq0LfodKpegQY6i7NP0aDuqKKvXoq+tM3h3 n5BDHFgvH1edAcb2uLlbmEfq2g3tUQZ588F0oMu+TpmNv1a65JIlPZaodfzwGdMJHFzf lovaGcl3aqtsX38BTib4GnfOse+d9ZgicV9WR1vu+RX+iudkb4LcBQbVrcXy0gFV0HjA MmPA== X-Gm-Message-State: APf1xPBVZCSCXQqqRdH37XebX33lPhw/o4frUWh6XkOrsJ9sVJB4XK3A NimyRGSlK/LNQnaulXFxjFMdPw== X-Received: by 10.200.61.90 with SMTP id u26mr5498820qtf.168.1518580227829; Tue, 13 Feb 2018 19:50:27 -0800 (PST) Received: from localhost.localdomain ([45.77.212.61]) by smtp.gmail.com with ESMTPSA id h45sm8913800qtc.34.2018.02.13.19.50.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 13 Feb 2018 19:50:26 -0800 (PST) From: Leo Yan To: Rob Herring , Mark Rutland , Wei Xu , Jassi Brar , Leo Yan , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Kaihua Zhong , Guodong Xu , Haojian Zhuang Cc: Ruyi Wang Subject: [PATCH RESEND v5 2/3] mailbox: Add support for Hi3660 mailbox Date: Wed, 14 Feb 2018 11:49:50 +0800 Message-Id: <1518580191-26451-3-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1518580191-26451-1-git-send-email-leo.yan@linaro.org> References: <1518580191-26451-1-git-send-email-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Kaihua Zhong Hi3660 mailbox controller is used to send message within multiple processors, MCU, HIFI, etc. It supports 32 mailbox channels and every channel can only be used for single transferring direction. Once the channel is enabled, it needs to specify the destination interrupt and acknowledge interrupt, these two interrupt vectors are used to create the connection between the mailbox and interrupt controllers. The data transferring supports two modes, one is named as "automatic acknowledge" mode so after send message the kernel doesn't need to wait for acknowledge from remote and directly return; there have another mode is to rely on handling interrupt for acknowledge. This commit is for initial version driver, which only supports "automatic acknowledge" mode to support CPU clock, which is the only one consumer to use mailbox and has been verified. Later may enhance this driver for interrupt mode (e.g. for supporting HIFI). Signed-off-by: Leo Yan Signed-off-by: Ruyi Wang Signed-off-by: Kaihua Zhong --- drivers/mailbox/Kconfig | 8 + drivers/mailbox/Makefile | 2 + drivers/mailbox/hi3660-mailbox.c | 316 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 326 insertions(+) create mode 100644 drivers/mailbox/hi3660-mailbox.c -- 1.9.1 diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index ba2f152..de8390d4 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -108,6 +108,14 @@ config TI_MESSAGE_MANAGER multiple processors within the SoC. Select this driver if your platform has support for the hardware block. +config HI3660_MBOX + tristate "Hi3660 Mailbox" + depends on ARCH_HISI && OF + help + An implementation of the hi3660 mailbox. It is used to send message + between application processors and other processors/MCU/DSP. Select + Y here if you want to use Hi3660 mailbox controller. + config HI6220_MBOX tristate "Hi6220 Mailbox" depends on ARCH_HISI diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 4896f8d..cc23c3a 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -27,6 +27,8 @@ obj-$(CONFIG_TI_MESSAGE_MANAGER) += ti-msgmgr.o obj-$(CONFIG_XGENE_SLIMPRO_MBOX) += mailbox-xgene-slimpro.o +obj-$(CONFIG_HI3660_MBOX) += hi3660-mailbox.o + obj-$(CONFIG_HI6220_MBOX) += hi6220-mailbox.o obj-$(CONFIG_BCM_PDC_MBOX) += bcm-pdc-mailbox.o diff --git a/drivers/mailbox/hi3660-mailbox.c b/drivers/mailbox/hi3660-mailbox.c new file mode 100644 index 0000000..d6b1600 --- /dev/null +++ b/drivers/mailbox/hi3660-mailbox.c @@ -0,0 +1,316 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Hisilicon Limited. +// Copyright (c) 2017 Linaro Limited. + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mailbox.h" + +#define MBOX_CHAN_MAX 32 + +#define MBOX_RX 0x0 +#define MBOX_TX 0x1 + +#define MBOX_BASE(mbox, ch) ((mbox)->base + ((ch) * 0x40)) +#define MBOX_SRC_REG 0x00 +#define MBOX_DST_REG 0x04 +#define MBOX_DCLR_REG 0x08 +#define MBOX_DSTAT_REG 0x0c +#define MBOX_MODE_REG 0x10 +#define MBOX_IMASK_REG 0x14 +#define MBOX_ICLR_REG 0x18 +#define MBOX_SEND_REG 0x1c +#define MBOX_DATA_REG 0x20 + +#define MBOX_IPC_LOCK_REG 0xa00 +#define MBOX_IPC_UNLOCK 0x1acce551 + +#define MBOX_AUTOMATIC_ACK 1 + +#define MBOX_STATE_IDLE BIT(4) +#define MBOX_STATE_ACK BIT(7) + +#define MBOX_MSG_LEN 8 + +/** + * Hi3660 mailbox channel information + * + * A channel can be used for TX or RX, it can trigger remote + * processor interrupt to notify remote processor and can receive + * interrupt if has incoming message. + * + * @dst_irq: Interrupt vector for remote processor + * @ack_irq: Interrupt vector for local processor + */ +struct hi3660_chan_info { + unsigned int dst_irq; + unsigned int ack_irq; +}; + +/** + * Hi3660 mailbox controller data + * + * Mailbox controller includes 32 channels and can allocate + * channel for message transferring. + * + * @dev: Device to which it is attached + * @base: Base address of the register mapping region + * @chan: Representation of channels in mailbox controller + * @mchan: Representation of channel info + * @controller: Representation of a communication channel controller + */ +struct hi3660_mbox { + struct device *dev; + void __iomem *base; + struct mbox_chan chan[MBOX_CHAN_MAX]; + struct hi3660_chan_info mchan[MBOX_CHAN_MAX]; + struct mbox_controller controller; +}; + +static struct hi3660_mbox *to_hi3660_mbox(struct mbox_controller *mbox) +{ + return container_of(mbox, struct hi3660_mbox, controller); +} + +static int hi3660_mbox_check_state(struct mbox_chan *chan) +{ + unsigned long ch = (unsigned long)chan->con_priv; + struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox); + struct hi3660_chan_info *mchan = &mbox->mchan[ch]; + void __iomem *base = MBOX_BASE(mbox, ch); + unsigned long val; + unsigned int state, ret; + + /* Mailbox is idle so directly bail out */ + state = readl_relaxed(base + MBOX_MODE_REG); + if (state & MBOX_STATE_IDLE) + return 0; + + /* Wait for acknowledge from remote */ + ret = readx_poll_timeout_atomic(readl_relaxed, base + MBOX_MODE_REG, + val, (val & MBOX_STATE_ACK), 1000, 300000); + if (ret) { + dev_err(mbox->dev, "%s: timeout for receiving ack\n", __func__); + return ret; + } + + /* Ensure channel is released */ + writel_relaxed(0xffffffff, base + MBOX_IMASK_REG); + writel_relaxed(BIT(mchan->ack_irq), base + MBOX_SRC_REG); + return 0; +} + +static int hi3660_mbox_unlock(struct mbox_chan *chan) +{ + struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox); + unsigned int val, retry = 3; + + do { + writel_relaxed(MBOX_IPC_UNLOCK, mbox->base + MBOX_IPC_LOCK_REG); + + val = readl_relaxed(mbox->base + MBOX_IPC_LOCK_REG); + if (!val) + break; + + udelay(10); + } while (retry--); + + if (val) + dev_err(mbox->dev, "%s: failed to unlock mailbox\n", __func__); + + return (!val) ? 0 : -ETIMEDOUT; +} + +static int hi3660_mbox_acquire_channel(struct mbox_chan *chan) +{ + unsigned long ch = (unsigned long)chan->con_priv; + struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox); + struct hi3660_chan_info *mchan = &mbox->mchan[ch]; + void __iomem *base = MBOX_BASE(mbox, ch); + unsigned int val, retry; + + for (retry = 10; retry; retry--) { + + /* Check if channel is in idle state */ + if (readl_relaxed(base + MBOX_MODE_REG) & MBOX_STATE_IDLE) { + + val = BIT(mchan->ack_irq); + writel_relaxed(val, base + MBOX_SRC_REG); + val = readl_relaxed(base + MBOX_SRC_REG); + + /* Check ack bit has been set successfully */ + if (val & BIT(mchan->ack_irq)) + break; + } + } + + if (!retry) + dev_err(mbox->dev, "%s: failed to acquire channel\n", __func__); + + return retry ? 0 : -ETIMEDOUT; +} + +static int hi3660_mbox_startup(struct mbox_chan *chan) +{ + int ret; + + ret = hi3660_mbox_check_state(chan); + if (ret) + return ret; + + ret = hi3660_mbox_unlock(chan); + if (ret) + return ret; + + ret = hi3660_mbox_acquire_channel(chan); + if (ret) + return ret; + + return 0; +} + +static int hi3660_mbox_send_data(struct mbox_chan *chan, void *msg) +{ + unsigned long ch = (unsigned long)chan->con_priv; + struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox); + struct hi3660_chan_info *mchan = &mbox->mchan[ch]; + void __iomem *base = MBOX_BASE(mbox, ch); + u32 *buf = msg; + unsigned int i; + + /* Ensure channel is released */ + writel_relaxed(0xffffffff, base + MBOX_IMASK_REG); + writel_relaxed(BIT(mchan->ack_irq), base + MBOX_SRC_REG); + + /* Clear mask for destination interrupt */ + writel_relaxed(~BIT(mchan->dst_irq), base + MBOX_IMASK_REG); + + /* Config destination for interrupt vector */ + writel_relaxed(BIT(mchan->dst_irq), base + MBOX_DST_REG); + + /* Automatic acknowledge mode */ + writel_relaxed(MBOX_AUTOMATIC_ACK, base + MBOX_MODE_REG); + + /* Fill message data */ + for (i = 0; i < MBOX_MSG_LEN; i++) + writel_relaxed(buf[i], base + MBOX_DATA_REG + i * 4); + + /* Trigger data transferring */ + writel_relaxed(BIT(mchan->ack_irq), base + MBOX_SEND_REG); + return 0; +} + +static struct mbox_chan_ops hi3660_mbox_ops = { + .startup = hi3660_mbox_startup, + .send_data = hi3660_mbox_send_data, +}; + +static struct mbox_chan *hi3660_mbox_xlate(struct mbox_controller *controller, + const struct of_phandle_args *spec) +{ + struct hi3660_mbox *mbox = to_hi3660_mbox(controller); + struct hi3660_chan_info *mchan; + unsigned int ch = spec->args[0]; + + if (ch >= MBOX_CHAN_MAX) { + dev_err(mbox->dev, "Invalid channel idx %d\n", ch); + return ERR_PTR(-EINVAL); + } + + mchan = &mbox->mchan[ch]; + mchan->dst_irq = spec->args[1]; + mchan->ack_irq = spec->args[2]; + + return &mbox->chan[ch]; +} + +static const struct of_device_id hi3660_mbox_of_match[] = { + { .compatible = "hisilicon,hi3660-mbox", }, + {}, +}; + +MODULE_DEVICE_TABLE(of, hi3660_mbox_of_match); + +static int hi3660_mbox_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct hi3660_mbox *mbox; + struct mbox_chan *chan; + struct resource *res; + unsigned long ch; + int err; + + mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); + if (!mbox) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mbox->base = devm_ioremap_resource(dev, res); + if (IS_ERR(mbox->base)) + return PTR_ERR(mbox->base); + + mbox->dev = dev; + mbox->controller.dev = dev; + mbox->controller.chans = mbox->chan; + mbox->controller.num_chans = MBOX_CHAN_MAX; + mbox->controller.ops = &hi3660_mbox_ops; + mbox->controller.of_xlate = hi3660_mbox_xlate; + + /* Initialize mailbox channel data */ + chan = mbox->chan; + for (ch = 0; ch < MBOX_CHAN_MAX; ch++) + chan[ch].con_priv = (void *)ch; + + err = mbox_controller_register(&mbox->controller); + if (err) { + dev_err(dev, "Failed to register mailbox %d\n", err); + return err; + } + + platform_set_drvdata(pdev, mbox); + dev_info(dev, "Mailbox enabled\n"); + return 0; +} + +static int hi3660_mbox_remove(struct platform_device *pdev) +{ + struct hi3660_mbox *mbox = platform_get_drvdata(pdev); + + mbox_controller_unregister(&mbox->controller); + return 0; +} + +static struct platform_driver hi3660_mbox_driver = { + .probe = hi3660_mbox_probe, + .remove = hi3660_mbox_remove, + .driver = { + .name = "hi3660-mbox", + .of_match_table = hi3660_mbox_of_match, + }, +}; + +static int __init hi3660_mbox_init(void) +{ + return platform_driver_register(&hi3660_mbox_driver); +} +core_initcall(hi3660_mbox_init); + +static void __exit hi3660_mbox_exit(void) +{ + platform_driver_unregister(&hi3660_mbox_driver); +} +module_exit(hi3660_mbox_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Hisilicon Hi3660 Mailbox Controller"); +MODULE_AUTHOR("Leo Yan "); From patchwork Wed Feb 14 03:49:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 128306 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp186270ljc; Tue, 13 Feb 2018 19:50:44 -0800 (PST) X-Google-Smtp-Source: AH8x224VIsHEf/NHfTkbh1Vhag/T20fj/6GHlwHFokm9gPfIX2XgpAcfiSR7cxNO0LAaFGTCc+fG X-Received: by 2002:a17:902:8bc5:: with SMTP id r5-v6mr3134428plo.213.1518580244209; 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Signed-off-by: Ruyi Wang Signed-off-by: Kaihua Zhong --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) -- 1.9.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 22570c3..1ef7b94 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -286,6 +286,14 @@ #reset-cells = <2>; }; + mailbox: mailbox@e896b000 { + compatible = "hisilicon,hi3660-mbox"; + reg = <0x0 0xe896b000 0x0 0x1000>; + interrupts = , + ; + #mbox-cells = <3>; + }; + stub_clock: stub_clock@e896b500 { compatible = "hisilicon,hi3660-stub-clk"; reg = <0x0 0xe896b500 0x0 0x0100>;