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[209.132.180.67]) by mx.google.com with ESMTP id z67si37492pfb.223.2018.02.14.07.51.55; Wed, 14 Feb 2018 07:51:56 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=K5+u/SgZ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1031830AbeBNPvw (ORCPT + 28 others); Wed, 14 Feb 2018 10:51:52 -0500 Received: from mail-wr0-f193.google.com ([209.85.128.193]:35476 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1031649AbeBNPvu (ORCPT ); Wed, 14 Feb 2018 10:51:50 -0500 Received: by mail-wr0-f193.google.com with SMTP id l43so428494wrc.2 for ; Wed, 14 Feb 2018 07:51:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/s3v19DQ4f5sPGj92UDuAjMT5jwdJ/Azi0AEYsiLKJU=; b=K5+u/SgZMXc5+q10Dvbep6lygoyN0VFQjI9CZgdOJLRfT/2w8Clggyrc0wbzdFVXpm osk4EOZtnKtN4MTm4lyKQYrAO2Q3JP1CPVh8HU7Ip5OkhaBJU5tMacg5u9Z0fbBd/AIR wqH2AkiBCa7rHU+l5FyA8h/OER0A7B4WsY1H8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/s3v19DQ4f5sPGj92UDuAjMT5jwdJ/Azi0AEYsiLKJU=; b=sUBVFBTDWeJHv+lX+NUiHP5fP4zPIBDxzYKSPHWeYlPQQLm4GI/ORQQ7lOqetW9wrQ NpowkkCEvS59Ez5pn1eLcFCvhotoUENx7M1vssqtqIEzGQo0bJ5V1z39wLQgeW/PtPhs tXWFdrzznSXvu7MFAD3vwSwYINkdCm1BjLIRNj3KG46DZXO3geFqJcepSp4sig5BITIK XN3Srx0S4x7oeDgeKbhkeed7sKGvjgo13elII1RyCb3FI2ArVh09s7H7cKvgzW3s6dhF 8w5JmtaS5mdMjLww+VLiYIc+k4ya/6jfi6Fg+hWOVSgqaPHyoDsKjwnwCamDbrN7WDJZ eSGQ== X-Gm-Message-State: APf1xPC6cL7Gj9zTQH4sn3jnH+divATzAMBz8zX31X6FV5U9Q+Ygoavh gIF20Hj5zlbwUMCemC4OYwc07g== X-Received: by 10.223.163.85 with SMTP id d21mr2586879wrb.105.1518623509362; Wed, 14 Feb 2018 07:51:49 -0800 (PST) Received: from localhost.localdomain ([154.145.114.50]) by smtp.gmail.com with ESMTPSA id i75sm9238638wmg.41.2018.02.14.07.51.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 Feb 2018 07:51:48 -0800 (PST) From: Ard Biesheuvel To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, will.deacon@arm.com, catalin.marinas@arm.com, broonie@linaro.org, marc.zyngier@arm.com, Ard Biesheuvel Subject: [PATCH] arm64: Move post_ttbr_update_workaround to C code Date: Wed, 14 Feb 2018 15:51:40 +0000 Message-Id: <20180214155140.27162-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180214154033.GA2745@kroah.com> References: <20180214154033.GA2745@kroah.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Marc Zyngier Commit 95e3de3590e3 upstream. We will soon need to invoke a CPU-specific function pointer after changing page tables, so move post_ttbr_update_workaround out into C code to make this possible. Signed-off-by: Marc Zyngier Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Ard Biesheuvel --- arch/arm64/include/asm/assembler.h | 13 ------------- arch/arm64/kernel/entry.S | 2 +- arch/arm64/mm/context.c | 9 +++++++++ arch/arm64/mm/proc.S | 3 +-- 4 files changed, 11 insertions(+), 16 deletions(-) -- 2.11.0 diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 6d951a82e656..463619dcadd4 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -481,19 +481,6 @@ alternative_endif mrs \rd, sp_el0 .endm -/* - * Errata workaround post TTBRx_EL1 update. - */ - .macro post_ttbr_update_workaround -#ifdef CONFIG_CAVIUM_ERRATUM_27456 -alternative_if ARM64_WORKAROUND_CAVIUM_27456 - ic iallu - dsb nsh - isb -alternative_else_nop_endif -#endif - .endm - /** * Errata workaround prior to disable MMU. Insert an ISB immediately prior * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0. diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index f786e8d3d5be..185c87a53fe3 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -275,7 +275,7 @@ alternative_else_nop_endif * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache * corruption). */ - post_ttbr_update_workaround + bl post_ttbr_update_workaround .endif 1: .if \el != 0 diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index db28958d9e4f..23498d032c82 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -235,6 +235,15 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) cpu_switch_mm(mm->pgd, mm); } +/* Errata workaround post TTBRx_EL1 update. */ +asmlinkage void post_ttbr_update_workaround(void) +{ + asm(ALTERNATIVE("nop; nop; nop", + "ic iallu; dsb nsh; isb", + ARM64_WORKAROUND_CAVIUM_27456, + CONFIG_CAVIUM_ERRATUM_27456)); +} + static int asids_init(void) { asid_bits = get_cpu_asid_bits(); diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index c25e58bc2910..27058f3fd132 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -148,8 +148,7 @@ ENTRY(cpu_do_switch_mm) isb msr ttbr0_el1, x0 // now update TTBR0 isb - post_ttbr_update_workaround - ret + b post_ttbr_update_workaround // Back to C code... ENDPROC(cpu_do_switch_mm) .pushsection ".idmap.text", "awx"