From patchwork Mon Jan 4 16:14:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 356400 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp15089782jai; Mon, 4 Jan 2021 08:10:44 -0800 (PST) X-Google-Smtp-Source: ABdhPJzzqm6R/FFJr/c3Dci5X8vwMRW1WQv9M5Ut0HltGoeXURn/4KSxsfU0SZndhOFwUBmQWuWo X-Received: by 2002:a50:eb97:: with SMTP id y23mr71589542edr.29.1609776644016; Mon, 04 Jan 2021 08:10:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609776644; cv=none; d=google.com; s=arc-20160816; b=DonvwuyPfrbz1RIMZaE/4FuS7vzixxm6BEyyHfpDlqBEiP4m13eBlaICnNX5tQKxbZ yXDwNRW//ZbfeIilW+mWn0BRvNo32i1dNKOBDjElspBwoy1MJmpGzLg6YVBSR0O5KPRo BioTXR/dV4gepZDLScEWMpFUFSdHcw+CUO64n8oQI/EBn09HZuYgysieuG81Jd+L0Tjb ZV0f9wAXQNOnZVcHarSeNJTzNN/bwSZwGNo9XKvPJCqOKpgbDtMyV7I12leG8h+vM2LT 2rdaeM8Joe0i1wJMe/2QSteaollrseeS0abg6Nf7kbxWr71NF1FWAjcNuEA065dJLqvk n2jA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=D3FY0m7LeloNo/GU5bzjUJdGWPyDuclaFRVWh7ls4wY=; b=WuOzf+SaAKbn6JGFw/TGUIgqJFuU/GUCDG52My5MvwDyZmBQaYhY/nHuDNEBK4YAze vr501fY3/H2cMTv+vdJqHug/cpxSOYsCwlxHdJxDKRk6uicxjD/mMMdnZf0CATki818+ m+evVPCsCgG/lY8VnMD4y7tuf4jSU6Q78tod6KBaRhNRRc1Gc06ucLf/2QnWGXtbQ6Dg ZV0KT8V03e/AriF+czJCjFm5pjsTbZUWuxIj3PMH/qJkpGWn2RqL29F+sd0ymOlKQ3AY uW7kC1JIHG8b/Cfcb2jPkgFoK31+34bWy3WHVEk8mHVw5d175lbXmvSBUv8NLtjt4hj6 qcTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="cqcV+gm/"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id 61si31780067edk.598.2021.01.04.08.10.43; Mon, 04 Jan 2021 08:10:44 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="cqcV+gm/"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728656AbhADQKM (ORCPT + 15 others); Mon, 4 Jan 2021 11:10:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729390AbhADQIK (ORCPT ); Mon, 4 Jan 2021 11:08:10 -0500 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D57C2C061794 for ; Mon, 4 Jan 2021 08:07:29 -0800 (PST) Received: by mail-wm1-x334.google.com with SMTP id a6so18931692wmc.2 for ; Mon, 04 Jan 2021 08:07:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=D3FY0m7LeloNo/GU5bzjUJdGWPyDuclaFRVWh7ls4wY=; b=cqcV+gm/7vkAygZEwdTzZm+Dz8EuQ2wy7vnF6lhjXYdbObIeqePcJ4DE1oWZdU7Tpt TiZrHmWq3hCOuD3heH4QfKnCFB+GuZ+vT6lhzA7YhbyeDqQU5vxAgr/2RUcvRbn4reeq VNTa2aW1IEG8Ma3jjW5phejZIvDBElkVqkVcVJbBl9X461molVlwz0ShRfiT2kcaywvD F2wTgjHrkVAcz4iec0f6MpQYB3j+yN//5CLeVfa2HLPvAsv39y8u6T8/X2IIt0BFJWGA Lo3eH13SM21MhvVK4o7L8+Ug97dm1axSsXehruzfu/RLijohVM3Q7bHKqeN2QP27FTy1 fnEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=D3FY0m7LeloNo/GU5bzjUJdGWPyDuclaFRVWh7ls4wY=; b=MIGK3ubTz6iYkOYZ3PBg8UKfZtYZqwx73LN5T0ycDvD8UTM/wqE/STHARl04jRbacE 6gjeXt95OaINruiBspgVlwaXj5j36FxsYHL4ego0VFRtMDUU1R+/qjhZhoyiIo689sq3 cLT7DxWFAKHn4Q6+LXTCKOds9qgYRYFDeDi+fznXwlHeuXY4SmK0PmFgOJBcGwVSB2vZ nUZwWtfWbX7UKO6OsWk8pxVXJ8bFXodbfnSfd7458mfB+TNoxL4AeqeLsFFBDnFALD9r mub+MPRCTWM1VnXuE/hp/dGlGOJI7wH+WkB44iAi7lRR9eqq44p4LbyZn7BZQ62p2ckG 8KMw== X-Gm-Message-State: AOAM531UKvGdLnoO81+Ppejj6HPiDN9LiHkWQrI/N/K2eFsei/XKEnbC dshbgwqg1iMEmw4LojYp5SC61Q== X-Received: by 2002:a7b:c842:: with SMTP id c2mr27377848wml.100.1609776448508; Mon, 04 Jan 2021 08:07:28 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:490:8730:41b:e085:fa9a:9c53]) by smtp.gmail.com with ESMTPSA id h9sm89278049wre.24.2021.01.04.08.07.27 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Jan 2021 08:07:28 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, bbhatt@codeaurora.org, hemantk@codeaurora.org, Loic Poulain Subject: [PATCH v8 01/10] bus: mhi: core: Add device hardware reset support Date: Mon, 4 Jan 2021 17:14:50 +0100 Message-Id: <1609776899-30664-2-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1609776899-30664-1-git-send-email-loic.poulain@linaro.org> References: <1609776899-30664-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The MHI specification allows to perform a hard reset of the device when writing to the SOC_RESET register. It can be used to completely restart the device (e.g. in case of unrecoverable MHI error). This is up to the MHI controller driver to determine when this hard reset should be used, and in case of MHI errors, should be used as a reset of last resort (after standard MHI stack reset). This function is a stateless function, the MHI layer do nothing except triggering the reset by writing into the right register(s), this is up to the caller to ensure right mhi_controller state (e.g. unregister the controller if necessary). Signed-off-by: Loic Poulain Reviewed-by: Manivannan Sadhasivam --- drivers/bus/mhi/core/main.c | 13 +++++++++++++ include/linux/mhi.h | 9 +++++++++ 2 files changed, 22 insertions(+) -- 2.7.4 diff --git a/drivers/bus/mhi/core/main.c b/drivers/bus/mhi/core/main.c index d34d7e9..9b42540 100644 --- a/drivers/bus/mhi/core/main.c +++ b/drivers/bus/mhi/core/main.c @@ -135,6 +135,19 @@ enum mhi_state mhi_get_mhi_state(struct mhi_controller *mhi_cntrl) } EXPORT_SYMBOL_GPL(mhi_get_mhi_state); +void mhi_soc_reset(struct mhi_controller *mhi_cntrl) +{ + if (mhi_cntrl->reset) { + mhi_cntrl->reset(mhi_cntrl); + return; + } + + /* Generic MHI SoC reset */ + mhi_write_reg(mhi_cntrl, mhi_cntrl->regs, MHI_SOC_RESET_REQ_OFFSET, + MHI_SOC_RESET_REQ); +} +EXPORT_SYMBOL_GPL(mhi_soc_reset); + int mhi_map_single_no_bb(struct mhi_controller *mhi_cntrl, struct mhi_buf_info *buf_info) { diff --git a/include/linux/mhi.h b/include/linux/mhi.h index 562862f..54afcae 100644 --- a/include/linux/mhi.h +++ b/include/linux/mhi.h @@ -347,6 +347,7 @@ struct mhi_controller_config { * @unmap_single: CB function to destroy TRE buffer * @read_reg: Read a MHI register via the physical link (required) * @write_reg: Write a MHI register via the physical link (required) + * @reset: Controller specific reset function (optional) * @buffer_len: Bounce buffer length * @index: Index of the MHI controller instance * @bounce_buf: Use of bounce buffer @@ -437,6 +438,7 @@ struct mhi_controller { u32 *out); void (*write_reg)(struct mhi_controller *mhi_cntrl, void __iomem *addr, u32 val); + void (*reset)(struct mhi_controller *mhi_cntrl); size_t buffer_len; int index; @@ -673,6 +675,13 @@ enum mhi_ee_type mhi_get_exec_env(struct mhi_controller *mhi_cntrl); enum mhi_state mhi_get_mhi_state(struct mhi_controller *mhi_cntrl); /** + * mhi_soc_reset - Trigger a device reset. This can be used as a last resort + * to reset and recover a device. + * @mhi_cntrl: MHI controller + */ +void mhi_soc_reset(struct mhi_controller *mhi_cntrl); + +/** * mhi_device_get - Disable device low power mode * @mhi_dev: Device associated with the channel */ From patchwork Mon Jan 4 16:14:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 356392 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp15088197jai; Mon, 4 Jan 2021 08:08:47 -0800 (PST) X-Google-Smtp-Source: ABdhPJxJ7nyda9QLSCq8Yg/RC3BWeArh+pnAY5IugpHZz9tiI9bd8MSxUTAAUbTCvsfLbwqPCqF/ X-Received: by 2002:a05:6402:1d24:: with SMTP id dh4mr70271334edb.161.1609776527548; Mon, 04 Jan 2021 08:08:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609776527; cv=none; d=google.com; s=arc-20160816; b=CJFVFFTVp/TCPegLqFBtq/RVAH51RMFONUUMgCoYyt4PRiBr/iCPA0g9UIgOEUWBew L7hx4MS21AAdUM7a/D+QAwgEKnhbf782pzQGu80P3e5F3qRkQNWLMvYXbXD7jb4ukRM6 /L2CAzzuKjNrQ0PUZmZFxGAWKfjtbhz55vXnvK+1Ext+nxFjTzPFoYYSZ7QO1OCLUGk5 NjpEYYqh4tWgyGRAwpYCBoyp/MWj1vl3P9noVpZXMV5/fP6vutIZK7fhV584wHrgWtnB /Ffkreq9VAI8J+33xgKGNAa6HGtO/RJbe2NOVSfRSACADd14CyyNQ2BonecIaMAKp3gO BJHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=WVEYav8eI3T4T9GoKINuGacLL3TQkLxasRSkMoJNjdY=; b=ule8G6HEcPvej/NgoC639VpIriH5mSoItOfknIX4sBu0G480LYM1GnkwkqlWB4FN8i R4aN1OHQzxy42/ZMfQnLiegHT0JIEYILIhus80bwoaLqBFDY9uSE/x3D07hRbnY6mExl q2e3UjXJ83UfetosNajnkmeN78sFRkKQMhafPX7d0EKGNUrl9PrQ2W6SNDEdMBP3XjUV Z5PUjLOWE3xpx21rLvSjAq2W4j6okfvq1sX16MNuv3BgZLRPLofSrSg8T14U4gP4BEO+ oNGb95DP4doNSaHEHTVFVUEmeGR8Y64OySg3n9vmhYawn+AqEI55aRB4EbDEFW6UirIh hr4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=D40SRcCS; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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That can be prevented by setting a larger number of events (i.e 2 x number of channel ring elements). Tested with FN980m module. Signed-off-by: Loic Poulain Reviewed-by: Manivannan Sadhasivam --- drivers/bus/mhi/pci_generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index f5bee76..d3896ef 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -91,7 +91,7 @@ struct mhi_pci_dev_info { #define MHI_EVENT_CONFIG_HW_DATA(ev_ring, ch_num) \ { \ - .num_elements = 128, \ + .num_elements = 256, \ .irq_moderation_ms = 5, \ .irq = (ev_ring) + 1, \ .priority = 1, \ From patchwork Mon Jan 4 16:14:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 356393 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp15088216jai; Mon, 4 Jan 2021 08:08:48 -0800 (PST) X-Google-Smtp-Source: ABdhPJz2tezHIZOk7gKq16mI/DnVTIQ5MpPZSDfE/Az3pdmzWY+7Gp8aNTVvMwanFYVsygIEZY6V X-Received: by 2002:a05:6402:1d24:: with SMTP id dh4mr70271401edb.161.1609776528544; Mon, 04 Jan 2021 08:08:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609776528; cv=none; d=google.com; s=arc-20160816; b=h2/zddLNDbm6z+sxmQroP1807mMeHUcxesiFq9srU0TGTGjDETtqnBxb1vPoVrXLPP r3byr+tqT1k1e1RBqfxZUd1ygonS5tJ80uSCVI9bJuDMTrqKJYWwRcfFyYg+ECkII6+c 3ihgl/NUqupAG+dBfL8A0GSWYtA72Axnp5zkS/RLLk54a2u+GOBMMi926kGdWL5ZtBgB S9Cip1yIBr0U6Nv9wjnzZxa4EKVAPF1ALvUANSm4Z1qlr1Rh1qn0oIMyBPDVpOjt+BuE uu0lshMfuNsc5HGfzn8o0V8tk80ERjj2zmXJhCFy2WDga+Gs2+GKJnEOn1p2pyaV04Sx jBNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=vyOYapeQzBqEAbAliweYgjMI0i+SwAaAghDPdGFwyJs=; b=YAgA8sdPrdgJWgAIs5GUVYCheuYJDVSBoXdMgLDLcpiCjObuu8hpQWrhwOaeSG5GAT EBjCOZeG4bRMjH0oKn+ZtNM+bevkGGKSNjU9GCzN+gfY1NMF6BZ8msdadfdC9dnd10ww Uic4wg8tQ/bQ5knzdDBQecXhJ6DSAx4/WislijQqK8Z+VaY62i0apC/JCq2681dj4SLI I9bZe6BdO26dGo5y01boKlu6cJyN/sAmvoKOiduwDQ0EVjfYc8ppKjRuR+OiGxdLZkW3 gbaVfYNUti1d31S/yYEzJ2plkvT573X/Qq6phCYjbo/hbJ3ywOF9TL0qAiFO9VOXZyW1 DifQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zBunDPFs; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e25si32468518edq.489.2021.01.04.08.08.48; Mon, 04 Jan 2021 08:08:48 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zBunDPFs; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729192AbhADQIS (ORCPT + 15 others); Mon, 4 Jan 2021 11:08:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729425AbhADQIM (ORCPT ); Mon, 4 Jan 2021 11:08:12 -0500 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 84D40C061795 for ; Mon, 4 Jan 2021 08:07:31 -0800 (PST) Received: by mail-wm1-x32d.google.com with SMTP id g185so19830447wmf.3 for ; Mon, 04 Jan 2021 08:07:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vyOYapeQzBqEAbAliweYgjMI0i+SwAaAghDPdGFwyJs=; b=zBunDPFs6m3V5Lt5E+gmrT4vVCnJkUzt3hNT2dJt1YDf/QD0vmma+wv1arwnkunCjV jYP9chYllrxoO/y5S2OiUOwe+4v54/2xFg4bmHsgAcNSmkFbPhuL8KEBAuT32Cz8dblF 8YxlHSKsTLjUwfVY4nyExHyQo5A1rkMapF71c88Y4SD4Pdgn7ko2yEFECPR2yxVuduqI 84JWKegQaNKjdgT8JXSXA3DHBM4wjItwTTAzDOr/5cVdlTHNDTOCPQKdy3PCvMWllCIv skViLxhBIEUJbRYdDnm+fFKG0mdqW6ZXnYpBO45/UCPPz0CBoX2wiz5XjJ50oaf0qBrY C9NA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vyOYapeQzBqEAbAliweYgjMI0i+SwAaAghDPdGFwyJs=; b=Y9snafQnAO6Aw0Xhvh9qDUlwYlUzElHwO6pL0R9D/rdhXHtvkWuQPCQoSwlidt3Xgp uljx68f32hNV4VvjES06TSs4DBYv9dYn4UcFrelxFq0hmisoTZYtbVBrMpW/fOfziiaZ YY+rIbUPYjIsXPFb/LUYOEk4cUuib+CoIzBBFUVbBZOWva9IfcW84wh40Z9+9R/nhOqh ocgA80nZJbdqQuWbU1TRAXopbIneTTmrCEQjeqLUOk8CjrtcqI1cNfAbMUOtPFVPMntI p7kVltzTjd4tok6id28GIqvIccRkmQ+QOCpipwEp6S0hbvaAWXIAltiw1lEBAtQNbsX6 3gLg== X-Gm-Message-State: AOAM533HdNr6l6WAwHW5EX3Tvb74d82fOBZBi8fIeThD5DhsUmLblP4E vTXwlopbe87DDurSWsr+kMYTIg== X-Received: by 2002:a1c:2e88:: with SMTP id u130mr27376224wmu.83.1609776450291; Mon, 04 Jan 2021 08:07:30 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:490:8730:41b:e085:fa9a:9c53]) by smtp.gmail.com with ESMTPSA id h9sm89278049wre.24.2021.01.04.08.07.29 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Jan 2021 08:07:29 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, bbhatt@codeaurora.org, hemantk@codeaurora.org, Loic Poulain Subject: [PATCH v8 03/10] mhi: pci_generic: Enable burst mode for hardware channels Date: Mon, 4 Jan 2021 17:14:52 +0100 Message-Id: <1609776899-30664-4-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1609776899-30664-1-git-send-email-loic.poulain@linaro.org> References: <1609776899-30664-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hardware channels have a feature called burst mode that allows to queue transfer ring element(s) (TRE) to a channel without ringing the device doorbell. In that mode, the device is polling the channel context for new elements. This reduces the frequency of host initiated doorbells and increase throughput. Create a new dedicated macro for hardware channels with burst enabled. Signed-off-by: Loic Poulain Reviewed-by: Manivannan Sadhasivam --- drivers/bus/mhi/pci_generic.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index d3896ef..778d13f 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -76,6 +76,36 @@ struct mhi_pci_dev_info { .offload_channel = false, \ } +#define MHI_CHANNEL_CONFIG_HW_UL(ch_num, ch_name, el_count, ev_ring) \ + { \ + .num = ch_num, \ + .name = ch_name, \ + .num_elements = el_count, \ + .event_ring = ev_ring, \ + .dir = DMA_TO_DEVICE, \ + .ee_mask = BIT(MHI_EE_AMSS), \ + .pollcfg = 0, \ + .doorbell = MHI_DB_BRST_ENABLE, \ + .lpm_notify = false, \ + .offload_channel = false, \ + .doorbell_mode_switch = true, \ + } \ + +#define MHI_CHANNEL_CONFIG_HW_DL(ch_num, ch_name, el_count, ev_ring) \ + { \ + .num = ch_num, \ + .name = ch_name, \ + .num_elements = el_count, \ + .event_ring = ev_ring, \ + .dir = DMA_FROM_DEVICE, \ + .ee_mask = BIT(MHI_EE_AMSS), \ + .pollcfg = 0, \ + .doorbell = MHI_DB_BRST_ENABLE, \ + .lpm_notify = false, \ + .offload_channel = false, \ + .doorbell_mode_switch = true, \ + } + #define MHI_EVENT_CONFIG_DATA(ev_ring) \ { \ .num_elements = 128, \ @@ -110,8 +140,8 @@ static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0), MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0), MHI_CHANNEL_CONFIG_DL(21, "IPCR", 8, 0), - MHI_CHANNEL_CONFIG_UL(100, "IP_HW0", 128, 1), - MHI_CHANNEL_CONFIG_DL(101, "IP_HW0", 128, 2), + MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 1), + MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 2), }; static const struct mhi_event_config modem_qcom_v1_mhi_events[] = { From patchwork Mon Jan 4 16:14:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 356404 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp15091416jai; Mon, 4 Jan 2021 08:12:44 -0800 (PST) X-Google-Smtp-Source: ABdhPJxtyRzFeVf+ZYRTVu+IdsllNugsCpdQ0tQQnZp5jyOSgCjFd38ddYX23LvDutj8CFVOgHzw X-Received: by 2002:a17:906:6606:: with SMTP id b6mr65653213ejp.151.1609776645903; Mon, 04 Jan 2021 08:10:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609776645; cv=none; d=google.com; s=arc-20160816; b=HfdH/QnmhyKmxMt9bL509Mh1zSLoFIhdEDBR1O56br37lZ2XLoboNXvDtIk29/qNI3 rngwqZbj248ot8KyteiyCnS+kw3DVzuEAeJDsTnAWVzApFJAEnMiREoq1n4uah4xxFSE RR6UHufDhVRkJjrJiiugmESTpRPsBX2QZs14cPHiTZabb4bMVDZ6H4C++JQJ4toAe6yE 5PaNiksxk17Y6p7UNzRK1Jhj9ZdjP/JXFK8lLtjZk50CTVqPIgW797RddV6gixfX8cvL PfScAcyeHHQzPgMwlPOry0BX/XYJlvurrTg3FVH7uaGRtL5IZNRZwwmu61kHu+F4/GEA n7pg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=FlAOxM9smlWMcv6DqjVn6eVaUh910lyWM2So7B2Pftk=; b=fGONHbdxDhmJI2NxmzLglvtHhtEH/Kromz12U1obwj0HrMjjI0R+RmjzmgYOmOjZsi CbPo7sH/VKftYk7WvcU1V7J+yaBGmQMMSA/TPuRg+ACdkIOhd2OZU6SlrD3+JtzEADKV QWQxMaPZ11qJm/8e0mOE2sW/EbX0AiVoXirbtQ0c1UBxeXErzhc+q5NITMTaDHTthZDF ttqcjcsamFks2WnDedlRrjpsPlzuBnX01giMNVLuJZm3tOrrd41H6xY5EEhYmzJZyBaa n1sRuQ0Ak7AyVAAVgToqVowi4Mm+qcLwFGOmRttQfIwge2FbtjIxnycAsyR5SXfPIXqP yzdQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VlNSf6lT; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Loic Poulain Reviewed-by: Manivannan Sadhasivam --- drivers/bus/mhi/pci_generic.c | 121 +++++++++++++++++++++++++++++++++++++----- 1 file changed, 108 insertions(+), 13 deletions(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 778d13f..f0dfa62 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -8,6 +8,7 @@ * Copyright (C) 2020 Linaro Ltd */ +#include #include #include #include @@ -15,6 +16,7 @@ #define MHI_PCI_DEFAULT_BAR_NUM 0 +#define MHI_POST_RESET_DELAY_MS 500 /** * struct mhi_pci_dev_info - MHI PCI device specific information * @config: MHI controller configuration @@ -177,6 +179,16 @@ static const struct pci_device_id mhi_pci_id_table[] = { }; MODULE_DEVICE_TABLE(pci, mhi_pci_id_table); +enum mhi_pci_device_status { + MHI_PCI_DEV_STARTED, +}; + +struct mhi_pci_device { + struct mhi_controller mhi_cntrl; + struct pci_saved_state *pci_state; + unsigned long status; +}; + static int mhi_pci_read_reg(struct mhi_controller *mhi_cntrl, void __iomem *addr, u32 *out) { @@ -196,6 +208,20 @@ static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl, /* Nothing to do for now */ } +static bool mhi_pci_is_alive(struct mhi_controller *mhi_cntrl) +{ + struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); + u16 vendor = 0; + + if (pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor)) + return false; + + if (vendor == (u16) ~0 || vendor == 0) + return false; + + return true; +} + static int mhi_pci_claim(struct mhi_controller *mhi_cntrl, unsigned int bar_num, u64 dma_mask) { @@ -291,16 +317,20 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data; const struct mhi_controller_config *mhi_cntrl_config; + struct mhi_pci_device *mhi_pdev; struct mhi_controller *mhi_cntrl; int err; dev_dbg(&pdev->dev, "MHI PCI device found: %s\n", info->name); - mhi_cntrl = mhi_alloc_controller(); - if (!mhi_cntrl) + /* mhi_pdev.mhi_cntrl must be zero-initialized */ + mhi_pdev = devm_kzalloc(&pdev->dev, sizeof(*mhi_pdev), GFP_KERNEL); + if (!mhi_pdev) return -ENOMEM; mhi_cntrl_config = info->config; + mhi_cntrl = &mhi_pdev->mhi_cntrl; + mhi_cntrl->cntrl_dev = &pdev->dev; mhi_cntrl->iova_start = 0; mhi_cntrl->iova_stop = (dma_addr_t)DMA_BIT_MASK(info->dma_data_width); @@ -315,17 +345,21 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width)); if (err) - goto err_release; + return err; err = mhi_pci_get_irqs(mhi_cntrl, mhi_cntrl_config); if (err) - goto err_release; + return err; + + pci_set_drvdata(pdev, mhi_pdev); - pci_set_drvdata(pdev, mhi_cntrl); + /* Have stored pci confspace at hand for restore in sudden PCI error */ + pci_save_state(pdev); + mhi_pdev->pci_state = pci_store_saved_state(pdev); err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config); if (err) - goto err_release; + return err; /* MHI bus does not power up the controller by default */ err = mhi_prepare_for_power_up(mhi_cntrl); @@ -340,33 +374,94 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) goto err_unprepare; } + set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); + return 0; err_unprepare: mhi_unprepare_after_power_down(mhi_cntrl); err_unregister: mhi_unregister_controller(mhi_cntrl); -err_release: - mhi_free_controller(mhi_cntrl); return err; } static void mhi_pci_remove(struct pci_dev *pdev) { - struct mhi_controller *mhi_cntrl = pci_get_drvdata(pdev); + struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { + mhi_power_down(mhi_cntrl, true); + mhi_unprepare_after_power_down(mhi_cntrl); + } - mhi_power_down(mhi_cntrl, true); - mhi_unprepare_after_power_down(mhi_cntrl); mhi_unregister_controller(mhi_cntrl); - mhi_free_controller(mhi_cntrl); } +static void mhi_pci_reset_prepare(struct pci_dev *pdev) +{ + struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + + dev_info(&pdev->dev, "reset\n"); + + /* Clean up MHI state */ + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { + mhi_power_down(mhi_cntrl, false); + mhi_unprepare_after_power_down(mhi_cntrl); + } + + /* cause internal device reset */ + mhi_soc_reset(mhi_cntrl); + + /* Be sure device reset has been executed */ + msleep(MHI_POST_RESET_DELAY_MS); +} + +static void mhi_pci_reset_done(struct pci_dev *pdev) +{ + struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + int err; + + /* Restore initial known working PCI state */ + pci_load_saved_state(pdev, mhi_pdev->pci_state); + pci_restore_state(pdev); + + /* Is device status available ? */ + if (!mhi_pci_is_alive(mhi_cntrl)) { + dev_err(&pdev->dev, "reset failed\n"); + return; + } + + err = mhi_prepare_for_power_up(mhi_cntrl); + if (err) { + dev_err(&pdev->dev, "failed to prepare MHI controller\n"); + return; + } + + err = mhi_sync_power_up(mhi_cntrl); + if (err) { + dev_err(&pdev->dev, "failed to power up MHI controller\n"); + mhi_unprepare_after_power_down(mhi_cntrl); + return; + } + + set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); +} + +static const struct pci_error_handlers mhi_pci_err_handler = { + .reset_prepare = mhi_pci_reset_prepare, + .reset_done = mhi_pci_reset_done, +}; + static struct pci_driver mhi_pci_driver = { .name = "mhi-pci-generic", .id_table = mhi_pci_id_table, .probe = mhi_pci_probe, - .remove = mhi_pci_remove + .remove = mhi_pci_remove, + .err_handler = &mhi_pci_err_handler, }; module_pci_driver(mhi_pci_driver); From patchwork Mon Jan 4 16:14:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 356402 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp15090878jai; Mon, 4 Jan 2021 08:12:11 -0800 (PST) X-Google-Smtp-Source: ABdhPJwnXotEoBYfUVQufH5Hdu7YpPzQGHxXz9FGjmssDTapsMrexepnoEzxjQR6N6Xmjto3PdrL X-Received: by 2002:a50:b742:: with SMTP id g60mr70768649ede.113.1609776628673; Mon, 04 Jan 2021 08:10:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609776628; cv=none; d=google.com; s=arc-20160816; b=ss3Kwy/eKgOqcVFGc8OtK3VedC+p0Zr+51AQ1VYgfppPUiFBdjN3wz/CypPM8YYJV+ zbyf7mTFbra7nvdsyrqBT0M9KtxWXKNHPxSegEGg3ZP+BNAnzBo2RZ24qOVyY+/2Gh7p ITnk8KUUfPiTuFj9lhaCEpCiCwMcDRYOp9uSGJ3QDk3b88/8QeioIvSsMDT6YDXEyvJJ Q1kIgvzOGqhqdJY2kAV8eJqZzPgH3XONCYnrdLZefq/55hQ0z8GXNpMqsH97OLGXEMdd OaVPg+3qhxK0QhRzbdUQQz/sI+1E58Tl0SpsFerCfZ1nDyeo8U2edvDhjXKruXVdTcDu uu6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=i+nXOsRRfuAtpnA3uXgsRZmPRSsd7wECnNCxfQNlAfM=; b=RkdXaYkb4H4pNElGDVOru/XPbitFtQlj1gyh4dyhxuejjWJgpxdL3F/ubrygyC+fPd b8pstM4gIANz5ndphlN55R2cxHZwfNxgIu2U7oo/03t6Fv2+G30uZmT6DizFEGhM8BQv /ttLRUHOpE2q7y8DQMEMSIpV6Q6PEKTFe7n4VDjS/qM7hhnleqb4dqZNNLAMLtj1SMDI jXKyzlSwLzeiUjzoFAypgdRsh2z/crDHK675f0QZ9i2o8vbEnYCpi2cuiFVALFS1o+Fx 0kSDVRhTsPctg9dO+ULTev2/fFJFubPEz8kobydzw6ZhH2VTu6uoVRN0YATxcb5aWk0G etew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sqGu3Jeg; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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During suspend, MHI device controller must be put in M3 state and PCI bus in D3 state. Add a recovery procedure allowing to reinitialize the device in case of error during resume steps, which can happen if device loses power (and so its context) while system suspend. Signed-off-by: Loic Poulain Reviewed-by Hemant Kumar Reviewed-by: Manivannan Sadhasivam --- drivers/bus/mhi/pci_generic.c | 105 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index f0dfa62..2552c2e 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -13,6 +13,7 @@ #include #include #include +#include #define MHI_PCI_DEFAULT_BAR_NUM 0 @@ -186,6 +187,7 @@ enum mhi_pci_device_status { struct mhi_pci_device { struct mhi_controller mhi_cntrl; struct pci_saved_state *pci_state; + struct work_struct recovery_work; unsigned long status; }; @@ -313,6 +315,50 @@ static void mhi_pci_runtime_put(struct mhi_controller *mhi_cntrl) /* no PM for now */ } +static void mhi_pci_recovery_work(struct work_struct *work) +{ + struct mhi_pci_device *mhi_pdev = container_of(work, struct mhi_pci_device, + recovery_work); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); + int err; + + dev_warn(&pdev->dev, "device recovery started\n"); + + /* Clean up MHI state */ + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { + mhi_power_down(mhi_cntrl, false); + mhi_unprepare_after_power_down(mhi_cntrl); + } + + /* Check if we can recover without full reset */ + pci_set_power_state(pdev, PCI_D0); + pci_load_saved_state(pdev, mhi_pdev->pci_state); + pci_restore_state(pdev); + + if (!mhi_pci_is_alive(mhi_cntrl)) + goto err_try_reset; + + err = mhi_prepare_for_power_up(mhi_cntrl); + if (err) + goto err_try_reset; + + err = mhi_sync_power_up(mhi_cntrl); + if (err) + goto err_unprepare; + + dev_dbg(&pdev->dev, "Recovery completed\n"); + + set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); + return; + +err_unprepare: + mhi_unprepare_after_power_down(mhi_cntrl); +err_try_reset: + if (pci_reset_function(pdev)) + dev_err(&pdev->dev, "Recovery failed\n"); +} + static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data; @@ -328,6 +374,8 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (!mhi_pdev) return -ENOMEM; + INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work); + mhi_cntrl_config = info->config; mhi_cntrl = &mhi_pdev->mhi_cntrl; @@ -391,6 +439,8 @@ static void mhi_pci_remove(struct pci_dev *pdev) struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + cancel_work_sync(&mhi_pdev->recovery_work); + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { mhi_power_down(mhi_cntrl, true); mhi_unprepare_after_power_down(mhi_cntrl); @@ -456,12 +506,67 @@ static const struct pci_error_handlers mhi_pci_err_handler = { .reset_done = mhi_pci_reset_done, }; +static int __maybe_unused mhi_pci_suspend(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + + cancel_work_sync(&mhi_pdev->recovery_work); + + /* Transition to M3 state */ + mhi_pm_suspend(mhi_cntrl); + + pci_save_state(pdev); + pci_disable_device(pdev); + pci_wake_from_d3(pdev, true); + pci_set_power_state(pdev, PCI_D3hot); + + return 0; +} + +static int __maybe_unused mhi_pci_resume(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + int err; + + pci_set_power_state(pdev, PCI_D0); + pci_restore_state(pdev); + pci_set_master(pdev); + + err = pci_enable_device(pdev); + if (err) + goto err_recovery; + + /* Exit M3, transition to M0 state */ + err = mhi_pm_resume(mhi_cntrl); + if (err) { + dev_err(&pdev->dev, "failed to resume device: %d\n", err); + goto err_recovery; + } + + return 0; + +err_recovery: + /* The device may have loose power or crashed, try recovering it */ + queue_work(system_long_wq, &mhi_pdev->recovery_work); + + return err; +} + +static const struct dev_pm_ops mhi_pci_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(mhi_pci_suspend, mhi_pci_resume) +}; + static struct pci_driver mhi_pci_driver = { .name = "mhi-pci-generic", .id_table = mhi_pci_id_table, .probe = mhi_pci_probe, .remove = mhi_pci_remove, .err_handler = &mhi_pci_err_handler, + .driver.pm = &mhi_pci_pm_ops }; module_pci_driver(mhi_pci_driver); From patchwork Mon Jan 4 16:14:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 356398 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp15089549jai; Mon, 4 Jan 2021 08:10:29 -0800 (PST) X-Google-Smtp-Source: ABdhPJy592/pdH8szj5IjD5hIhyk1pYVwF8ykXpmGTVKYroBKl3iTQnXSWcE0xzgTNF51uU9DOr7 X-Received: by 2002:a05:6402:1ac4:: with SMTP id ba4mr17452516edb.383.1609776629569; Mon, 04 Jan 2021 08:10:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609776629; cv=none; d=google.com; s=arc-20160816; b=Dx/u9uCTEG0uieWGE8V+jx81MnRvfjOMs22PtfryuirSfBT/LdAvlXFQH2UdlKlxcd RWUaOo6KfaS8LxGgWR/XAHbMF6LeQFur7p7AibXkv1yRwN5xHSDacjaiAdiiBtUfF0wX bVX2AI50atKz10dgjKe4vfy4T8H/+9xZxN1MJqA/AxYk0IWC8DOlzLz2YNryn2Bb+nnH nd48wJFwZH5rbfAkd3Vn5uBoq9VXvTwpALqy/4WD9+6kCPWMH+kWmlXuogwqXMDTTR6x BFoyqiEaVv6KkajKNkgVt6jn/j0teK1yl2fYuhh+vkE69e3oKyAKSTIU4en2T7X5+GHp T5kg== ARC-Message-Signature: i=1; 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This patch enables error reporting and implements error_detected, slot_reset and resume callbacks. Signed-off-by: Loic Poulain Reviewed-by Hemant Kumar Reviewed-by: Manivannan Sadhasivam --- drivers/bus/mhi/pci_generic.c | 50 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 2552c2e..2cc4410 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -8,6 +8,7 @@ * Copyright (C) 2020 Linaro Ltd */ +#include #include #include #include @@ -405,6 +406,8 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) pci_save_state(pdev); mhi_pdev->pci_state = pci_store_saved_state(pdev); + pci_enable_pcie_error_reporting(pdev); + err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config); if (err) return err; @@ -501,7 +504,54 @@ static void mhi_pci_reset_done(struct pci_dev *pdev) set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); } +static pci_ers_result_t mhi_pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t state) +{ + struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + + dev_err(&pdev->dev, "PCI error detected, state = %u\n", state); + + if (state == pci_channel_io_perm_failure) + return PCI_ERS_RESULT_DISCONNECT; + + /* Clean up MHI state */ + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { + mhi_power_down(mhi_cntrl, false); + mhi_unprepare_after_power_down(mhi_cntrl); + } else { + /* Nothing to do */ + return PCI_ERS_RESULT_RECOVERED; + } + + pci_disable_device(pdev); + + return PCI_ERS_RESULT_NEED_RESET; +} + +static pci_ers_result_t mhi_pci_slot_reset(struct pci_dev *pdev) +{ + if (pci_enable_device(pdev)) { + dev_err(&pdev->dev, "Cannot re-enable PCI device after reset.\n"); + return PCI_ERS_RESULT_DISCONNECT; + } + + return PCI_ERS_RESULT_RECOVERED; +} + +static void mhi_pci_io_resume(struct pci_dev *pdev) +{ + struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); + + dev_err(&pdev->dev, "PCI slot reset done\n"); + + queue_work(system_long_wq, &mhi_pdev->recovery_work); +} + static const struct pci_error_handlers mhi_pci_err_handler = { + .error_detected = mhi_pci_error_detected, + .slot_reset = mhi_pci_slot_reset, + .resume = mhi_pci_io_resume, .reset_prepare = mhi_pci_reset_prepare, .reset_done = mhi_pci_reset_done, }; From patchwork Mon Jan 4 16:14:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 356396 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp15089520jai; Mon, 4 Jan 2021 08:10:28 -0800 (PST) X-Google-Smtp-Source: ABdhPJxfg6e7QtONYtrhrOGhVM+d0uwUhpShqJFdsXkThHbbSAePUysgFS2R6V4HiVBcDDOhvMPc X-Received: by 2002:a17:906:234d:: with SMTP id m13mr27742022eja.270.1609776628135; Mon, 04 Jan 2021 08:10:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609776628; cv=none; d=google.com; s=arc-20160816; b=AqXi8u5F/V3PDrQ64QKZSZCFURBkEBFkJZZImZWFjlkzVF2qkk3QOUum3d+HxG4OaU kJDw37Ld0u9dZuRP2pKHPuTmGmty8MO9cl9u2gHT3u1VD0pF3RBc0/QkdlvBvZS9/H0s r/ZhcT0nq415Omu/WIUd3y/CoK10TdcVTzLb8OIMoXySfv1n+EV7m4bVsg2qpkhs3POh eX8j0mWUSw07o4B6I+Cyvne8tmhnEJZMP2RGQCPvo5X77Yrq6GGcdPcMmYEneBP77eH9 gY4swMafqRvCmDH4UkoSdohDyytlLlhN2nJdiVUPbuYVUN+2OiYDtDfRr+aAdzhls1Ct HRRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=kjPhna6u1Nba3XrHjeQUkH1Nd8d+FuS1Z+vXfvMqIC4=; b=sPxk/ZlkgcoPeG8sltvR7A97Y4vogJCkvHUwo6RmKJjrkcU0dQI69KSKKctU2+Iti0 caAhsgkdDx56WxjnWlbgLfHdrlDitOBJoPYOqW/vCVdM/JMPQUSmV8hAjFiyFcJza40N 5/SikQOWMwaAxn+aS5Jxr1Rl28rF2I5y6hvZu2NYklHOpwNCAouHp/kCNmeaShOwfYJZ 22yu8Ahs8tAuhXOp+2jov6O5m5+2ZSQVAc9ZUfUd09ulAOtTNCYO7SjWSdV0WvEsfxsT 9jUb5wNL5OFG6WgQ9cD4sWfJE3D66yTYD5uUhhKLqz9l6vAk15v2OGhj0nmBxqPqsw7t bokA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VuKZWYku; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This patch implements a health-check mechanism to check regularly that device is alive (MHI layer can communicate with). If device is not alive (because a crash or unexpected reset), the recovery procedure is triggered. Tested successfully with Telit FN980m module. Signed-off-by: Loic Poulain Reviewed-by: Manivannan Sadhasivam Reviewed-by: Hemant Kumar --- drivers/bus/mhi/pci_generic.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 2cc4410..3eac410 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -14,11 +14,15 @@ #include #include #include +#include #include #define MHI_PCI_DEFAULT_BAR_NUM 0 #define MHI_POST_RESET_DELAY_MS 500 + +#define HEALTH_CHECK_PERIOD (HZ * 2) + /** * struct mhi_pci_dev_info - MHI PCI device specific information * @config: MHI controller configuration @@ -189,6 +193,7 @@ struct mhi_pci_device { struct mhi_controller mhi_cntrl; struct pci_saved_state *pci_state; struct work_struct recovery_work; + struct timer_list health_check_timer; unsigned long status; }; @@ -326,6 +331,8 @@ static void mhi_pci_recovery_work(struct work_struct *work) dev_warn(&pdev->dev, "device recovery started\n"); + del_timer(&mhi_pdev->health_check_timer); + /* Clean up MHI state */ if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { mhi_power_down(mhi_cntrl, false); @@ -351,6 +358,7 @@ static void mhi_pci_recovery_work(struct work_struct *work) dev_dbg(&pdev->dev, "Recovery completed\n"); set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); + mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); return; err_unprepare: @@ -360,6 +368,21 @@ static void mhi_pci_recovery_work(struct work_struct *work) dev_err(&pdev->dev, "Recovery failed\n"); } +static void health_check(struct timer_list *t) +{ + struct mhi_pci_device *mhi_pdev = from_timer(mhi_pdev, t, health_check_timer); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + + if (!mhi_pci_is_alive(mhi_cntrl)) { + dev_err(mhi_cntrl->cntrl_dev, "Device died\n"); + queue_work(system_long_wq, &mhi_pdev->recovery_work); + return; + } + + /* reschedule in two seconds */ + mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); +} + static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data; @@ -376,6 +399,7 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) return -ENOMEM; INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work); + timer_setup(&mhi_pdev->health_check_timer, health_check, 0); mhi_cntrl_config = info->config; mhi_cntrl = &mhi_pdev->mhi_cntrl; @@ -427,6 +451,9 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); + /* start health check */ + mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); + return 0; err_unprepare: @@ -442,6 +469,7 @@ static void mhi_pci_remove(struct pci_dev *pdev) struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + del_timer(&mhi_pdev->health_check_timer); cancel_work_sync(&mhi_pdev->recovery_work); if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { @@ -459,6 +487,8 @@ static void mhi_pci_reset_prepare(struct pci_dev *pdev) dev_info(&pdev->dev, "reset\n"); + del_timer(&mhi_pdev->health_check_timer); + /* Clean up MHI state */ if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { mhi_power_down(mhi_cntrl, false); @@ -502,6 +532,7 @@ static void mhi_pci_reset_done(struct pci_dev *pdev) } set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); + mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); } static pci_ers_result_t mhi_pci_error_detected(struct pci_dev *pdev, @@ -562,6 +593,7 @@ static int __maybe_unused mhi_pci_suspend(struct device *dev) struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + del_timer(&mhi_pdev->health_check_timer); cancel_work_sync(&mhi_pdev->recovery_work); /* Transition to M3 state */ @@ -597,6 +629,9 @@ static int __maybe_unused mhi_pci_resume(struct device *dev) goto err_recovery; } + /* Resume health check */ + mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); + return 0; err_recovery: From patchwork Mon Jan 4 16:14:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 356397 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp15089545jai; Mon, 4 Jan 2021 08:10:29 -0800 (PST) X-Google-Smtp-Source: ABdhPJx1DegnFiwYloEu/3G1HpD72TYw6Icc26wdzaWunnMJs9aClrcC8krbA3jcDz9o9gD5Umnu X-Received: by 2002:a17:906:4809:: with SMTP id w9mr66847023ejq.139.1609776629147; Mon, 04 Jan 2021 08:10:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609776629; cv=none; d=google.com; s=arc-20160816; b=krzOMVvVsJauaB8rqXr0K6mu02FMbWFXexU37buhzY4i2axK4mHIs1XlKvNTZrW1I/ aMxrn2r8oFZkb8E1n49VCURDvIqR2m/3w4IQYC1phhTFWFhnEtuTcz4oEPJFso1WJV7p X/tADAiRmUtTLkNCHihbG3CQaibrc+qHYyk5dKZKOD3KoVK4DygtoRPSTi1E1hSseHjX Vz3H5ngLpNembJoNAk0JOQomxk9Dv3Jx7owm0qbN3rdrfK/jaYDaxgaavF0Zx7HyAFGN ZN3w/hSsDgUIYbYAoCqJN2uUwuBj2ApipIKKmgLKronlTO+lZ65IAf9H99LrYYMxMlV6 LtQQ== ARC-Message-Signature: i=1; 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Increase the timeout to prevent MHI power-up issues. Signed-off-by: Loic Poulain Reviewed-by: Hemant Kumar Reviewed-by: Manivannan Sadhasivam --- drivers/bus/mhi/pci_generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 3eac410..cbf28c3 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -162,7 +162,7 @@ static const struct mhi_event_config modem_qcom_v1_mhi_events[] = { static const struct mhi_controller_config modem_qcom_v1_mhiv_config = { .max_channels = 128, - .timeout_ms = 5000, + .timeout_ms = 8000, .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels), .ch_cfg = modem_qcom_v1_mhi_channels, .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events), From patchwork Mon Jan 4 16:14:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 356394 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp15089489jai; Mon, 4 Jan 2021 08:10:26 -0800 (PST) X-Google-Smtp-Source: ABdhPJyGzJz9AUJarN+cYH94+4svuHZRaWq4WmaMAGQ+cy1t3ntVIm272cDHFW6uptC1UBSifSrC X-Received: by 2002:aa7:df0f:: with SMTP id c15mr72592909edy.354.1609776625989; Mon, 04 Jan 2021 08:10:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609776625; cv=none; d=google.com; s=arc-20160816; b=SFR/vY8fbkATW9v499tTkOx0ytVwPQo0fiMHqnZK7suvpniLEWmdFV8Gbia4GPKooK 8Y8RfnLpuOSTsr4TlCZvfVTB4BibKAtAPP3RpoPsYQ2UGk945eKVnYu3MICA6ocLliKE OqlT0CPlvGyMfif3ckLmmmLckWb3LjPGVysAooO04CzP/oFx6hcwza3fQlQfVo8nB3CH NAreLj0MbS5J55D2ca/tUQPFbB8bRRYntr6yxzau4LRlYjwHUidlJthDauZflkzA+Vqy NGXku6BRz3BTxd5Tq6xAtLDYzTHljw+QdCAt2HlS6uA2A9WhY4XAtbsg5NcenGZv0bQP +Txw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=U8FF5tjOadW4QdWdsG3P63qW/Qu0k2UYQBrwR3cTaGs=; b=VvijVRQhpYGD4QfyS1LOymN6/EJLzBTkibCcgFC+AQ7wrcXVw/QGAwa+rz0Ayw4u+8 2KCNLLnmabu5gt55XB0tpadloHW0xU4qz5dMDRg4r1EvAymHR2nKqfvBzZC/B25zkful lM72rNfHULO4FiVbIItC+sYX6FZzcNqv8zYlKmQ0qj4QrdHOTv7LbRUQELrZVW65y7RO m/x67aZWrE3Gqd5T55Q5xglAu/0KsibzVzRufzIn2hdlX5227PXVA0Hpv6gJjvmR3Ly9 HRUHYyTj3b6iN5ZplnKyjGeag3IYnDMOz0GIF0DK0VAeY8rO071nEcSDuWKaj2raapPD QpmA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zZaToSCQ; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Qualcomm Diag is the qualcomm diagnostics interface that can be used to collect modem logs, events, traces, etc. It can be used by tools such QPST or QXDM. This patch adds the DIAG channels and a dedicated event ring. Signed-off-by: Loic Poulain Reviewed-by Hemant Kumar Reviewed-by: Manivannan Sadhasivam --- drivers/bus/mhi/pci_generic.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index cbf28c3..5104084 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -142,22 +142,26 @@ struct mhi_pci_dev_info { } static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { + MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1), + MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1), MHI_CHANNEL_CONFIG_UL(12, "MBIM", 4, 0), MHI_CHANNEL_CONFIG_DL(13, "MBIM", 4, 0), MHI_CHANNEL_CONFIG_UL(14, "QMI", 4, 0), MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0), MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0), MHI_CHANNEL_CONFIG_DL(21, "IPCR", 8, 0), - MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 1), - MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 2), + MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 2), + MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 3), }; static const struct mhi_event_config modem_qcom_v1_mhi_events[] = { /* first ring is control+data ring */ MHI_EVENT_CONFIG_CTRL(0), + /* DIAG dedicated event ring */ + MHI_EVENT_CONFIG_DATA(1), /* Hardware channels request dedicated hardware event rings */ - MHI_EVENT_CONFIG_HW_DATA(1, 100), - MHI_EVENT_CONFIG_HW_DATA(2, 101) + MHI_EVENT_CONFIG_HW_DATA(2, 100), + MHI_EVENT_CONFIG_HW_DATA(3, 101) }; static const struct mhi_controller_config modem_qcom_v1_mhiv_config = { From patchwork Mon Jan 4 16:14:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 356395 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp15089498jai; Mon, 4 Jan 2021 08:10:26 -0800 (PST) X-Google-Smtp-Source: ABdhPJzjdnaqF2tvFzgB6x1ByEFUgsqr+zHq6AAnAdzNTPK65hjaTrc+ogWR3LJkp4ToCyzNq5bm X-Received: by 2002:a17:906:60c3:: with SMTP id f3mr66630737ejk.65.1609776626450; Mon, 04 Jan 2021 08:10:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609776626; cv=none; d=google.com; s=arc-20160816; b=xnsbUilbjTT9AXRoAjvw3vZE7v23gVE3lqbzbPOJbnjw1NDgJp34U+umlzMO0eigZP z8AhTQBzKYLZ3WaQPh4+VJvFGDU+B2Vw1CgI1T4api3Ilqkmk3c08QPDz14P5bglN94f eqXUbiHn9qHvSNXEpysCyPKFNVA4GBS2lb1+zjG7cXJPaEDcXuJJ6Q9omBYHZ8PDjz3q Ooexcqp5joFs66d9Te44QdetvUYcJnw9oozCI3NwS8jpafSPq9aBlS9i6fFcOX0r2nC6 uCm8XAkZ/WBtLwN22FR4gIqpZkYTzI4u2gwTRMxurSlfKUQE81/6QmFNjHrxcpRCneuu chJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=078yqWa4fm6+2z9avg2zxC4IELqOvwOqSWVwgOyL6OI=; b=K3VdwIvmey3WCSlX7zwMPPArZ9rGOQG+PBji8HnwP9SRHAqNSIyQ9a/RyqbvuqIotO q6vckTefKE3UlCa5IEVg9dbBmBLXGbTJ/YPhOthxlracSV35RDI06yj1v64T24ycnkdi 9ckh/9OXOehGFd6GzQmzLksQKoN838wLTD5pSQu5p+i8O4h7+l35OPw4CTLkOroNfksn mXPPlG8gd0bMXS2PYBMIsw5Lenn5CIySYfoEMyKYNX+95m4RuIQn/wVMFfqx4VDeyP9G Ic5aFsw6OT6VYZfzwuKa07A0U93W9aIai5D80cUjdZmgqIufzPzT6ZKnqSuf5dfzHyp1 Q7ow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CDEOR81M; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This path needs to be optimized for low latency and high throughput. After several tests on FN980m SDX55 based modem, it seems 1ms is a good default irq_moderation value: - It allows to reach the maximum download throughput - It introduces limited latency (5ms is too high) - It prevents interrupt flooding Signed-off-by: Loic Poulain Reviewed-by: Manivannan Sadhasivam --- drivers/bus/mhi/pci_generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 5104084..c13de0f 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -130,7 +130,7 @@ struct mhi_pci_dev_info { #define MHI_EVENT_CONFIG_HW_DATA(ev_ring, ch_num) \ { \ .num_elements = 256, \ - .irq_moderation_ms = 5, \ + .irq_moderation_ms = 1, \ .irq = (ev_ring) + 1, \ .priority = 1, \ .mode = MHI_DB_BRST_DISABLE, \