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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.14.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:14:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 01/47] linux-user: Conditionalize TUNSETVNETLE Date: Thu, 7 Jan 2021 10:14:02 -1000 Message-Id: <20210107201448.1152301-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This fixes the build for older ppc64 kernel headers. Fixes: 6addf06a3c4 Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/ioctls.h | 2 ++ 1 file changed, 2 insertions(+) -- 2.25.1 diff --git a/linux-user/ioctls.h b/linux-user/ioctls.h index 661b5daa9f..7193c3b226 100644 --- a/linux-user/ioctls.h +++ b/linux-user/ioctls.h @@ -748,8 +748,10 @@ IOCTL(TUNSETQUEUE, IOC_W, MK_PTR(MK_STRUCT(STRUCT_short_ifreq))) IOCTL(TUNSETIFINDEX , IOC_W, MK_PTR(TYPE_INT)) /* TUNGETFILTER is not supported: see TUNATTACHFILTER. */ +#ifdef TUNSETVNETLE IOCTL(TUNSETVNETLE, IOC_W, MK_PTR(TYPE_INT)) IOCTL(TUNGETVNETLE, IOC_R, MK_PTR(TYPE_INT)) +#endif #ifdef TUNSETVNETBE IOCTL(TUNSETVNETBE, IOC_W, MK_PTR(TYPE_INT)) IOCTL(TUNGETVNETBE, IOC_R, MK_PTR(TYPE_INT)) From patchwork Thu Jan 7 20:14:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358248 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp777113jai; Thu, 7 Jan 2021 12:15:34 -0800 (PST) X-Google-Smtp-Source: ABdhPJyMDfRK+7nhaFeBQfNifTDzMF3DyQRDZpvX1i3fecY5FX/zYq7pcaWApZ906WPh4wNGZynK X-Received: by 2002:a25:d10f:: with SMTP id i15mr853789ybg.244.1610050534562; Thu, 07 Jan 2021 12:15:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610050534; cv=none; d=google.com; s=arc-20160816; b=nec+gEKBDlYBMhnQxkaDGjrhgCVwlgYBfojFKpqwpBY634OK2bN4kbPrQj93OWNTT2 Oo8WmoWVav3EWoy/eezXuIr2jZ78QlDwlCPobV9Ig9rm1+jZTQqaAdbBkrqb9p2HyGxa 1YHIppMIRBeEUHiw+aayezxHAtjASS1acEk5YnDDI4dEH58YzeXvPylzGj2K63NLqopm qnxlqyUwdEF3MUHdzG0HKGw+Iv2SARVTkmiR3xfzhMU9MOI6pH9+k1n9+imwOsUYYkcT sRhqooZr1EtTrVVb4bTMavT4MVN4Hogj0NKTqxSkxHgGBT5yC4CIGGq+shubOw1Zbmko hUvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Bf5p3FouUPwrNDxVcRENcW6lpJP3fGRWqNfTxuoxyGQ=; b=fGlAXSOUuyIjPcmDGOEA/V8Fol9TsY6CZmhm1aPNtKgn28EkJrLbuELM95c5i64pHa 4PP4vFonN3IXk6ODUkOu809SPr+5Q/FPLNF4BdPeONuGeKDnjY/mM1ScJD3M+RXsey7W WWzU9u9pdzMqwY1p/YXXfp0bvluGZ0H71Rk+zFYq+oVvf7bNnAGVwV5MGEar47Z0uYog HS43s25qFA3u95b9LPyyp2+vNBj0Kyn8xRRXlTpgPRDXBbacUIfCCtV1vwq1idei955Y UtZ/v+SbTk9bcwv8KUhNQlUULPEMDcPTAJ0NlZC8wYpJ3aFm4PDHoUiBKrrjhf4puXHE pK9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hq9xyY73; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.14.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:14:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 02/47] tcg/i386: Adjust TCG_TARGET_HAS_MEMORY_BSWAP Date: Thu, 7 Jan 2021 10:14:03 -1000 Message-Id: <20210107201448.1152301-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Always true when movbe is available, otherwise leave this to generic code. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 3 +- tcg/i386/tcg-target.c.inc | 119 ++++++++++++++------------------------ 2 files changed, 47 insertions(+), 75 deletions(-) -- 2.25.1 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index cd067e0b30..b1ada9777a 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -101,6 +101,7 @@ extern bool have_bmi1; extern bool have_popcnt; extern bool have_avx1; extern bool have_avx2; +extern bool have_movbe; /* optional instructions */ #define TCG_TARGET_HAS_div2_i32 1 @@ -225,7 +226,7 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) -#define TCG_TARGET_HAS_MEMORY_BSWAP 1 +#define TCG_TARGET_HAS_MEMORY_BSWAP have_movbe #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index d8797ed398..01588cdcb4 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -154,13 +154,12 @@ bool have_bmi1; bool have_popcnt; bool have_avx1; bool have_avx2; +bool have_movbe; #ifdef CONFIG_CPUID_H -static bool have_movbe; static bool have_bmi2; static bool have_lzcnt; #else -# define have_movbe 0 # define have_bmi2 0 # define have_lzcnt 0 #endif @@ -1986,13 +1985,14 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, TCGReg base, int index, intptr_t ofs, int seg, bool is64, MemOp memop) { - const MemOp real_bswap = memop & MO_BSWAP; - MemOp bswap = real_bswap; + bool use_movbe = false; int rexw = is64 * P_REXW; int movop = OPC_MOVL_GvEv; - if (have_movbe && real_bswap) { - bswap = 0; + /* Do big-endian loads with movbe. */ + if (memop & MO_BSWAP) { + tcg_debug_assert(have_movbe); + use_movbe = true; movop = OPC_MOVBE_GyMy; } @@ -2006,23 +2006,28 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, base, index, 0, ofs); break; case MO_UW: - tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo, - base, index, 0, ofs); - if (real_bswap) { - tcg_out_rolw_8(s, datalo); - } - break; - case MO_SW: - if (real_bswap) { - if (have_movbe) { + if (use_movbe) { + /* There is no extending movbe; only low 16-bits are modified. */ + if (datalo != base && datalo != index) { + /* XOR breaks dependency chains. */ + tgen_arithr(s, ARITH_XOR, datalo, datalo); tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg, datalo, base, index, 0, ofs); } else { - tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo, - base, index, 0, ofs); - tcg_out_rolw_8(s, datalo); + tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg, + datalo, base, index, 0, ofs); + tcg_out_ext16u(s, datalo, datalo); } - tcg_out_modrm(s, OPC_MOVSWL + rexw, datalo, datalo); + } else { + tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo, + base, index, 0, ofs); + } + break; + case MO_SW: + if (use_movbe) { + tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg, + datalo, base, index, 0, ofs); + tcg_out_ext16s(s, datalo, datalo, rexw); } else { tcg_out_modrm_sib_offset(s, OPC_MOVSWL + rexw + seg, datalo, base, index, 0, ofs); @@ -2030,18 +2035,12 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, break; case MO_UL: tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs); - if (bswap) { - tcg_out_bswap32(s, datalo); - } break; #if TCG_TARGET_REG_BITS == 64 case MO_SL: - if (real_bswap) { - tcg_out_modrm_sib_offset(s, movop + seg, datalo, + if (use_movbe) { + tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + seg, datalo, base, index, 0, ofs); - if (bswap) { - tcg_out_bswap32(s, datalo); - } tcg_out_ext32s(s, datalo, datalo); } else { tcg_out_modrm_sib_offset(s, OPC_MOVSLQ + seg, datalo, @@ -2053,12 +2052,9 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, if (TCG_TARGET_REG_BITS == 64) { tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo, base, index, 0, ofs); - if (bswap) { - tcg_out_bswap64(s, datalo); - } } else { - if (real_bswap) { - int t = datalo; + if (use_movbe) { + TCGReg t = datalo; datalo = datahi; datahi = t; } @@ -2073,14 +2069,10 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs); } - if (bswap) { - tcg_out_bswap32(s, datalo); - tcg_out_bswap32(s, datahi); - } } break; default: - tcg_abort(); + g_assert_not_reached(); } } @@ -2128,24 +2120,27 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, TCGReg base, int index, intptr_t ofs, int seg, MemOp memop) { - /* ??? Ideally we wouldn't need a scratch register. For user-only, - we could perform the bswap twice to restore the original value - instead of moving to the scratch. But as it is, the L constraint - means that TCG_REG_L0 is definitely free here. */ const TCGReg scratch = TCG_REG_L0; - const MemOp real_bswap = memop & MO_BSWAP; - MemOp bswap = real_bswap; + bool use_movbe = false; int movop = OPC_MOVL_EvGv; - if (have_movbe && real_bswap) { - bswap = 0; + /* + * Do big-endian stores with movbe or softmmu. + * User-only without movbe will have its swapping done generically. + */ + if (memop & MO_BSWAP) { + tcg_debug_assert(have_movbe); + use_movbe = true; movop = OPC_MOVBE_MyGy; } switch (memop & MO_SIZE) { case MO_8: - /* In 32-bit mode, 8-bit stores can only happen from [abcd]x. - Use the scratch register if necessary. */ + /* + * In 32-bit mode, 8-bit stores can only happen from [abcd]x. + * TODO: Adjust constraints such that this is is forced, + * then we won't need a scratch at all for user-only. + */ if (TCG_TARGET_REG_BITS == 32 && datalo >= 4) { tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); datalo = scratch; @@ -2154,43 +2149,19 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, datalo, base, index, 0, ofs); break; case MO_16: - if (bswap) { - tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); - tcg_out_rolw_8(s, scratch); - datalo = scratch; - } tcg_out_modrm_sib_offset(s, movop + P_DATA16 + seg, datalo, base, index, 0, ofs); break; case MO_32: - if (bswap) { - tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); - tcg_out_bswap32(s, scratch); - datalo = scratch; - } tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs); break; case MO_64: if (TCG_TARGET_REG_BITS == 64) { - if (bswap) { - tcg_out_mov(s, TCG_TYPE_I64, scratch, datalo); - tcg_out_bswap64(s, scratch); - datalo = scratch; - } tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo, base, index, 0, ofs); - } else if (bswap) { - tcg_out_mov(s, TCG_TYPE_I32, scratch, datahi); - tcg_out_bswap32(s, scratch); - tcg_out_modrm_sib_offset(s, OPC_MOVL_EvGv + seg, scratch, - base, index, 0, ofs); - tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); - tcg_out_bswap32(s, scratch); - tcg_out_modrm_sib_offset(s, OPC_MOVL_EvGv + seg, scratch, - base, index, 0, ofs + 4); } else { - if (real_bswap) { - int t = datalo; + if (use_movbe) { + TCGReg t = datalo; datalo = datahi; datahi = t; } @@ -2201,7 +2172,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, } break; default: - tcg_abort(); + g_assert_not_reached(); } } From patchwork Thu Jan 7 20:14:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358249 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp777157jai; Thu, 7 Jan 2021 12:15:37 -0800 (PST) X-Google-Smtp-Source: ABdhPJzBji8F5rUcglKbCaQR/5tYM8qLZFWPBwxq9EeCy5MDoiUPeCDmGiIFYl9jOEswF13ipiO7 X-Received: by 2002:a25:743:: with SMTP id 64mr642308ybh.333.1610050537568; Thu, 07 Jan 2021 12:15:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610050537; cv=none; d=google.com; s=arc-20160816; b=Atv9ATvQg5G275tRlCO78eS0ll+yT+twPvFIT7ek0syMI3FikWg569QVoQv5YGnpps rQvqxS2EHS0KbBiQXThzHtGt0FjWb3ihOv88EH/z3vdgeeQ47cM9nX0uKI2R+PAPT74W yuFNg//y98DR+Axa7xk1TeFrGN7qMgljRP/OgA5Sa/oWPcjIdZnjXtRaGYWLwmmLKT4j TheSmLxB4XzWNCz5BplfU5egi6IVO3lTy44yG16TCoFaOKgKrRpTcRZUz4eJQ1S8DYCv vpIeP2kT/891gM4scdiuikY+m5XuPpTOE57Tc0k9QyMdU4PHNw6B96K9xtuicmlT5yG+ LlRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=7cOc/EO426UcFq+Ds2TZQxNrDdGfPnqOjFWRfHCKoV4=; b=sd1fZG8TgCXYbgswAJro7k2MPpuiaOstO7qqi5xwFbRaD+RZGeg/BQo7O8H10QuT7K SHJosL8QNBNfwBBUjPeegl5ePzcu9ohVfHcoaKXlK0J9um6+Z1Zy6E9gdx1qIA/rrB6+ TKwscXo8vu3Bkwdjta4zDoh6wt7/3WVBLLqe7LmspY04wmtAYjjfkkt9HgRbor0YbIPj uVoNiYd/mXv/yj0N2fd/RsYllOSZQ6T8MERLo0p0j9mnhfVvK8Mo93+BfWymVxV1vhQ7 A2Lb9OF8F3vEkKYEeMY1Ml/BbkvG1xL/EofPJaCTlhselvm8CC/9OT+Bentb+pBF3pp9 qkBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="u/Ao3UOq"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.14.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:14:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 03/47] tcg: Introduce INDEX_op_qemu_st8_i32 Date: Thu, 7 Jan 2021 10:14:04 -1000 Message-Id: <20210107201448.1152301-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Enable this on i386 to restrict the set of input registers for an 8-bit store, as required by the architecture. This removes the last use of scratch registers for user-only mode. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 5 +++++ tcg/aarch64/tcg-target.h | 1 + tcg/arm/tcg-target.h | 1 + tcg/i386/tcg-target.h | 3 +++ tcg/mips/tcg-target.h | 1 + tcg/ppc/tcg-target.h | 1 + tcg/riscv/tcg-target.h | 1 + tcg/s390/tcg-target.h | 1 + tcg/sparc/tcg-target.h | 1 + tcg/tci/tcg-target.h | 1 + tcg/optimize.c | 1 + tcg/tcg-op.c | 6 +++++- tcg/tcg.c | 4 ++++ tcg/i386/tcg-target.c.inc | 29 ++++++++++++++++++----------- tcg/README | 5 +++++ 15 files changed, 49 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 67092e82c6..70a76646c4 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -211,6 +211,11 @@ DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 1, DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) +/* Only used by i386 to cope with stupid register constraints. */ +DEF(qemu_st8_i32, 0, TLADDR_ARGS + 1, 1, + TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | + IMPL(TCG_TARGET_HAS_qemu_st8_i32)) + /* Host vector support. */ #define IMPLVEC TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 8a6b97598e..108a1fa969 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -88,6 +88,7 @@ typedef enum { #define TCG_TARGET_HAS_extrl_i64_i32 0 #define TCG_TARGET_HAS_extrh_i64_i32 0 #define TCG_TARGET_HAS_goto_ptr 1 +#define TCG_TARGET_HAS_qemu_st8_i32 0 #define TCG_TARGET_HAS_div_i64 1 #define TCG_TARGET_HAS_rem_i64 1 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index f1955ce4ac..1e18fefd0e 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -126,6 +126,7 @@ extern bool use_idiv_instructions; #define TCG_TARGET_HAS_rem_i32 0 #define TCG_TARGET_HAS_goto_ptr 1 #define TCG_TARGET_HAS_direct_jump 0 +#define TCG_TARGET_HAS_qemu_st8_i32 0 enum { TCG_AREG0 = TCG_REG_R6, diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index b1ada9777a..f3836a4d0c 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -172,6 +172,9 @@ extern bool have_movbe; #define TCG_TARGET_HAS_muls2_i64 1 #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i64 0 +#define TCG_TARGET_HAS_qemu_st8_i32 0 +#else +#define TCG_TARGET_HAS_qemu_st8_i32 1 #endif /* We do not support older SSE systems, only beginning with AVX1. */ diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 92c1d63da3..624248b81e 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -169,6 +169,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_clz_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_ctz_i32 0 #define TCG_TARGET_HAS_ctpop_i32 0 +#define TCG_TARGET_HAS_qemu_st8_i32 0 #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_movcond_i64 use_movnz_instructions diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index a509a19628..301173c97e 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -108,6 +108,7 @@ extern bool have_vsx; #define TCG_TARGET_HAS_mulsh_i32 1 #define TCG_TARGET_HAS_goto_ptr 1 #define TCG_TARGET_HAS_direct_jump 1 +#define TCG_TARGET_HAS_qemu_st8_i32 0 #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_add2_i32 0 diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index c1bd52bb9a..888288d54c 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -119,6 +119,7 @@ typedef enum { #define TCG_TARGET_HAS_direct_jump 0 #define TCG_TARGET_HAS_brcond2 1 #define TCG_TARGET_HAS_setcond2 1 +#define TCG_TARGET_HAS_qemu_st8_i32 0 #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_movcond_i64 0 diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index b4feb2f55a..69576f4a9a 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -97,6 +97,7 @@ extern uint64_t s390_facilities; #define TCG_TARGET_HAS_extrh_i64_i32 0 #define TCG_TARGET_HAS_goto_ptr 1 #define TCG_TARGET_HAS_direct_jump (s390_facilities & FACILITY_GEN_INST_EXT) +#define TCG_TARGET_HAS_qemu_st8_i32 0 #define TCG_TARGET_HAS_div2_i64 1 #define TCG_TARGET_HAS_rot_i64 1 diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index d8b0e32e2e..9dce305253 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -126,6 +126,7 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_goto_ptr 1 #define TCG_TARGET_HAS_direct_jump 1 +#define TCG_TARGET_HAS_qemu_st8_i32 0 #define TCG_TARGET_HAS_extrl_i64_i32 1 #define TCG_TARGET_HAS_extrh_i64_i32 1 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index b84480f989..e8277caee2 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -88,6 +88,7 @@ #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_goto_ptr 0 #define TCG_TARGET_HAS_direct_jump 1 +#define TCG_TARGET_HAS_qemu_st8_i32 0 #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_extrl_i64_i32 0 diff --git a/tcg/optimize.c b/tcg/optimize.c index 7ca71de956..1fb42eb2a9 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1541,6 +1541,7 @@ void tcg_optimize(TCGContext *s) case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_st8_i32: case INDEX_op_qemu_st_i64: case INDEX_op_call: /* Opcodes that touch guest memory stop the optimization. */ diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 4b8a473fad..af7ce91ffa 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2883,7 +2883,11 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop) } addr = plugin_prep_mem_callbacks(addr); - gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx); + if (TCG_TARGET_HAS_qemu_st8_i32 && (memop & MO_SIZE) == MO_8) { + gen_ldst_i32(INDEX_op_qemu_st8_i32, val, addr, memop, idx); + } else { + gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx); + } plugin_gen_mem_callbacks(addr, info); if (swap) { diff --git a/tcg/tcg.c b/tcg/tcg.c index ebb9466ffc..95aacc8597 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1427,6 +1427,9 @@ bool tcg_op_supported(TCGOpcode op) case INDEX_op_qemu_st_i64: return true; + case INDEX_op_qemu_st8_i32: + return TCG_TARGET_HAS_qemu_st8_i32; + case INDEX_op_goto_ptr: return TCG_TARGET_HAS_goto_ptr; @@ -2087,6 +2090,7 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs) break; case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_st8_i32: case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: { diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 01588cdcb4..f8e9a24e3b 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -245,11 +245,21 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, ct->regs |= ALL_VECTOR_REGS; break; - /* qemu_ld/st address constraint */ case 'L': + /* qemu_ld/st data+address constraint */ ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff; +#ifdef CONFIG_SOFTMMU tcg_regset_reset_reg(ct->regs, TCG_REG_L0); tcg_regset_reset_reg(ct->regs, TCG_REG_L1); +#endif + break; + case 's': + /* qemu_st8_i32 data constraint */ + ct->regs = 0xf; +#ifdef CONFIG_SOFTMMU + tcg_regset_reset_reg(ct->regs, TCG_REG_L0); + tcg_regset_reset_reg(ct->regs, TCG_REG_L1); +#endif break; case 'e': @@ -2120,7 +2130,6 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, TCGReg base, int index, intptr_t ofs, int seg, MemOp memop) { - const TCGReg scratch = TCG_REG_L0; bool use_movbe = false; int movop = OPC_MOVL_EvGv; @@ -2136,15 +2145,8 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, switch (memop & MO_SIZE) { case MO_8: - /* - * In 32-bit mode, 8-bit stores can only happen from [abcd]x. - * TODO: Adjust constraints such that this is is forced, - * then we won't need a scratch at all for user-only. - */ - if (TCG_TARGET_REG_BITS == 32 && datalo >= 4) { - tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); - datalo = scratch; - } + /* This is handled with constraints on INDEX_op_qemu_st8_i32. */ + tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || datalo < 4); tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg, datalo, base, index, 0, ofs); break; @@ -2491,6 +2493,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_qemu_ld(s, args, 1); break; case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_st8_i32: tcg_out_qemu_st(s, args, 0); break; case INDEX_op_qemu_st_i64: @@ -2949,9 +2952,11 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) static const TCGTargetOpDef r_0_ci = { .args_ct_str = { "r", "0", "ci" } }; static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } }; + static const TCGTargetOpDef s_L = { .args_ct_str = { "s", "L" } }; static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } }; static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } }; static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } }; + static const TCGTargetOpDef s_L_L = { .args_ct_str = { "s", "L", "L" } }; static const TCGTargetOpDef r_r_L_L = { .args_ct_str = { "r", "r", "L", "L" } }; static const TCGTargetOpDef L_L_L_L @@ -3145,6 +3150,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L; case INDEX_op_qemu_st_i32: return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L : &L_L_L; + case INDEX_op_qemu_st8_i32: + return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &s_L : &s_L_L; case INDEX_op_qemu_ld_i64: return (TCG_TARGET_REG_BITS == 64 ? &r_L : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L diff --git a/tcg/README b/tcg/README index 2f051e5c97..0cf9e2727c 100644 --- a/tcg/README +++ b/tcg/README @@ -502,6 +502,7 @@ goto_ptr opcode, emitting this op is equivalent to emitting exit_tb(0). * qemu_ld_i32/i64 t0, t1, flags, memidx * qemu_st_i32/i64 t0, t1, flags, memidx +* qemu_st8_i32 t0, t1, flags, memidx Load data at the guest address t1 into t0, or store data in t0 at guest address t1. The _i32/_i64 size applies to the size of the input/output @@ -518,6 +519,10 @@ of the memory access. For a 32-bit host, qemu_ld/st_i64 is guaranteed to only be used with a 64-bit memory access specified in flags. +For i386, qemu_st8_i32 is exactly like qemu_st_i32, except the size of +the memory operation is known to be 8-bit. This allows the backend to +provide a different set of register constraints. + ********* Host vector operations All of the vector ops have two parameters, TCGOP_VECL & TCGOP_VECE. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.14.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:14:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 04/47] util/oslib-win32: Use _aligned_malloc for qemu_try_memalign Date: Thu, 7 Jan 2021 10:14:05 -1000 Message-Id: <20210107201448.1152301-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Stefan Weil Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We do not need or want to be allocating page sized quanta. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Stefan Weil Message-Id: <20201018164836.1149452-1-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- util/oslib-win32.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/util/oslib-win32.c b/util/oslib-win32.c index 01787df74c..8adc651259 100644 --- a/util/oslib-win32.c +++ b/util/oslib-win32.c @@ -39,6 +39,7 @@ #include "trace.h" #include "qemu/sockets.h" #include "qemu/cutils.h" +#include /* this must come after including "trace.h" */ #include @@ -56,10 +57,8 @@ void *qemu_try_memalign(size_t alignment, size_t size) { void *ptr; - if (!size) { - abort(); - } - ptr = VirtualAlloc(NULL, size, MEM_COMMIT, PAGE_READWRITE); + g_assert(size != 0); + ptr = _aligned_malloc(alignment, size); trace_qemu_memalign(alignment, size, ptr); return ptr; } @@ -93,9 +92,7 @@ void *qemu_anon_ram_alloc(size_t size, uint64_t *align, bool shared) void qemu_vfree(void *ptr) { trace_qemu_vfree(ptr); - if (ptr) { - VirtualFree(ptr, 0, MEM_RELEASE); - } + _aligned_free(ptr); } void qemu_anon_ram_free(void *ptr, size_t size) From patchwork Thu Jan 7 20:14:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358250 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp779265jai; Thu, 7 Jan 2021 12:19:07 -0800 (PST) X-Google-Smtp-Source: ABdhPJyTpw1zHqOUhuWa89NYBCDmRs5qSMC3uZagUOGQ8/gGb9+U68RrFtvu5c+2F14uxGTXEXMQ X-Received: by 2002:a25:b43:: with SMTP id 64mr770901ybl.57.1610050747718; Thu, 07 Jan 2021 12:19:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610050747; cv=none; d=google.com; s=arc-20160816; b=Zp8x8YRcnKKlTatZHEPCx3JM2MQiGpGvTIoT/ymP7Y18uvUuxmWl2Nc7PqhhsTGwmG bks0o0s6M1du1DdxuKs6GRZZn1llKYZf4PKAVmlBLJTmHAyOutrlVfpNJVEEw/YnSy3t kYVGUgjBFWpvdQ//oO71JJEIKj8G2OWrnpfPp8OXQKeVZvYBSZBVN9gyT21YZcoweYID gDJu84yGp+DJi1pWpCaxbxwAzCXAr/wfo35du3BakHfvCvo3gBO0z+nmGvX5OFSiFNJ7 +SiCFH/Nu1+AAqxw9Gn5nOJdoS9+cbw8trFG4wn795yOBGoECjJcKCO0CqUOamI5Tq+W fRSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xH5M81fqmCpdca/RUuW2bG6ZjrHw1rwqh2ryuVvV5yk=; b=QQkRZWoPU45Dc1+U65dvKRBn4aJo90yoJ+dXUPyknvKeyg2IStAPixnDCMFUsoLBuK Bd5Mqv3y2WpJMgPcx+/m1gQ8Ne6zRbm34RCSPNwusQJqLZmsP7XuInq7T1pi9QfNI7+Y fdnEOUMz0igE4ks5WxqyEbEucLebw5E+XhMSyRr+gepBB9R9wD5GrkjVKStpn2jdJcct K43v8G3lqFtpgxKJNoYh7Zu9LsHJxbP9kM7UOSfI+JkhcLkAz101vuAKwCTyv9TqK9jV 7O7/DQNBhu0sVqvPS6Suy0x6lEa97KtjuTsI3N8aH4g58NiFG94tikCDQsKPSjtaKSCP uPFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nxaC4v5m; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.14.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 05/47] util/oslib: Assert qemu_try_memalign() alignment is a power of 2 Date: Thu, 7 Jan 2021 10:14:06 -1000 Message-Id: <20210107201448.1152301-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé qemu_try_memalign() expects a power of 2 alignment: - posix_memalign(3): The address of the allocated memory will be a multiple of alignment, which must be a power of two and a multiple of sizeof(void *). - _aligned_malloc() The alignment value, which must be an integer power of 2. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20201021173803.2619054-3-philmd@redhat.com> Signed-off-by: Richard Henderson --- util/oslib-posix.c | 2 ++ util/oslib-win32.c | 1 + 2 files changed, 3 insertions(+) -- 2.25.1 diff --git a/util/oslib-posix.c b/util/oslib-posix.c index f1e2801b11..359c52df12 100644 --- a/util/oslib-posix.c +++ b/util/oslib-posix.c @@ -201,6 +201,8 @@ void *qemu_try_memalign(size_t alignment, size_t size) if (alignment < sizeof(void*)) { alignment = sizeof(void*); + } else { + g_assert(is_power_of_2(alignment)); } #if defined(CONFIG_POSIX_MEMALIGN) diff --git a/util/oslib-win32.c b/util/oslib-win32.c index 8adc651259..e6f83e10ed 100644 --- a/util/oslib-win32.c +++ b/util/oslib-win32.c @@ -58,6 +58,7 @@ void *qemu_try_memalign(size_t alignment, size_t size) void *ptr; g_assert(size != 0); + g_assert(is_power_of_2(alignment)); ptr = _aligned_malloc(alignment, size); trace_qemu_memalign(alignment, size, ptr); return ptr; From patchwork Thu Jan 7 20:14:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358251 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp779311jai; Thu, 7 Jan 2021 12:19:11 -0800 (PST) X-Google-Smtp-Source: ABdhPJz8YOTp7W3bmqOjjrz8nHh1r/468XaApviz5w+lt/uYIZUMdYj2tATTnNDA7b6s2aj9f8AQ X-Received: by 2002:a5b:410:: with SMTP id m16mr718642ybp.451.1610050751256; Thu, 07 Jan 2021 12:19:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610050751; cv=none; d=google.com; s=arc-20160816; b=yCyS9ZM2XdW5b0ieGeCcEoaJSDR4976bUXSImZ8KM6HhQOt82y+WaR46Yqj2ASrF1D Eju9dVd5aBdcOUJbVHyy37elV9ngC9SXqC8OoIytEnZXRr4RmOCHE7t3meXBurx5tFCq M+A23GvcQeKlDdKNqo6AMfgbMaeE8UUqedO00dLivnd2PqlVNLorcYLb/9+H1m1AFZw/ 4FmvWUeClhS4U5+quYwbLdyHcQDmv2Gxgo8xWObgB+YIEP5JylXJCnJW7i/Vvo5VRmNh eHeelEfNMAueZ/XLGAGMxFUwo6kDbNfcK4v81NAYBXJ39U0AELx4p6aVS4ZA9yJNpYRj XF8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=gV4erddw36/IIPMNTq7/TG+v9uQaJ4h6PGeY7YFnJXE=; b=FqRQ+BquSsyG/I3yLEJm7bH3tfBjJhqWMVK+W2Y8QDhIQl4jZ+/RdRKR6VS5X94cjc itwd1FLf5MTx1mw90VyPjSLkX08PFj2UrsQ+DtX+6EvSfq/1cp4f744RFoKHN/kvNlbr UK1ozp28WcHFRTJecyqyy9r+frPYD+IvJq+RnaZjzBup2ZhvT3q9Ktg62pmh5w1AxwfO 7I9Yp6MRjtQORGgU7LvNlOqKqlNWPFT5eh9rP1cnjnICnVDrTktCVRAydCjPR3Kl/N5v ILYvS0+4zqCKS1E8YOPg4zlNYtIPuaNFbsO2v4K/JPJT58FWAflZsCRhmhbgA9mFoa5G ++Ew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MGdg3hW9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 06/47] tcg: Do not flush icache for interpreter Date: Thu, 7 Jan 2021 10:14:07 -1000 Message-Id: <20210107201448.1152301-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Joelle van Dyne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is currently a no-op within tci/tcg-target.h, but is about to be moved to a more generic location. Reviewed-by: Joelle van Dyne Signed-off-by: Richard Henderson --- tcg/tcg.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.25.1 diff --git a/tcg/tcg.c b/tcg/tcg.c index 95aacc8597..9bdc450196 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1078,7 +1078,9 @@ void tcg_prologue_init(TCGContext *s) #endif buf1 = s->code_ptr; +#ifndef CONFIG_TCG_INTERPRETER flush_icache_range((uintptr_t)buf0, (uintptr_t)buf1); +#endif /* Deduct the prologue from the buffer. */ prologue_size = tcg_current_code_size(s); @@ -4324,8 +4326,10 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) return -2; } +#ifndef CONFIG_TCG_INTERPRETER /* flush instruction cache */ flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr); +#endif return tcg_current_code_size(s); } From patchwork Thu Jan 7 20:14:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358254 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp781075jai; Thu, 7 Jan 2021 12:22:18 -0800 (PST) X-Google-Smtp-Source: ABdhPJwf3EEDX7bXLDKbwJPtot4QMKH4nUA3ZK0pZQwkjFRDBvnw1w6595z4f/1s7gxcW2maEQtw X-Received: by 2002:a25:2e05:: with SMTP id u5mr798139ybu.297.1610050938571; Thu, 07 Jan 2021 12:22:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610050938; cv=none; d=google.com; s=arc-20160816; b=BkaRI+U+En/nY85R5wk4GOBdOpGojM/TLoBLz6sYkfYNf/HMiJoY8bmL5gw6ASiXIy hsm3cVBupPcl3ObOG6Ihh6J03mUo1ukB1Ehd4bw1peIu/pyQ3Hq3oirF4QkzAppXzNws ywDBxWd3OGWKFYrw2hxk60JmgLmWaiEDk3HcqFc5dZbSjGEeds5SVWi8b0azvwXrB3B6 6BvNToS9YNolCme2f1kbdYs1mEMs0irepxoytEwtlZisj2X1EzjTHre7cw/vmDINehC+ 4BkmraN1xGrxNZ7xUX1+PWeVIwIGeuw52TcLPwyl7vIZVV4Y9ZBNDKYNEcvG8JU9TdF8 TIjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=48z+GqlaobtZlttO/+L7peMtbYaAP6yESc8MWoNMMuc=; b=oCEpXiaihHyyNxLLNbHq/VT8+8dCNCzFQEzme/tMQRIoeSpXbuyh8YZ8swPqRJwb4Z xeLdbMQP4yjVxPOk87sSdnYq9gT3x7GzWf1RaYlSb0wKgQ9AlG033W4XO35iWiVkDA4C Gba0XlgOtDu8y1LvqIIiTUIhlL2x5zAIR86eNNyoBYZdK0v+AHByMCHERpGlKVoO2ofp a8riE+W3Zi3lDY2AQxF4NkFzZi4eNURlE9mRgNVKR6B5xwpiEVHo/6dMA32MHSbdMjAa cI2MZmeIR3WGejsBb6M65VyX5ix/4vvdSdsPMBHF0hwT/NiXLA4IExzsfWj2eKXTO4U8 TCmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=I78dbytR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 07/47] util: Enhance flush_icache_range with separate data pointer Date: Thu, 7 Jan 2021 10:14:08 -1000 Message-Id: <20210107201448.1152301-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Joelle van Dyne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We are shortly going to have a split rw/rx jit buffer. Depending on the host, we need to flush the dcache at the rw data pointer and flush the icache at the rx code pointer. For now, the two passed pointers are identical, so there is no effective change in behaviour. Reviewed-by: Joelle van Dyne Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/qemu/cacheflush.h | 15 ++++++++++++-- softmmu/physmem.c | 2 +- tcg/tcg.c | 6 ++++-- util/cacheflush.c | 38 +++++++++++++++++++++--------------- util/cacheinfo.c | 8 +++++--- tcg/aarch64/tcg-target.c.inc | 2 +- tcg/mips/tcg-target.c.inc | 2 +- tcg/ppc/tcg-target.c.inc | 4 ++-- tcg/sparc/tcg-target.c.inc | 4 ++-- 9 files changed, 51 insertions(+), 30 deletions(-) -- 2.25.1 diff --git a/include/qemu/cacheflush.h b/include/qemu/cacheflush.h index 58ae488491..ae20bcda73 100644 --- a/include/qemu/cacheflush.h +++ b/include/qemu/cacheflush.h @@ -8,16 +8,27 @@ #ifndef QEMU_CACHEFLUSH_H #define QEMU_CACHEFLUSH_H +/** + * flush_idcache_range: + * @rx: instruction address + * @rw: data address + * @len: length to flush + * + * Flush @len bytes of the data cache at @rw and the icache at @rx + * to bring them in sync. The two addresses may be different virtual + * mappings of the same physical page(s). + */ + #if defined(__i386__) || defined(__x86_64__) || defined(__s390__) -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) +static inline void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len) { /* icache is coherent and does not require flushing. */ } #else -void flush_icache_range(uintptr_t start, uintptr_t stop); +void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len); #endif diff --git a/softmmu/physmem.c b/softmmu/physmem.c index 8b9ffc41c2..6301f4f0a5 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -2946,7 +2946,7 @@ static inline MemTxResult address_space_write_rom_internal(AddressSpace *as, invalidate_and_set_dirty(mr, addr1, l); break; case FLUSH_CACHE: - flush_icache_range((uintptr_t)ram_ptr, (uintptr_t)ram_ptr + l); + flush_idcache_range((uintptr_t)ram_ptr, (uintptr_t)ram_ptr, l); break; } } diff --git a/tcg/tcg.c b/tcg/tcg.c index 9bdc450196..759a41d848 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1079,7 +1079,8 @@ void tcg_prologue_init(TCGContext *s) buf1 = s->code_ptr; #ifndef CONFIG_TCG_INTERPRETER - flush_icache_range((uintptr_t)buf0, (uintptr_t)buf1); + flush_idcache_range((uintptr_t)buf0, (uintptr_t)buf0, + tcg_ptr_byte_diff(buf1, buf0)); #endif /* Deduct the prologue from the buffer. */ @@ -4328,7 +4329,8 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) #ifndef CONFIG_TCG_INTERPRETER /* flush instruction cache */ - flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr); + flush_idcache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_buf, + tcg_ptr_byte_diff(s->code_ptr, s->code_buf)); #endif return tcg_current_code_size(s); diff --git a/util/cacheflush.c b/util/cacheflush.c index 2881832a38..92805efe49 100644 --- a/util/cacheflush.c +++ b/util/cacheflush.c @@ -21,29 +21,32 @@ #include #endif -void flush_icache_range(uintptr_t start, uintptr_t stop) +void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len) { - cacheflush((void *)start, stop - start, ICACHE); + if (rx != rw) { + cacheflush((void *)rw, len, DCACHE); + } + cacheflush((void *)rx, len, ICACHE); } #elif defined(__powerpc__) -void flush_icache_range(uintptr_t start, uintptr_t stop) +void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len) { - uintptr_t p, start1, stop1; + uintptr_t p, b, e; size_t dsize = qemu_dcache_linesize; size_t isize = qemu_icache_linesize; - start1 = start & ~(dsize - 1); - stop1 = (stop + dsize - 1) & ~(dsize - 1); - for (p = start1; p < stop1; p += dsize) { + b = rw & ~(dsize - 1); + e = (rw + len + dsize - 1) & ~(dsize - 1); + for (p = b; p < e; p += dsize) { asm volatile ("dcbst 0,%0" : : "r"(p) : "memory"); } asm volatile ("sync" : : : "memory"); - start &= start & ~(isize - 1); - stop1 = (stop + isize - 1) & ~(isize - 1); - for (p = start1; p < stop1; p += isize) { + b = rx & ~(isize - 1); + e = (rx + len + isize - 1) & ~(isize - 1); + for (p = b; p < e; p += isize) { asm volatile ("icbi 0,%0" : : "r"(p) : "memory"); } asm volatile ("sync" : : : "memory"); @@ -52,20 +55,23 @@ void flush_icache_range(uintptr_t start, uintptr_t stop) #elif defined(__sparc__) -void flush_icache_range(uintptr_t start, uintptr_t stop) +void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len) { - uintptr_t p; - - for (p = start & -8; p < ((stop + 7) & -8); p += 8) { + /* No additional data flush to the RW virtual address required. */ + uintptr_t p, end = (rx + len + 7) & -8; + for (p = rx & -8; p < end; p += 8) { __asm__ __volatile__("flush\t%0" : : "r" (p)); } } #else -void flush_icache_range(uintptr_t start, uintptr_t stop) +void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len) { - __builtin___clear_cache((char *)start, (char *)stop); + if (rw != rx) { + __builtin___clear_cache((char *)rw, (char *)rw + len); + } + __builtin___clear_cache((char *)rx, (char *)rx + len); } #endif diff --git a/util/cacheinfo.c b/util/cacheinfo.c index 7804c186b6..b182f0b693 100644 --- a/util/cacheinfo.c +++ b/util/cacheinfo.c @@ -166,9 +166,11 @@ static void fallback_cache_info(int *isize, int *dsize) *isize = *dsize; } else { #if defined(_ARCH_PPC) - /* For PPC, we're going to use the icache size computed for - flush_icache_range. Which means that we must use the - architecture minimum. */ + /* + * For PPC, we're going to use the cache sizes computed for + * flush_idcache_range. Which means that we must use the + * architecture minimum. + */ *isize = *dsize = 16; #else /* Otherwise, 64 bytes is not uncommon. */ diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 26f71cb599..83af3108a4 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1363,7 +1363,7 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, } pair = (uint64_t)i2 << 32 | i1; qatomic_set((uint64_t *)jmp_addr, pair); - flush_icache_range(jmp_addr, jmp_addr + 8); + flush_idcache_range(jmp_addr, jmp_addr, 8); } static inline void tcg_out_goto_label(TCGContext *s, TCGLabel *l) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 41be574e89..c255ecb444 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -2660,7 +2660,7 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, uintptr_t addr) { qatomic_set((uint32_t *)jmp_addr, deposit32(OPC_J, 0, 26, addr >> 2)); - flush_icache_range(jmp_addr, jmp_addr + 4); + flush_idcache_range(jmp_addr, jmp_addr, 4); } typedef struct { diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 0d068ec8ab..b756281042 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1753,12 +1753,12 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, /* As per the enclosing if, this is ppc64. Avoid the _Static_assert within qatomic_set that would fail to build a ppc32 host. */ qatomic_set__nocheck((uint64_t *)jmp_addr, pair); - flush_icache_range(jmp_addr, jmp_addr + 8); + flush_idcache_range(jmp_addr, jmp_addr, 8); } else { intptr_t diff = addr - jmp_addr; tcg_debug_assert(in_range_b(diff)); qatomic_set((uint32_t *)jmp_addr, B | (diff & 0x3fffffc)); - flush_icache_range(jmp_addr, jmp_addr + 4); + flush_idcache_range(jmp_addr, jmp_addr, 4); } } diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 6775bd30fc..6e2d755f6a 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -1836,7 +1836,7 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, if (!USE_REG_TB) { qatomic_set((uint32_t *)jmp_addr, deposit32(CALL, 0, 30, br_disp >> 2)); - flush_icache_range(jmp_addr, jmp_addr + 4); + flush_idcache_range(jmp_addr, jmp_addr, 4); return; } @@ -1860,5 +1860,5 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, } qatomic_set((uint64_t *)jmp_addr, deposit64(i2, 32, 32, i1)); - flush_icache_range(jmp_addr, jmp_addr + 8); + flush_idcache_range(jmp_addr, jmp_addr, 8); } From patchwork Thu Jan 7 20:14:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358262 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp784101jai; Thu, 7 Jan 2021 12:27:27 -0800 (PST) X-Google-Smtp-Source: ABdhPJyl9eswb542Cjsbqz8umUsC1wtfwMOyGICTy/zzyHtwMWIBn9ohGt+Ct5Xb+Ip2YXiGSzP/ X-Received: by 2002:a25:bd92:: with SMTP id f18mr750559ybh.369.1610051247041; Thu, 07 Jan 2021 12:27:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610051247; cv=none; d=google.com; s=arc-20160816; b=fxPQ9jS2MxIBQT+K3q4Awc6h8qlOW5iwZnnzan5gL4TBsfCMO4E/R93A6KTUT0epSY LJnbSIh/bmjvEjbLOX/VnzFJ3ofg/dk6rCBexidJk8inV/ipbCPvaaO12j6JiH1xpTJq SxcphVm9Pq0/FPJzbdqNyfg6nt98esHVxUGkG/QkvuAv8BcemJY3RT7jveFjMAvqO/um Wq1pCwKEV2OayWwOAlJRkbN0x5H8XRSS/jPsJ407jee5BNIQEq3JY/GHBcJ6ed9jQclF taHHtIXlGgq9e7EoqGBuRkpfZX5WrjXjteTFxxax6Dch4PghWsf01KIllr4lW/5h/Dg6 CSsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NqDvAjSsLSimLcFmAjOdfLypVhA8Qg70u4hgiCmTSw4=; b=obYJFbjRJv3zKix3kHEa4Be7mcYPdN5lCjqxoJCsUHTtWmVronVDPTLCTsiaZqYTVq 07Jl+hrb+I4nuuRp7DpgV23D3L503q/8o4sfXuwmrfEmysaYcyY5OSAbpIKl2RR+PZWT 9CTPcTa+hEPphC6EZb4cXCKQvNDNfwey3wU/0vrl7xDsLqK4W19ICgbNv2WrP4a4T92z jF6rHnW/P25YZLfWPnJ3jqPl6/ufWmtFX/oJ3D3EZIPNCJrbvezQ4s1yJxXvEGdzNI2z ClvdxY1S5yfLhiMXFtGs9tf3ThzUymMDNjuf+ej9GqWIFpzJng3tCr33nx3iCxAIb816 BTeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Stwg9jZi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 08/47] util: Specialize flush_idcache_range for aarch64 Date: Thu, 7 Jan 2021 10:14:09 -1000 Message-Id: <20210107201448.1152301-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Joelle van Dyne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For darwin, the CTR_EL0 register is not accessible, but there are system routines that we can use. For other hosts, copy the single pointer implementation from libgcc and modify it to support the double pointer interface we require. This halves the number of cache operations required when split-rwx is enabled. Reviewed-by: Joelle van Dyne Signed-off-by: Richard Henderson --- util/cacheflush.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) -- 2.25.1 diff --git a/util/cacheflush.c b/util/cacheflush.c index 92805efe49..6a20723902 100644 --- a/util/cacheflush.c +++ b/util/cacheflush.c @@ -7,12 +7,81 @@ #include "qemu/osdep.h" #include "qemu/cacheflush.h" +#include "qemu/bitops.h" #if defined(__i386__) || defined(__x86_64__) || defined(__s390__) /* Caches are coherent and do not require flushing; symbol inline. */ +#elif defined(__aarch64__) + +#ifdef CONFIG_DARWIN +/* Apple does not expose CTR_EL0, so we must use system interfaces. */ +extern void sys_icache_invalidate(void *start, size_t len); +extern void sys_dcache_flush(void *start, size_t len); +void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len) +{ + sys_dcache_flush((void *)rw, len); + sys_icache_invalidate((void *)rx, len); +} +#else + +/* + * TODO: unify this with cacheinfo.c. + * We want to save the whole contents of CTR_EL0, so that we + * have more than the linesize, but also IDC and DIC. + */ +static unsigned int save_ctr_el0; +static void __attribute__((constructor)) init_ctr_el0(void) +{ + asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0)); +} + +/* + * This is a copy of gcc's __aarch64_sync_cache_range, modified + * to fit this three-operand interface. + */ +void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len) +{ + const unsigned CTR_IDC = 1u << 28; + const unsigned CTR_DIC = 1u << 29; + const unsigned int ctr_el0 = save_ctr_el0; + const uintptr_t icache_lsize = 4 << extract32(ctr_el0, 0, 4); + const uintptr_t dcache_lsize = 4 << extract32(ctr_el0, 16, 4); + uintptr_t p; + + /* + * If CTR_EL0.IDC is enabled, Data cache clean to the Point of Unification + * is not required for instruction to data coherence. + */ + if (!(ctr_el0 & CTR_IDC)) { + /* + * Loop over the address range, clearing one cache line at once. + * Data cache must be flushed to unification first to make sure + * the instruction cache fetches the updated data. + */ + for (p = rw & -dcache_lsize; p < rw + len; p += dcache_lsize) { + asm volatile("dc\tcvau, %0" : : "r" (p) : "memory"); + } + asm volatile("dsb\tish" : : : "memory"); + } + + /* + * If CTR_EL0.DIC is enabled, Instruction cache cleaning to the Point + * of Unification is not required for instruction to data coherence. + */ + if (!(ctr_el0 & CTR_DIC)) { + for (p = rx & -icache_lsize; p < rx + len; p += icache_lsize) { + asm volatile("ic\tivau, %0" : : "r"(p) : "memory"); + } + asm volatile ("dsb\tish" : : : "memory"); + } + + asm volatile("isb" : : : "memory"); +} +#endif /* CONFIG_DARWIN */ + #elif defined(__mips__) #ifdef __OpenBSD__ From patchwork Thu Jan 7 20:14:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358256 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp782590jai; Thu, 7 Jan 2021 12:24:44 -0800 (PST) X-Google-Smtp-Source: ABdhPJw4l1DxRniP1ETOcr9UJ5UivjziDWqWgYX9XIVDzGuHQ3PSPfYyebwCMKmkmmX+gCuy6dOm X-Received: by 2002:a25:1e42:: with SMTP id e63mr865701ybe.270.1610051084392; Thu, 07 Jan 2021 12:24:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610051084; cv=none; d=google.com; s=arc-20160816; b=j7BNHLtqc+gV1PtYpah3HJlwpX0GgDfghxd8EQsdixTwsao39vDkUEsa7wk/trtWZz Utyp30ODj+skjgnXpUUhKw15CBc5nYcYL2orw2eZIA1avjJnnyRKl6XHJV5LEUirlXEZ mvPRTGoZoy2y1oFPlREqFAcFmbEwtCIAGJf+NsvJU1lNmhWm9lVX35gUnXhSHpwjFlJk tSVjfwjfHdLSD3huazjVubQCM03LfEVkCM08Q5rglL880xkZRajuKcxHlIJ8/cPthM7c /2UyMrnfO5Kpy7l+0reefRxybMxgVG313bzuVs+Tkx8YtoDf8U25q9kopSP8mjDNd1bg FIdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=cwIe7ehFV7zcthsYPXS8JZ/YxLeGaqAzHfZida8viS0=; b=QnOeyKCn53vgL+ySejmg4BS8FN+kZI3Bb9rkelLQUTaGGuOG0R0vpBlX1DWzokk4z1 as+MZjrvcpoBZYu4yRo+HmE5kek7pJj0A05vBdrLoNAM5h29PX5y3KIFmlVZ45lJOZ3c Nh8QYjkvrvMvR7tZVlixRiiAT5B7OMvnZ7GMBGVjase8QxIxRlqYJJWoj24rGtjH6tXh Om5ZeHSgxpD6xEzBbzW39DkN2vXuPxBanNg1xT56QO9vEVFlgj3f1oGIA1gPlgC9k0uH 2bgO7pZBWXkYysXAYaGebq9FuMAXjmhMtmSnMvxacOufAYDKCemKsgE+NDDxvG1/vIvW Ohqw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BB4dVPFl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 09/47] tcg: Move tcg prologue pointer out of TCGContext Date: Thu, 7 Jan 2021 10:14:10 -1000 Message-Id: <20210107201448.1152301-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Joelle van Dyne , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This value is constant across all thread-local copies of TCGContext, so we might as well move it out of thread-local storage. Use the correct function pointer type, and name the variable tcg_qemu_tb_exec, which means that we are able to remove the macro that does the casting. Replace HAVE_TCG_QEMU_TB_EXEC with CONFIG_TCG_INTERPRETER, as this is somewhat clearer in intent. Reviewed-by: Joelle van Dyne Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 9 ++++----- tcg/tcg.c | 9 ++++++++- tcg/tci.c | 4 ++-- 3 files changed, 14 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 8ff9dad4ef..9cc412f90c 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -621,7 +621,6 @@ struct TCGContext { here, because there's too much arithmetic throughout that relies on addition and subtraction working on bytes. Rely on the GCC extension that allows arithmetic on void*. */ - void *code_gen_prologue; void *code_gen_epilogue; void *code_gen_buffer; size_t code_gen_buffer_size; @@ -1222,11 +1221,11 @@ static inline unsigned get_mmuidx(TCGMemOpIdx oi) #define TB_EXIT_IDXMAX 1 #define TB_EXIT_REQUESTED 3 -#ifdef HAVE_TCG_QEMU_TB_EXEC -uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr); +#ifdef CONFIG_TCG_INTERPRETER +uintptr_t tcg_qemu_tb_exec(CPUArchState *env, void *tb_ptr); #else -# define tcg_qemu_tb_exec(env, tb_ptr) \ - ((uintptr_t (*)(void *, void *))tcg_ctx->code_gen_prologue)(env, tb_ptr) +typedef uintptr_t tcg_prologue_fn(CPUArchState *env, void *tb_ptr); +extern tcg_prologue_fn *tcg_qemu_tb_exec; #endif void tcg_register_jit(void *buf, size_t buf_size); diff --git a/tcg/tcg.c b/tcg/tcg.c index 759a41d848..b686cc9ba8 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -162,6 +162,10 @@ static TCGContext **tcg_ctxs; static unsigned int n_tcg_ctxs; TCGv_env cpu_env = 0; +#ifndef CONFIG_TCG_INTERPRETER +tcg_prologue_fn *tcg_qemu_tb_exec; +#endif + struct tcg_region_tree { QemuMutex lock; GTree *tree; @@ -1055,7 +1059,10 @@ void tcg_prologue_init(TCGContext *s) s->code_ptr = buf0; s->code_buf = buf0; s->data_gen_ptr = NULL; - s->code_gen_prologue = buf0; + +#ifndef CONFIG_TCG_INTERPRETER + tcg_qemu_tb_exec = (tcg_prologue_fn *)buf0; +#endif /* Compute a high-water mark, at which we voluntarily flush the buffer and start over. The size here is arbitrary, significantly larger diff --git a/tcg/tci.c b/tcg/tci.c index 5d97b7c71c..cf0440445d 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -481,9 +481,9 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition) * One possible operation in the pseudo code is a call to binary code. * Therefore, disable CFI checks in the interpreter function */ -QEMU_DISABLE_CFI -uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) +uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, void *v_tb_ptr) { + uint8_t *tb_ptr = v_tb_ptr; tcg_target_ulong regs[TCG_TARGET_NB_REGS]; long tcg_temps[CPU_TEMP_BUF_NLONGS]; uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS); From patchwork Thu Jan 7 20:14:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358263 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp784350jai; Thu, 7 Jan 2021 12:27:51 -0800 (PST) X-Google-Smtp-Source: ABdhPJz5AIamYrG8mYddDBK6E04e2LzDxvY3bneHUiVeElAytnp/9p8cd3w2MJLNZ4nhK5Xa+RVG X-Received: by 2002:a25:d24a:: with SMTP id j71mr805473ybg.13.1610051271480; Thu, 07 Jan 2021 12:27:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610051271; cv=none; d=google.com; s=arc-20160816; b=V8yfkumo7jMcxNcbAFpU5ixZqkqz2BJAWZSIOi0kJro0yBs4koTYMU9Xiv8f21ysS6 m9eU1K/n0dahaC71JpTfiduhgbVCzqOgQbkLoslJ5w5mUNBC883sJmT6N/qJwNzpidkl Qfss6GWvRrh56mWymqT75qwHsaojOgmlVWsWktl4cHMGoe36xD1n72/ojEa4wqjwWvLq GJ6J/oDVFxE6lRlQOrtISy7tnRwb8eeR1so/KchkYBRfjkiF8CsnlqYXCt/RmUZu1t9Y wbsd/2WzMgprHBozNle0d4/IWOGckNXNnpm9i5sdMMXw9Nmu0k71PkikfX6t7HyYuUA2 hXoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=2Cs9+y1G+pu19qlVm3AK/YYBuG9IZ09f226BO4KIS2I=; b=0/YSwE8qwTQbOxAcO4CbyrOQzqfMb1skiHhkLRYIgXf5U/zOUY013Rn7SSUktIGilC 4qR68K9ibH7YJagGzpY7TLyiSmD2BMONJwZm6CgagdxEoks5LXXYyLGxbvjnspTi8aso A61rxrHEGz+16Qq8VPmrIYezrA0CFNjfrYZBw4UxOSv0vREW1BZyDLLk79MI2eY8rsSp 8E0+m0nZF3xWiOX3cdIfyUe/gzy17vDNj1JlWlaS+mWjBbA4S2jm178YwLk4ipBA67A0 GAAIPU2otni5zNlBd+VdeDBDVJa1EXK1jj+lFrCRafQ6lbVzYpmMJGXrk6TkBcu2bgUx 89Xg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vbejh20I; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 10/47] tcg: Move tcg epilogue pointer out of TCGContext Date: Thu, 7 Jan 2021 10:14:11 -1000 Message-Id: <20210107201448.1152301-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Joelle van Dyne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This value is constant across all thread-local copies of TCGContext, so we might as well move it out of thread-local storage. Reviewed-by: Joelle van Dyne Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 2 +- accel/tcg/tcg-runtime.c | 2 +- tcg/tcg.c | 3 ++- tcg/aarch64/tcg-target.c.inc | 4 ++-- tcg/arm/tcg-target.c.inc | 2 +- tcg/i386/tcg-target.c.inc | 4 ++-- tcg/mips/tcg-target.c.inc | 2 +- tcg/ppc/tcg-target.c.inc | 2 +- tcg/riscv/tcg-target.c.inc | 4 ++-- tcg/s390/tcg-target.c.inc | 4 ++-- tcg/sparc/tcg-target.c.inc | 2 +- 11 files changed, 16 insertions(+), 15 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 9cc412f90c..bb1e97b13b 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -621,7 +621,6 @@ struct TCGContext { here, because there's too much arithmetic throughout that relies on addition and subtraction working on bytes. Rely on the GCC extension that allows arithmetic on void*. */ - void *code_gen_epilogue; void *code_gen_buffer; size_t code_gen_buffer_size; void *code_gen_ptr; @@ -678,6 +677,7 @@ struct TCGContext { extern TCGContext tcg_init_ctx; extern __thread TCGContext *tcg_ctx; +extern void *tcg_code_gen_epilogue; extern TCGv_env cpu_env; static inline size_t temp_idx(TCGTemp *ts) diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index 446465a09a..f85dfefeab 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -154,7 +154,7 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env) tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, curr_cflags()); if (tb == NULL) { - return tcg_ctx->code_gen_epilogue; + return tcg_code_gen_epilogue; } qemu_log_mask_and_addr(CPU_LOG_EXEC, pc, "Chain %d: %p [" diff --git a/tcg/tcg.c b/tcg/tcg.c index b686cc9ba8..12f598cc18 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -161,6 +161,7 @@ static int tcg_out_ldst_finalize(TCGContext *s); static TCGContext **tcg_ctxs; static unsigned int n_tcg_ctxs; TCGv_env cpu_env = 0; +void *tcg_code_gen_epilogue; #ifndef CONFIG_TCG_INTERPRETER tcg_prologue_fn *tcg_qemu_tb_exec; @@ -1133,7 +1134,7 @@ void tcg_prologue_init(TCGContext *s) /* Assert that goto_ptr is implemented completely. */ if (TCG_TARGET_HAS_goto_ptr) { - tcg_debug_assert(s->code_gen_epilogue != NULL); + tcg_debug_assert(tcg_code_gen_epilogue != NULL); } } diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 83af3108a4..76f8ae48ad 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1873,7 +1873,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_exit_tb: /* Reuse the zeroing that exists for goto_ptr. */ if (a0 == 0) { - tcg_out_goto_long(s, s->code_gen_epilogue); + tcg_out_goto_long(s, tcg_code_gen_epilogue); } else { tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X0, a0); tcg_out_goto_long(s, tb_ret_addr); @@ -2894,7 +2894,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - s->code_gen_epilogue = s->code_ptr; + tcg_code_gen_epilogue = s->code_ptr; tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_X0, 0); /* TB epilogue */ diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 62c37a954b..1e32bf42b8 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2297,7 +2297,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - s->code_gen_epilogue = s->code_ptr; + tcg_code_gen_epilogue = s->code_ptr; tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0); tcg_out_epilogue(s); } diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index f8e9a24e3b..ee3a27069d 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2240,7 +2240,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_exit_tb: /* Reuse the zeroing that exists for goto_ptr. */ if (a0 == 0) { - tcg_out_jmp(s, s->code_gen_epilogue); + tcg_out_jmp(s, tcg_code_gen_epilogue); } else { tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_EAX, a0); tcg_out_jmp(s, tb_ret_addr); @@ -3803,7 +3803,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - s->code_gen_epilogue = s->code_ptr; + tcg_code_gen_epilogue = s->code_ptr; tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_EAX, 0); /* TB epilogue */ diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index c255ecb444..f641105f9a 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -2483,7 +2483,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - s->code_gen_epilogue = s->code_ptr; + tcg_code_gen_epilogue = s->code_ptr; tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); /* TB epilogue */ diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index b756281042..15d5c78798 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2341,7 +2341,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out32(s, BCCTR | BO_ALWAYS); /* Epilogue */ - s->code_gen_epilogue = tb_ret_addr = s->code_ptr; + tcg_code_gen_epilogue = tb_ret_addr = s->code_ptr; tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET); for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 4089e29cd9..25df85b33a 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1288,7 +1288,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_exit_tb: /* Reuse the zeroing that exists for goto_ptr. */ if (a0 == 0) { - tcg_out_call_int(s, s->code_gen_epilogue, true); + tcg_out_call_int(s, tcg_code_gen_epilogue, true); } else { tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0); tcg_out_call_int(s, tb_ret_addr, true); @@ -1822,7 +1822,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); /* Return path for goto_ptr. Set return value to 0 */ - s->code_gen_epilogue = s->code_ptr; + tcg_code_gen_epilogue = s->code_ptr; tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO); /* TB epilogue */ diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index c5e096449b..ac99ccea73 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -1756,7 +1756,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, /* Reuse the zeroing that exists for goto_ptr. */ a0 = args[0]; if (a0 == 0) { - tgen_gotoi(s, S390_CC_ALWAYS, s->code_gen_epilogue); + tgen_gotoi(s, S390_CC_ALWAYS, tcg_code_gen_epilogue); } else { tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, a0); tgen_gotoi(s, S390_CC_ALWAYS, tb_ret_addr); @@ -2561,7 +2561,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - s->code_gen_epilogue = s->code_ptr; + tcg_code_gen_epilogue = s->code_ptr; tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, 0); /* TB epilogue */ diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 6e2d755f6a..5b3bc91b05 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -1038,7 +1038,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_nop(s); /* Epilogue for goto_ptr. */ - s->code_gen_epilogue = s->code_ptr; + tcg_code_gen_epilogue = s->code_ptr; tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); /* delay slot */ tcg_out_movi_imm13(s, TCG_REG_O0, 0); From patchwork Thu Jan 7 20:14:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358265 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp785124jai; Thu, 7 Jan 2021 12:29:12 -0800 (PST) X-Google-Smtp-Source: ABdhPJwS4MQf4fiGC4VYgwYOvnFDME/7uCVpBUBCZ+i0gaxUxHAG7vC5/cqGHhT81Ti9NMgrAFfW X-Received: by 2002:a25:3812:: with SMTP id f18mr814541yba.157.1610051352742; Thu, 07 Jan 2021 12:29:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610051352; cv=none; d=google.com; s=arc-20160816; b=Z4lyh1gOHNKjrPrK6So3UE7WQc22wyJDVTlTfvAEZpju2Ttd9VTmwALizgBCgIk0U4 hKk9Xr1JMvbSEkDdzexI4U+USc6swc6JW2dU629H69Q+CET/0n0tM6I2OgouP4jkQ/AL aTjO1r8jWULvfvEOmORirQQYOQdJJliGGLsuCy+Ogoje7bKH0Qy9IbKfcwmwiyT81k0K 7I6/O3ePTWZdpRayIpQK6QlG0pXrj7aF8N995empW5eyEeXlSH990Drz2eIDJSp68F9A UVnYw62lfjeimjGWr0YqNsP85bUcDPjO+zgEGrtrnUpIuwcYy+66BQq6BNV5niRnAh9x byiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9ERcwQ1o1WQCtk37LfWcrGwhEwI+ExpBZ4567jVnbB8=; b=TS6/qENmr4ksFLjekrKeahxRyJifaz4VyDKUgRa3Fhw2hvcZN8j8MYMqyPJWCOF4qZ kcE/xEoBI3yBUZcx8bqPch8m2ygeIpJNn1yAiOul1VdnkFTrugZTouaVG4GYf2XzWmSk OkGe1gQ1qk8ve9iK9Sr9HR6Kbqz+3TpIB/KPwLGCuG4CkiJ1YBJ5rrJVwjWLuo2pQIEV osXZDqV142u+mGRnQg9xIkr6f8Fvznm+oa5012A/erVC+YA/I5N2bFsnNSoOWIfxR/Bf 8VwqjUrt18SDJGTND4l6p8vDU21bgRrdv4/kDaA8aiqx07T3roH8ACsynfR13ebgM5qq xE0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=koyIZqoB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 11/47] tcg: Add in_code_gen_buffer Date: Thu, 7 Jan 2021 10:14:12 -1000 Message-Id: <20210107201448.1152301-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a function to determine if a pointer is within the buffer. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 11 +++++++++++ accel/tcg/translate-all.c | 26 ++++++++------------------ 2 files changed, 19 insertions(+), 18 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index bb1e97b13b..ef571b6f3e 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -680,6 +680,17 @@ extern __thread TCGContext *tcg_ctx; extern void *tcg_code_gen_epilogue; extern TCGv_env cpu_env; +static inline bool in_code_gen_buffer(const void *p) +{ + const TCGContext *s = &tcg_init_ctx; + /* + * Much like it is valid to have a pointer to the byte past the + * end of an array (so long as you don't dereference it), allow + * a pointer to the byte past the end of the code gen buffer. + */ + return (size_t)(p - s->code_gen_buffer) <= s->code_gen_buffer_size; +} + static inline size_t temp_idx(TCGTemp *ts) { ptrdiff_t n = ts - tcg_ctx->temps; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index a1803a1026..3f9e25fa0c 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -392,27 +392,18 @@ void tb_destroy(TranslationBlock *tb) bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit) { - TranslationBlock *tb; - bool r = false; - uintptr_t check_offset; - - /* The host_pc has to be in the region of current code buffer. If - * it is not we will not be able to resolve it here. The two cases - * where host_pc will not be correct are: + /* + * The host_pc has to be in the region of the code buffer. + * If it is not we will not be able to resolve it here. + * The two cases where host_pc will not be correct are: * * - fault during translation (instruction fetch) * - fault from helper (not using GETPC() macro) * * Either way we need return early as we can't resolve it here. - * - * We are using unsigned arithmetic so if host_pc < - * tcg_init_ctx.code_gen_buffer check_offset will wrap to way - * above the code_gen_buffer_size */ - check_offset = host_pc - (uintptr_t) tcg_init_ctx.code_gen_buffer; - - if (check_offset < tcg_init_ctx.code_gen_buffer_size) { - tb = tcg_tb_lookup(host_pc); + if (in_code_gen_buffer((const void *)host_pc)) { + TranslationBlock *tb = tcg_tb_lookup(host_pc); if (tb) { cpu_restore_state_from_tb(cpu, tb, host_pc, will_exit); if (tb_cflags(tb) & CF_NOCACHE) { @@ -421,11 +412,10 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit) tcg_tb_remove(tb); tb_destroy(tb); } - r = true; + return true; } } - - return r; + return false; } static void page_init(void) From patchwork Thu Jan 7 20:14:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358267 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp786085jai; Thu, 7 Jan 2021 12:30:49 -0800 (PST) X-Google-Smtp-Source: ABdhPJzBf+nB/E1vTwKsGoXZlZsBEo8qF0kBqie0AwelgSZzKBUFDPKtqyb/03umajyvX1zC8RdZ X-Received: by 2002:a25:4984:: with SMTP id w126mr810307yba.391.1610051449861; Thu, 07 Jan 2021 12:30:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610051449; cv=none; d=google.com; s=arc-20160816; b=hEcxTsREHMQ/voBAqmGir5XEs+CVn5U+nfqmP12jSzSo0tZSuObjkf07Lepqz3oIpQ AQhR+Sc/biYSbQ9XGfOxpGmYqAuA23gkRlEXF4m0YmNoo0NQ5DcSw0d8FTFYxvqhzVgz BdKC+8M2vjS8IjWmottqWvNFT2S+XJeRle1yI5tOykstZpfl5Vq963QquIKbLghABwXR wu5zWtwd20of0dB/VJ1ClOW6Lm5hIdZEP4H8Fp+TkRznGznU2DNgO+MllzfqfOkGYWXd cZpFfAnTSwKZz6MRNjSAIN+m696hbdtr6myLubR80G9zQoGqIzkyGw6pv+4aTqLSe1sA x79w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=J5TmU4gbar1MXIri3MdIsFToppdmZPje42GiCM2xGSI=; b=WBMNOqyiB5hcAFmCi/mhwPSZXeV38U1ZdiKeHpiLPEKVqVEz06ewb7zwRfiVgqIxyd McBPf2IAwF05A2kYZSMQMDATF5lnV+EMnXMwgD6TLbdk1vrnLLRxGS8kYiOupo1rtNNo uWhCoUzgog3byFxqb6CkyYK1W2a3zFvLEbwZbuG5J+9FgOJqIV0nCR4FWxJKgT0Fzo8a bD+kt4aqDA/Ja38iR8v+/0K5/U72cgEw8KQsOVFc0m+I+3zER8ckMHXOFO00rgb6jLv9 ZVjW7RsXw5uat6YdObr1qH79oSEX1A/bLsVLIMjHeiY2Pd1b4/34mi6EwvuvX1yVOiq3 x+6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FJuFk4iU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 12/47] tcg: Introduce tcg_splitwx_to_{rx,rw} Date: Thu, 7 Jan 2021 10:14:13 -1000 Message-Id: <20210107201448.1152301-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Joelle van Dyne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add two helper functions, using a global variable to hold the displacement. The displacement is currently always 0, so no change in behaviour. Begin using the functions in tcg common code only. Reviewed-by: Joelle van Dyne Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 2 +- include/disas/disas.h | 2 +- include/exec/exec-all.h | 2 +- include/exec/log.h | 2 +- include/tcg/tcg.h | 26 ++++++++++++++---- accel/tcg/cpu-exec.c | 2 +- accel/tcg/tcg-runtime.c | 2 +- accel/tcg/translate-all.c | 33 +++++++++++------------ disas.c | 4 ++- tcg/tcg.c | 56 ++++++++++++++++++++++++++++++++++----- tcg/tci.c | 6 +++-- tcg/tcg-pool.c.inc | 6 ++++- accel/tcg/trace-events | 2 +- 13 files changed, 105 insertions(+), 40 deletions(-) -- 2.25.1 diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index 2e36d6eb0c..91a5b7e85f 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -24,7 +24,7 @@ DEF_HELPER_FLAGS_1(clrsb_i64, TCG_CALL_NO_RWG_SE, i64, i64) DEF_HELPER_FLAGS_1(ctpop_i32, TCG_CALL_NO_RWG_SE, i32, i32) DEF_HELPER_FLAGS_1(ctpop_i64, TCG_CALL_NO_RWG_SE, i64, i64) -DEF_HELPER_FLAGS_1(lookup_tb_ptr, TCG_CALL_NO_WG_SE, ptr, env) +DEF_HELPER_FLAGS_1(lookup_tb_ptr, TCG_CALL_NO_WG_SE, cptr, env) DEF_HELPER_FLAGS_1(exit_atomic, TCG_CALL_NO_WG, noreturn, env) diff --git a/include/disas/disas.h b/include/disas/disas.h index 36c33f6f19..d363e95ede 100644 --- a/include/disas/disas.h +++ b/include/disas/disas.h @@ -7,7 +7,7 @@ #include "cpu.h" /* Disassemble this for me please... (debugging). */ -void disas(FILE *out, void *code, unsigned long size); +void disas(FILE *out, const void *code, unsigned long size); void target_disas(FILE *out, CPUState *cpu, target_ulong code, target_ulong size); diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index fab573da06..2e5b4bba48 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -448,7 +448,7 @@ int probe_access_flags(CPUArchState *env, target_ulong addr, * Note: the address of search data can be obtained by adding @size to @ptr. */ struct tb_tc { - void *ptr; /* pointer to the translated code */ + const void *ptr; /* pointer to the translated code */ size_t size; }; diff --git a/include/exec/log.h b/include/exec/log.h index e02fff5de1..3c7fa65ead 100644 --- a/include/exec/log.h +++ b/include/exec/log.h @@ -56,7 +56,7 @@ static inline void log_target_disas(CPUState *cpu, target_ulong start, rcu_read_unlock(); } -static inline void log_disas(void *code, unsigned long size) +static inline void log_disas(const void *code, unsigned long size) { QemuLogFile *logfile; rcu_read_lock(); diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index ef571b6f3e..b769e868bc 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -678,6 +678,7 @@ struct TCGContext { extern TCGContext tcg_init_ctx; extern __thread TCGContext *tcg_ctx; extern void *tcg_code_gen_epilogue; +extern uintptr_t tcg_splitwx_diff; extern TCGv_env cpu_env; static inline bool in_code_gen_buffer(const void *p) @@ -691,6 +692,21 @@ static inline bool in_code_gen_buffer(const void *p) return (size_t)(p - s->code_gen_buffer) <= s->code_gen_buffer_size; } +#ifdef CONFIG_DEBUG_TCG +const void *tcg_splitwx_to_rx(void *rw); +void *tcg_splitwx_to_rw(const void *rx); +#else +static inline const void *tcg_splitwx_to_rx(void *rw) +{ + return rw ? rw + tcg_splitwx_diff : NULL; +} + +static inline void *tcg_splitwx_to_rw(const void *rx) +{ + return rx ? (void *)rx - tcg_splitwx_diff : NULL; +} +#endif + static inline size_t temp_idx(TCGTemp *ts) { ptrdiff_t n = ts - tcg_ctx->temps; @@ -1111,7 +1127,7 @@ static inline TCGLabel *arg_label(TCGArg i) * correct result. */ -static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b) +static inline ptrdiff_t tcg_ptr_byte_diff(const void *a, const void *b) { return a - b; } @@ -1125,9 +1141,9 @@ static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b) * to the destination address. */ -static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target) +static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, const void *target) { - return tcg_ptr_byte_diff(target, s->code_ptr); + return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_ptr)); } /** @@ -1233,9 +1249,9 @@ static inline unsigned get_mmuidx(TCGMemOpIdx oi) #define TB_EXIT_REQUESTED 3 #ifdef CONFIG_TCG_INTERPRETER -uintptr_t tcg_qemu_tb_exec(CPUArchState *env, void *tb_ptr); +uintptr_t tcg_qemu_tb_exec(CPUArchState *env, const void *tb_ptr); #else -typedef uintptr_t tcg_prologue_fn(CPUArchState *env, void *tb_ptr); +typedef uintptr_t tcg_prologue_fn(CPUArchState *env, const void *tb_ptr); extern tcg_prologue_fn *tcg_qemu_tb_exec; #endif diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index fa325bb3d8..f9344db283 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -161,7 +161,7 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb) uintptr_t ret; TranslationBlock *last_tb; int tb_exit; - uint8_t *tb_ptr = itb->tc.ptr; + const void *tb_ptr = itb->tc.ptr; qemu_log_mask_and_addr(CPU_LOG_EXEC, itb->pc, "Trace %d: %p [" diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index f85dfefeab..d736f4ff55 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -145,7 +145,7 @@ uint64_t HELPER(ctpop_i64)(uint64_t arg) return ctpop64(arg); } -void *HELPER(lookup_tb_ptr)(CPUArchState *env) +const void *HELPER(lookup_tb_ptr)(CPUArchState *env) { CPUState *cpu = env_cpu(env); TranslationBlock *tb; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 3f9e25fa0c..c0a3c60e1e 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -269,9 +269,9 @@ static uint8_t *encode_sleb128(uint8_t *p, target_long val) /* Decode a signed leb128 sequence at *PP; increment *PP past the decoded value. Return the decoded value. */ -static target_long decode_sleb128(uint8_t **pp) +static target_long decode_sleb128(const uint8_t **pp) { - uint8_t *p = *pp; + const uint8_t *p = *pp; target_long val = 0; int byte, shift = 0; @@ -342,7 +342,7 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, target_ulong data[TARGET_INSN_START_WORDS] = { tb->pc }; uintptr_t host_pc = (uintptr_t)tb->tc.ptr; CPUArchState *env = cpu->env_ptr; - uint8_t *p = tb->tc.ptr + tb->tc.size; + const uint8_t *p = tb->tc.ptr + tb->tc.size; int i, j, num_insns = tb->icount; #ifdef CONFIG_PROFILER TCGProfile *prof = &tcg_ctx->prof; @@ -393,7 +393,7 @@ void tb_destroy(TranslationBlock *tb) bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit) { /* - * The host_pc has to be in the region of the code buffer. + * The host_pc has to be in the rx region of the code buffer. * If it is not we will not be able to resolve it here. * The two cases where host_pc will not be correct are: * @@ -402,7 +402,7 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit) * * Either way we need return early as we can't resolve it here. */ - if (in_code_gen_buffer((const void *)host_pc)) { + if (in_code_gen_buffer((const void *)(host_pc - tcg_splitwx_diff))) { TranslationBlock *tb = tcg_tb_lookup(host_pc); if (tb) { cpu_restore_state_from_tb(cpu, tb, host_pc, will_exit); @@ -1712,7 +1712,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } gen_code_buf = tcg_ctx->code_gen_ptr; - tb->tc.ptr = gen_code_buf; + tb->tc.ptr = tcg_splitwx_to_rx(gen_code_buf); tb->pc = pc; tb->cs_base = cs_base; tb->flags = flags; @@ -1806,15 +1806,19 @@ TranslationBlock *tb_gen_code(CPUState *cpu, if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM) && qemu_log_in_addr_range(tb->pc)) { FILE *logfile = qemu_log_lock(); - int code_size, data_size = 0; + int code_size, data_size; + const tcg_target_ulong *rx_data_gen_ptr; size_t chunk_start; int insn = 0; if (tcg_ctx->data_gen_ptr) { - code_size = tcg_ctx->data_gen_ptr - tb->tc.ptr; + rx_data_gen_ptr = tcg_splitwx_to_rx(tcg_ctx->data_gen_ptr); + code_size = (const void *)rx_data_gen_ptr - tb->tc.ptr; data_size = gen_code_size - code_size; } else { + rx_data_gen_ptr = 0; code_size = gen_code_size; + data_size = 0; } /* Dump header and the first instruction */ @@ -1849,16 +1853,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu, if (data_size) { int i; qemu_log(" data: [size=%d]\n", data_size); - for (i = 0; i < data_size; i += sizeof(tcg_target_ulong)) { - if (sizeof(tcg_target_ulong) == 8) { - qemu_log("0x%08" PRIxPTR ": .quad 0x%016" PRIx64 "\n", - (uintptr_t)tcg_ctx->data_gen_ptr + i, - *(uint64_t *)(tcg_ctx->data_gen_ptr + i)); - } else { - qemu_log("0x%08" PRIxPTR ": .long 0x%08x\n", - (uintptr_t)tcg_ctx->data_gen_ptr + i, - *(uint32_t *)(tcg_ctx->data_gen_ptr + i)); - } + for (i = 0; i < data_size / sizeof(tcg_target_ulong); i++) { + qemu_log("0x%08" PRIxPTR ": .quad 0x%" TCG_PRIlx "\n", + (uintptr_t)&rx_data_gen_ptr[i], rx_data_gen_ptr[i]); } } qemu_log("\n"); diff --git a/disas.c b/disas.c index 7c18d7d2a7..de1de7be94 100644 --- a/disas.c +++ b/disas.c @@ -299,8 +299,10 @@ char *plugin_disas(CPUState *cpu, uint64_t addr, size_t size) } /* Disassemble this for me please... (debugging). */ -void disas(FILE *out, void *code, unsigned long size) +void disas(FILE *out, const void *ccode, unsigned long size) { + /* TODO: Push constness through the disas backends. */ + void *code = (void *)ccode; uintptr_t pc; int count; CPUDebug s; diff --git a/tcg/tcg.c b/tcg/tcg.c index 12f598cc18..7bf441979d 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -162,6 +162,7 @@ static TCGContext **tcg_ctxs; static unsigned int n_tcg_ctxs; TCGv_env cpu_env = 0; void *tcg_code_gen_epilogue; +uintptr_t tcg_splitwx_diff; #ifndef CONFIG_TCG_INTERPRETER tcg_prologue_fn *tcg_qemu_tb_exec; @@ -406,8 +407,9 @@ static void tcg_region_trees_init(void) } } -static struct tcg_region_tree *tc_ptr_to_region_tree(void *p) +static struct tcg_region_tree *tc_ptr_to_region_tree(const void *cp) { + void *p = tcg_splitwx_to_rw(cp); size_t region_idx; if (p < region.start_aligned) { @@ -701,6 +703,7 @@ void tcg_region_init(void) size_t region_size; size_t n_regions; size_t i; + uintptr_t splitwx_diff; n_regions = tcg_n_regions(); @@ -731,6 +734,7 @@ void tcg_region_init(void) region.end -= page_size; /* set guard pages */ + splitwx_diff = tcg_splitwx_diff; for (i = 0; i < region.n; i++) { void *start, *end; int rc; @@ -738,6 +742,10 @@ void tcg_region_init(void) tcg_region_bounds(i, &start, &end); rc = qemu_mprotect_none(end, page_size); g_assert(!rc); + if (splitwx_diff) { + rc = qemu_mprotect_none(end + splitwx_diff, page_size); + g_assert(!rc); + } } tcg_region_trees_init(); @@ -752,6 +760,29 @@ void tcg_region_init(void) #endif } +#ifdef CONFIG_DEBUG_TCG +const void *tcg_splitwx_to_rx(void *rw) +{ + /* Pass NULL pointers unchanged. */ + if (rw) { + g_assert(in_code_gen_buffer(rw)); + rw += tcg_splitwx_diff; + } + return rw; +} + +void *tcg_splitwx_to_rw(const void *rx) +{ + /* Pass NULL pointers unchanged. */ + if (rx) { + rx -= tcg_splitwx_diff; + /* Assert that we end with a pointer in the rw region. */ + g_assert(in_code_gen_buffer(rx)); + } + return (void *)rx; +} +#endif /* CONFIG_DEBUG_TCG */ + static void alloc_tcg_plugin_context(TCGContext *s) { #ifdef CONFIG_PLUGIN @@ -1061,8 +1092,15 @@ void tcg_prologue_init(TCGContext *s) s->code_buf = buf0; s->data_gen_ptr = NULL; + /* + * The region trees are not yet configured, but tcg_splitwx_to_rx + * needs the bounds for an assert. + */ + region.start = buf0; + region.end = buf0 + total_size; + #ifndef CONFIG_TCG_INTERPRETER - tcg_qemu_tb_exec = (tcg_prologue_fn *)buf0; + tcg_qemu_tb_exec = (tcg_prologue_fn *)tcg_splitwx_to_rx(buf0); #endif /* Compute a high-water mark, at which we voluntarily flush the buffer @@ -1087,7 +1125,7 @@ void tcg_prologue_init(TCGContext *s) buf1 = s->code_ptr; #ifndef CONFIG_TCG_INTERPRETER - flush_idcache_range((uintptr_t)buf0, (uintptr_t)buf0, + flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(buf0), (uintptr_t)buf0, tcg_ptr_byte_diff(buf1, buf0)); #endif @@ -4231,8 +4269,13 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) tcg_reg_alloc_start(s); - s->code_buf = tb->tc.ptr; - s->code_ptr = tb->tc.ptr; + /* + * Reset the buffer pointers when restarting after overflow. + * TODO: Move this into translate-all.c with the rest of the + * buffer management. Having only this done here is confusing. + */ + s->code_buf = tcg_splitwx_to_rw(tb->tc.ptr); + s->code_ptr = s->code_buf; #ifdef TCG_TARGET_NEED_LDST_LABELS QSIMPLEQ_INIT(&s->ldst_labels); @@ -4337,7 +4380,8 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) #ifndef CONFIG_TCG_INTERPRETER /* flush instruction cache */ - flush_idcache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_buf, + flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s->code_buf), + (uintptr_t)s->code_buf, tcg_ptr_byte_diff(s->code_ptr, s->code_buf)); #endif diff --git a/tcg/tci.c b/tcg/tci.c index cf0440445d..017887bbc9 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -481,9 +481,11 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition) * One possible operation in the pseudo code is a call to binary code. * Therefore, disable CFI checks in the interpreter function */ -uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, void *v_tb_ptr) +uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, + const void *v_tb_ptr) { - uint8_t *tb_ptr = v_tb_ptr; + /* TODO: Propagate const through this file. */ + uint8_t *tb_ptr = (uint8_t *)v_tb_ptr; tcg_target_ulong regs[TCG_TARGET_NB_REGS]; long tcg_temps[CPU_TEMP_BUF_NLONGS]; uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS); diff --git a/tcg/tcg-pool.c.inc b/tcg/tcg-pool.c.inc index 82cbcc89bd..90c2e63b7f 100644 --- a/tcg/tcg-pool.c.inc +++ b/tcg/tcg-pool.c.inc @@ -140,6 +140,8 @@ static int tcg_out_pool_finalize(TCGContext *s) for (; p != NULL; p = p->next) { size_t size = sizeof(tcg_target_ulong) * p->nlong; + uintptr_t value; + if (!l || l->nlong != p->nlong || memcmp(l->data, p->data, size)) { if (unlikely(a > s->code_gen_highwater)) { return -1; @@ -148,7 +150,9 @@ static int tcg_out_pool_finalize(TCGContext *s) a += size; l = p; } - if (!patch_reloc(p->label, p->rtype, (intptr_t)a - size, p->addend)) { + + value = (uintptr_t)tcg_splitwx_to_rx(a) - size; + if (!patch_reloc(p->label, p->rtype, value, p->addend)) { return -2; } } diff --git a/accel/tcg/trace-events b/accel/tcg/trace-events index 385b9f749b..6eefb37f5d 100644 --- a/accel/tcg/trace-events +++ b/accel/tcg/trace-events @@ -7,4 +7,4 @@ exec_tb_nocache(void *tb, uintptr_t pc) "tb:%p pc=0x%"PRIxPTR exec_tb_exit(void *last_tb, unsigned int flags) "tb:%p flags=0x%x" # translate-all.c -translate_block(void *tb, uintptr_t pc, uint8_t *tb_code) "tb:%p, pc:0x%"PRIxPTR", tb_code:%p" +translate_block(void *tb, uintptr_t pc, const void *tb_code) "tb:%p, pc:0x%"PRIxPTR", tb_code:%p" From patchwork Thu Jan 7 20:14:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358255 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp781139jai; Thu, 7 Jan 2021 12:22:25 -0800 (PST) X-Google-Smtp-Source: ABdhPJwnHWVYvSbHYZA0giUeMg0M89sCmLGbiftW2yIFGkRBTTjD4TFfnUf3uDrjPgpFvRGEI9t8 X-Received: by 2002:a25:9c83:: with SMTP id y3mr709736ybo.307.1610050945034; Thu, 07 Jan 2021 12:22:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610050945; cv=none; d=google.com; s=arc-20160816; b=aLg1IhVr0R/iCVrqPxX/W8LMd7QZsnUkxubKbidwW3xYHsG/YOaKR1cNzNLjaaGKDq ToLHZoza8m+zmOPFRXh/ODP7d5XVrJINwCBiNN9qlxP0lhXKtf+qyJ+tN2UVoEftoTMe 1z/ZAxc5iO6zI7xy6xgDBIhzVghOEiak7Xu0NsXzVxBtELLQwCcnyzllSUKhVJ9zCk94 f3tZ2gxx3BzVEPvJv8K2LWOh1Z87Kv+EGao84NZnNO/4wU9vjwTBHvBSe3t5Ziow9MRT 0QR5mCIuORE+kT3eKiNJVv4ZII2vusNOqpWdQg0LfjV3AQZPcjEKV+xxB1NalokXR7H2 R+Sw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=yHpWBji5XIjin1o+94tFD6CTmKluj6DDVpJFH1M81zM=; b=I4D+so1O2I8Cnt3LXIbpyveUwqIReKJYzRNaC7JR6eLQ2YETbzH8fie0WsU2BMt7fj xEkQ8e3fgeDi1T444mLDBjQbWoREN+CuJHBihdF4RDn6dKKLvPbiz3z5xkSO8CmM5fPp R6BDhspnQEMTGwxJZOTiqDrOH/39dNoj9pdgFHHtsMwObUUKo3rdMktmnE6/AQwTI3ZD NWP3rCV35zyg1Kw5amJQVci0lQXN2PvFAmLVYBLyc/nPtJoycr5uhhMcNw33nIi8QSkT VMQJ8yUcalT+EZVeS3O8ZJxUUyYi28gRnpazRX1ZDVAXJrpzOOVUmFwVeTJWm1hNUuDw oJXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P5DOXmM1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 13/47] tcg: Adjust TCGLabel for const Date: Thu, 7 Jan 2021 10:14:14 -1000 Message-Id: <20210107201448.1152301-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Joelle van Dyne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Change TCGLabel.u.value_ptr to const, and initialize it with tcg_splitwx_to_rx. Propagate const through tcg/host/ only as far as needed to avoid errors from the value_ptr change. Reviewed-by: Joelle van Dyne Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 2 +- tcg/tcg.c | 2 +- tcg/aarch64/tcg-target.c.inc | 2 +- tcg/arm/tcg-target.c.inc | 2 +- tcg/mips/tcg-target.c.inc | 5 +++-- tcg/ppc/tcg-target.c.inc | 4 ++-- tcg/s390/tcg-target.c.inc | 2 +- 7 files changed, 10 insertions(+), 9 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index b769e868bc..e9af279738 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -261,7 +261,7 @@ struct TCGLabel { unsigned refs : 16; union { uintptr_t value; - tcg_insn_unit *value_ptr; + const tcg_insn_unit *value_ptr; } u; QSIMPLEQ_HEAD(, TCGRelocation) relocs; QSIMPLEQ_ENTRY(TCGLabel) next; diff --git a/tcg/tcg.c b/tcg/tcg.c index 7bf441979d..325e439cb7 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -306,7 +306,7 @@ static void tcg_out_label(TCGContext *s, TCGLabel *l, tcg_insn_unit *ptr) { tcg_debug_assert(!l->has_value); l->has_value = 1; - l->u.value_ptr = ptr; + l->u.value_ptr = tcg_splitwx_to_rx(ptr); } TCGLabel *gen_new_label(void) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 76f8ae48ad..96dc9f4d0b 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1306,7 +1306,7 @@ static void tcg_out_cmp(TCGContext *s, TCGType ext, TCGReg a, } } -static inline void tcg_out_goto(TCGContext *s, tcg_insn_unit *target) +static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) { ptrdiff_t offset = target - s->code_ptr; tcg_debug_assert(offset == sextract64(offset, 0, 26)); diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 1e32bf42b8..f8f485d807 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1019,7 +1019,7 @@ static inline void tcg_out_st8(TCGContext *s, int cond, * with the code buffer limited to 16MB we wouldn't need the long case. * But we also use it for the tail-call to the qemu_ld/st helpers, which does. */ -static void tcg_out_goto(TCGContext *s, int cond, tcg_insn_unit *addr) +static void tcg_out_goto(TCGContext *s, int cond, const tcg_insn_unit *addr) { intptr_t addri = (intptr_t)addr; ptrdiff_t disp = tcg_pcrel_diff(s, addr); diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index f641105f9a..a3f838fa51 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -144,7 +144,8 @@ static tcg_insn_unit *bswap32_addr; static tcg_insn_unit *bswap32u_addr; static tcg_insn_unit *bswap64_addr; -static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, tcg_insn_unit *target) +static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, + const tcg_insn_unit *target) { /* Let the compiler perform the right-shift as part of the arithmetic. */ ptrdiff_t disp = target - (pc + 1); @@ -152,7 +153,7 @@ static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, tcg_insn_unit *target) return disp & 0xffff; } -static inline void reloc_pc16(tcg_insn_unit *pc, tcg_insn_unit *target) +static inline void reloc_pc16(tcg_insn_unit *pc, const tcg_insn_unit *target) { *pc = deposit32(*pc, 0, 16, reloc_pc16_val(pc, target)); } diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 15d5c78798..d108f01fec 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -184,7 +184,7 @@ static inline bool in_range_b(tcg_target_long target) return target == sextract64(target, 0, 26); } -static uint32_t reloc_pc24_val(tcg_insn_unit *pc, tcg_insn_unit *target) +static uint32_t reloc_pc24_val(tcg_insn_unit *pc, const tcg_insn_unit *target) { ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); tcg_debug_assert(in_range_b(disp)); @@ -201,7 +201,7 @@ static bool reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target) return false; } -static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg_insn_unit *target) +static uint16_t reloc_pc14_val(tcg_insn_unit *pc, const tcg_insn_unit *target) { ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); tcg_debug_assert(disp == (int16_t) disp); diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index ac99ccea73..1b5c4f0ab0 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -1302,7 +1302,7 @@ static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src, tcg_out_risbg(s, dest, src, 64 - len, 63, 64 - ofs, 1); } -static void tgen_gotoi(TCGContext *s, int cc, tcg_insn_unit *dest) +static void tgen_gotoi(TCGContext *s, int cc, const tcg_insn_unit *dest) { ptrdiff_t off = dest - s->code_ptr; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 14/47] tcg: Adjust tcg_out_call for const Date: Thu, 7 Jan 2021 10:14:15 -1000 Message-Id: <20210107201448.1152301-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Joelle van Dyne , =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We must change all targets at once, since all must match the declaration in tcg.c. Reviewed-by: Joelle van Dyne Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg.c | 2 +- tcg/aarch64/tcg-target.c.inc | 2 +- tcg/arm/tcg-target.c.inc | 2 +- tcg/i386/tcg-target.c.inc | 4 ++-- tcg/mips/tcg-target.c.inc | 6 +++--- tcg/ppc/tcg-target.c.inc | 8 ++++---- tcg/riscv/tcg-target.c.inc | 6 +++--- tcg/s390/tcg-target.c.inc | 2 +- tcg/sparc/tcg-target.c.inc | 4 ++-- tcg/tci/tcg-target.c.inc | 2 +- 10 files changed, 19 insertions(+), 19 deletions(-) -- 2.25.1 diff --git a/tcg/tcg.c b/tcg/tcg.c index 325e439cb7..a34d2e5bb7 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -149,7 +149,7 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2); static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, TCGReg base, intptr_t ofs); -static void tcg_out_call(TCGContext *s, tcg_insn_unit *target); +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target); static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct); #ifdef TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 96dc9f4d0b..6d8152c468 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1329,7 +1329,7 @@ static inline void tcg_out_callr(TCGContext *s, TCGReg reg) tcg_out_insn(s, 3207, BLR, reg); } -static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *target) +static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *target) { ptrdiff_t offset = target - s->code_ptr; if (offset == sextract64(offset, 0, 26)) { diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index f8f485d807..a197e6bc45 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1033,7 +1033,7 @@ static void tcg_out_goto(TCGContext *s, int cond, const tcg_insn_unit *addr) /* The call case is mostly used for helpers - so it's not unreasonable * for them to be beyond branch range */ -static void tcg_out_call(TCGContext *s, tcg_insn_unit *addr) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *addr) { intptr_t addri = (intptr_t)addr; ptrdiff_t disp = tcg_pcrel_diff(s, addr); diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index ee3a27069d..9e4053f4e7 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1600,7 +1600,7 @@ static void tcg_out_clz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1, } } -static void tcg_out_branch(TCGContext *s, int call, tcg_insn_unit *dest) +static void tcg_out_branch(TCGContext *s, int call, const tcg_insn_unit *dest) { intptr_t disp = tcg_pcrel_diff(s, dest) - 5; @@ -1619,7 +1619,7 @@ static void tcg_out_branch(TCGContext *s, int call, tcg_insn_unit *dest) } } -static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *dest) +static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest) { tcg_out_branch(s, 1, dest); } diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index a3f838fa51..6d2c369a85 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -517,7 +517,7 @@ static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, * Type jump. * Returns true if the branch was in range and the insn was emitted. */ -static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, void *target) +static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) { uintptr_t dest = (uintptr_t)target; uintptr_t from = (uintptr_t)s->code_ptr + 4; @@ -1080,7 +1080,7 @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, } } -static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail) +static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) { /* Note that the ABI requires the called function's address to be loaded into T9, even if a direct branch is in range. */ @@ -1098,7 +1098,7 @@ static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail) } } -static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) { tcg_out_call_int(s, arg, false); tcg_out_nop(s); diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index d108f01fec..38dabe40c4 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1106,7 +1106,7 @@ static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) tcg_out_zori32(s, dst, src, c, XORI, XORIS); } -static void tcg_out_b(TCGContext *s, int mask, tcg_insn_unit *target) +static void tcg_out_b(TCGContext *s, int mask, const tcg_insn_unit *target) { ptrdiff_t disp = tcg_pcrel_diff(s, target); if (in_range_b(disp)) { @@ -1762,13 +1762,13 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, } } -static void tcg_out_call(TCGContext *s, tcg_insn_unit *target) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target) { #ifdef _CALL_AIX /* Look through the descriptor. If the branch is in range, and we don't have to spend too much effort on building the toc. */ - void *tgt = ((void **)target)[0]; - uintptr_t toc = ((uintptr_t *)target)[1]; + const void *tgt = ((const void * const *)target)[0]; + uintptr_t toc = ((const uintptr_t *)target)[1]; intptr_t diff = tcg_pcrel_diff(s, tgt); if (in_range_b(diff) && toc == (uint32_t)toc) { diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 25df85b33a..90588ca2a3 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -449,7 +449,7 @@ static bool reloc_jimm20(tcg_insn_unit *code_ptr, tcg_insn_unit *target) return false; } -static bool reloc_call(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +static bool reloc_call(tcg_insn_unit *code_ptr, const tcg_insn_unit *target) { intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; int32_t lo = sextreg(offset, 0, 12); @@ -861,7 +861,7 @@ static inline void tcg_out_goto(TCGContext *s, tcg_insn_unit *target) tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, offset); } -static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail) +static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) { TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; ptrdiff_t offset = tcg_pcrel_diff(s, arg); @@ -888,7 +888,7 @@ static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail) } } -static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) { tcg_out_call_int(s, arg, false); } diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index 1b5c4f0ab0..37f4dc4cfd 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -1415,7 +1415,7 @@ static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c, tgen_branch(s, cc, l); } -static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest) { ptrdiff_t off = dest - s->code_ptr; if (off == (int32_t)off) { diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 5b3bc91b05..1a40911660 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -840,7 +840,7 @@ static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh, tcg_out_mov(s, TCG_TYPE_I64, rl, tmp); } -static void tcg_out_call_nodelay(TCGContext *s, tcg_insn_unit *dest, +static void tcg_out_call_nodelay(TCGContext *s, const tcg_insn_unit *dest, bool in_prologue) { ptrdiff_t disp = tcg_pcrel_diff(s, dest); @@ -855,7 +855,7 @@ static void tcg_out_call_nodelay(TCGContext *s, tcg_insn_unit *dest, } } -static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest) { tcg_out_call_nodelay(s, dest, false); tcg_out_nop(s); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 231b9b1775..d5a4d9d37c 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -545,7 +545,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type, old_code_ptr[1] = s->code_ptr - old_code_ptr; } -static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *arg) +static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) { uint8_t *old_code_ptr = s->code_ptr; tcg_out_op_t(s, INDEX_op_call); From patchwork Thu Jan 7 20:14:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358266 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp785505jai; Thu, 7 Jan 2021 12:29:55 -0800 (PST) X-Google-Smtp-Source: ABdhPJxXTP1HLIy+ZIXvGTGT+go5w+gCbsASnWYL0eSE/StCnWSXNsEv/1sB9lThQzr4eTu2VVEb X-Received: by 2002:a05:6902:504:: with SMTP id x4mr901148ybs.446.1610051394903; Thu, 07 Jan 2021 12:29:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610051394; cv=none; d=google.com; s=arc-20160816; b=aHlV+hlsW1l6/LfgXbeSf/kwM3NNCTjzSYrQf5kLtZZx/eT3prby7em0BZmgnd8Vnh K3GS5FbfrjbZUiMVuWtyM//ivE12GLDqcpvb+hVrcMF0nHRpGCaLMIrshdrj6jsibVQD o7K6xFM86mRWt/SKMzw1YW8pWtjgnf6NIq6VxX1nMcPFDLhzP4/YHyRbrbRUgvDrEY7U OcN03vohx2N9HnIlIic3DHY3WxF6DuSm/v4+VjvRbyue6yYZEuGa1Ju1yArwSy2rftEW 49p+b3pC1KUVwqKXHAPqM7nFVzTM17mIcCmOBu3UNGlQtSsjtRdh+MEj8UG+vXZzALGV yL0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NQliFXXfgB1CXPoiBmFHUeq1S6nzHe9RcOFk3sVmuPo=; b=R/AybL7Gd/2fAQzFOPhqKqvMd+SG23M8AAzWpEda8UZiKCzMbEzLFdYxzuS5Qbuanf RDze914Ne+DciYmOj67hB0utwFkhXiwJk5NVzJMgYm0LD0w34O5lI+dhgQXL0RqDvdjX ATGX8EgxNaGPV01WVr48FSijqcA6LJnCfTyxyuXom5WMZRFWtYMv8ovqx4kbe7oQKV8D uLgrGuWjWA2uBI6xIDx+U6IM93CedfX4h9bakMqNJT/Y7nZTox4pZ/tjd2jbnB6BDa0w 9afX0wDrFDw4izMmWp1xZK7QRn9LTt8Jx6shdy3xdv8YyLo8pXQd9bto6Y9XDi7bxUP0 2D/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RYPyOcCc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 15/47] tcg: Adjust tcg_out_label for const Date: Thu, 7 Jan 2021 10:14:16 -1000 Message-Id: <20210107201448.1152301-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Joelle van Dyne , =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Simplify the arguments to always use s->code_ptr instead of take it as an argument. That makes it easy to ensure that the value_ptr is always the rx version. Reviewed-by: Joelle van Dyne Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg.c | 6 +++--- tcg/i386/tcg-target.c.inc | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/tcg/tcg.c b/tcg/tcg.c index a34d2e5bb7..898c4bd1b6 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -302,11 +302,11 @@ static void tcg_out_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, QSIMPLEQ_INSERT_TAIL(&l->relocs, r, next); } -static void tcg_out_label(TCGContext *s, TCGLabel *l, tcg_insn_unit *ptr) +static void tcg_out_label(TCGContext *s, TCGLabel *l) { tcg_debug_assert(!l->has_value); l->has_value = 1; - l->u.value_ptr = tcg_splitwx_to_rx(ptr); + l->u.value_ptr = tcg_splitwx_to_rx(s->code_ptr); } TCGLabel *gen_new_label(void) @@ -4329,7 +4329,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) break; case INDEX_op_set_label: tcg_reg_alloc_bb_end(s, s->reserved_regs); - tcg_out_label(s, arg_label(op->args[0]), s->code_ptr); + tcg_out_label(s, arg_label(op->args[0])); break; case INDEX_op_call: tcg_reg_alloc_call(s, op); diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 9e4053f4e7..197e3006c8 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1461,7 +1461,7 @@ static void tcg_out_brcond2(TCGContext *s, const TCGArg *args, default: tcg_abort(); } - tcg_out_label(s, label_next, s->code_ptr); + tcg_out_label(s, label_next); } #endif @@ -1503,10 +1503,10 @@ static void tcg_out_setcond2(TCGContext *s, const TCGArg *args, tcg_out_movi(s, TCG_TYPE_I32, args[0], 0); tcg_out_jxx(s, JCC_JMP, label_over, 1); - tcg_out_label(s, label_true, s->code_ptr); + tcg_out_label(s, label_true); tcg_out_movi(s, TCG_TYPE_I32, args[0], 1); - tcg_out_label(s, label_over, s->code_ptr); + tcg_out_label(s, label_over); } else { /* When the destination does not overlap one of the arguments, clear the destination first, jump if cond false, and emit an @@ -1520,7 +1520,7 @@ static void tcg_out_setcond2(TCGContext *s, const TCGArg *args, tcg_out_brcond2(s, new_args, const_args+1, 1); tgen_arithi(s, ARITH_ADD, args[0], 1, 0); - tcg_out_label(s, label_over, s->code_ptr); + tcg_out_label(s, label_over); } } #endif @@ -1534,7 +1534,7 @@ static void tcg_out_cmov(TCGContext *s, TCGCond cond, int rexw, TCGLabel *over = gen_new_label(); tcg_out_jxx(s, tcg_cond_to_jcc[tcg_invert_cond(cond)], over, 1); tcg_out_mov(s, TCG_TYPE_I32, dest, v1); - tcg_out_label(s, over, s->code_ptr); + tcg_out_label(s, over); } } From patchwork Thu Jan 7 20:14:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358253 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp780927jai; Thu, 7 Jan 2021 12:22:02 -0800 (PST) X-Google-Smtp-Source: ABdhPJwjs4oQn3/s73Nng48e5s11dQv8vlC+6Vshoyp9GXhv7lA7I5D1sVpXUQdPAGK/Gzkkl5Zj X-Received: by 2002:a25:8743:: with SMTP id e3mr799945ybn.362.1610050921897; Thu, 07 Jan 2021 12:22:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610050921; cv=none; d=google.com; s=arc-20160816; b=uYACxjyHzyyLnOG9wLW7cnca3MgM9CEIQCWXOAhgxEadDIKt+MRZPgsIebYuMhMuaQ RspRa2UjelIfTeLp+qT9w4AjAI8OmqUUSouvUGapa76pWq9OkTpH+f2zj9ssEy/U+Rv3 3ICmB8PZQ7qFx2aRUHVq02e3iD1AWqcknovcoJwP3KCtyCiDFjHJR2OXEfBs2VZwJsM4 vbjZWqXoAuLpvLrBtw3FQZehWu4VfSGTod0K42kASeksUezmzgwNtL0/WCNRSxXNJdCT ToCOcr2+Ws0/NRqFdPVXWFqqk5sbq0dAhNx8bTsUOutIwzV+GXoXZRVLrBs6HQfZm2kn g8Zw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rtXLHEnFm6PYImUKUfsTMRutoZrBjCY0hpS4NqovFSw=; b=kEtbUaV+LVCi3ML9OPVW53e1H45/5NF4K6HSBIKLbOrKjWdbyP4AesVZBbdkei1kpV F+fo5kSwpXYRbKDGAxbm4xJjjarx/OcRcsuoKLxar5oWwvipGmWPOuuAFT4+ugIFmKQy mui9vTe72YgFKFe2iAZC6t5GiPT34mSArDS6CUVnRrk53YvFS428HnUtZBnccb+8bIev mfaSofcWRWoOsYmS5r4Lxw54k57UkLYdKmTGLfcdoeQ9W9a3SmrbJVlrauw/C+03wlhb DYfvU5qLNo45m4W+SO1hxyQaxiI+gcHbpC7QUiq9/lZNuBa20Ts7Pca85VwZ2HhI+hgn EyoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IDQ37mg0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 16/47] tcg: Adjust tcg_register_jit for const Date: Thu, 7 Jan 2021 10:14:17 -1000 Message-Id: <20210107201448.1152301-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Joelle van Dyne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We must change all targets at once, since all must match the declaration in tcg.c. Reviewed-by: Joelle van Dyne Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 2 +- tcg/tcg.c | 10 +++++----- tcg/aarch64/tcg-target.c.inc | 2 +- tcg/arm/tcg-target.c.inc | 2 +- tcg/i386/tcg-target.c.inc | 2 +- tcg/mips/tcg-target.c.inc | 2 +- tcg/ppc/tcg-target.c.inc | 2 +- tcg/riscv/tcg-target.c.inc | 2 +- tcg/s390/tcg-target.c.inc | 2 +- tcg/sparc/tcg-target.c.inc | 2 +- 10 files changed, 14 insertions(+), 14 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index e9af279738..e744a1ce02 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -1255,7 +1255,7 @@ typedef uintptr_t tcg_prologue_fn(CPUArchState *env, const void *tb_ptr); extern tcg_prologue_fn *tcg_qemu_tb_exec; #endif -void tcg_register_jit(void *buf, size_t buf_size); +void tcg_register_jit(const void *buf, size_t buf_size); #if TCG_TARGET_MAYBE_vec /* Return zero if the tuple (opc, type, vece) is unsupportable; diff --git a/tcg/tcg.c b/tcg/tcg.c index 898c4bd1b6..f278772512 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -97,7 +97,7 @@ typedef struct QEMU_PACKED { DebugFrameFDEHeader fde; } DebugFrameHeader; -static void tcg_register_jit_int(void *buf, size_t size, +static void tcg_register_jit_int(const void *buf, size_t size, const void *debug_frame, size_t debug_frame_size) __attribute__((unused)); @@ -1137,7 +1137,7 @@ void tcg_prologue_init(TCGContext *s) total_size -= prologue_size; s->code_gen_buffer_size = total_size; - tcg_register_jit(s->code_gen_buffer, total_size); + tcg_register_jit(tcg_splitwx_to_rx(s->code_gen_buffer), total_size); #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) { @@ -4511,7 +4511,7 @@ static int find_string(const char *strtab, const char *str) } } -static void tcg_register_jit_int(void *buf_ptr, size_t buf_size, +static void tcg_register_jit_int(const void *buf_ptr, size_t buf_size, const void *debug_frame, size_t debug_frame_size) { @@ -4713,13 +4713,13 @@ static void tcg_register_jit_int(void *buf_ptr, size_t buf_size, /* No support for the feature. Provide the entry point expected by exec.c, and implement the internal function we declared earlier. */ -static void tcg_register_jit_int(void *buf, size_t size, +static void tcg_register_jit_int(const void *buf, size_t size, const void *debug_frame, size_t debug_frame_size) { } -void tcg_register_jit(void *buf, size_t buf_size) +void tcg_register_jit(const void *buf, size_t buf_size) { } #endif /* ELF_HOST_MACHINE */ diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 6d8152c468..9ace859db3 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2964,7 +2964,7 @@ static const DebugFrame debug_frame = { } }; -void tcg_register_jit(void *buf, size_t buf_size) +void tcg_register_jit(const void *buf, size_t buf_size) { tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); } diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index a197e6bc45..9b9400f164 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2353,7 +2353,7 @@ static const DebugFrame debug_frame = { } }; -void tcg_register_jit(void *buf, size_t buf_size) +void tcg_register_jit(const void *buf, size_t buf_size) { tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); } diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 197e3006c8..d272975ff1 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -3976,7 +3976,7 @@ static const DebugFrame debug_frame = { #endif #if defined(ELF_HOST_MACHINE) -void tcg_register_jit(void *buf, size_t buf_size) +void tcg_register_jit(const void *buf, size_t buf_size) { tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); } diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 6d2c369a85..e9c8c24741 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -2703,7 +2703,7 @@ static const DebugFrame debug_frame = { } }; -void tcg_register_jit(void *buf, size_t buf_size) +void tcg_register_jit(const void *buf, size_t buf_size) { tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); } diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 38dabe40c4..a0a5bac13f 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -3847,7 +3847,7 @@ static DebugFrame debug_frame = { } }; -void tcg_register_jit(void *buf, size_t buf_size) +void tcg_register_jit(const void *buf, size_t buf_size) { uint8_t *p = &debug_frame.fde_reg_ofs[3]; int i; diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 90588ca2a3..0518595742 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1907,7 +1907,7 @@ static const DebugFrame debug_frame = { } }; -void tcg_register_jit(void *buf, size_t buf_size) +void tcg_register_jit(const void *buf, size_t buf_size) { tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); } diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index 37f4dc4cfd..1444914428 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -2620,7 +2620,7 @@ static const DebugFrame debug_frame = { } }; -void tcg_register_jit(void *buf, size_t buf_size) +void tcg_register_jit(const void *buf, size_t buf_size) { tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); } diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 1a40911660..4c81d5f1c2 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -1816,7 +1816,7 @@ static const DebugFrame debug_frame = { .fde_ret_save = { 9, 15, 31 }, /* DW_CFA_register o7, i7 */ }; -void tcg_register_jit(void *buf, size_t buf_size) +void tcg_register_jit(const void *buf, size_t buf_size) { tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); } From patchwork Thu Jan 7 20:14:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358257 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp782626jai; Thu, 7 Jan 2021 12:24:47 -0800 (PST) X-Google-Smtp-Source: ABdhPJy5xOK5GXLtoAMpFg+zfqrYPUC9bu8c00IDPwApwTPI/Pepu4ICc3RW8TU5yluDWd/KnxpU X-Received: by 2002:a25:9b81:: with SMTP id v1mr750814ybo.168.1610051087496; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 17/47] tcg: Adjust tb_target_set_jmp_target for split-wx Date: Thu, 7 Jan 2021 10:14:18 -1000 Message-Id: <20210107201448.1152301-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Joelle van Dyne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Pass both rx and rw addresses to tb_target_set_jmp_target. Reviewed-by: Joelle van Dyne Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 +- tcg/arm/tcg-target.h | 2 +- tcg/i386/tcg-target.h | 6 +++--- tcg/mips/tcg-target.h | 2 +- tcg/ppc/tcg-target.h | 2 +- tcg/riscv/tcg-target.h | 2 +- tcg/s390/tcg-target.h | 8 ++++---- tcg/sparc/tcg-target.h | 2 +- tcg/tci/tcg-target.h | 6 +++--- accel/tcg/cpu-exec.c | 4 +++- tcg/aarch64/tcg-target.c.inc | 12 ++++++------ tcg/mips/tcg-target.c.inc | 8 ++++---- tcg/ppc/tcg-target.c.inc | 16 ++++++++-------- tcg/sparc/tcg-target.c.inc | 14 +++++++------- 14 files changed, 44 insertions(+), 42 deletions(-) -- 2.25.1 diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 108a1fa969..5ec30dba25 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -149,7 +149,7 @@ typedef enum { #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 1e18fefd0e..8d1fee6327 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -136,7 +136,7 @@ enum { #define TCG_TARGET_HAS_MEMORY_BSWAP 1 /* not defined -- call should be eliminated at compile time */ -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index f3836a4d0c..b693d3692d 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -210,11 +210,11 @@ extern bool have_movbe; #define TCG_TARGET_extract_i64_valid(ofs, len) \ (((ofs) == 8 && (len) == 8) || ((ofs) + (len)) == 32) -static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, - uintptr_t jmp_addr, uintptr_t addr) +static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, + uintptr_t jmp_rw, uintptr_t addr) { /* patch the branch destination */ - qatomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4)); + qatomic_set((int32_t *)jmp_rw, addr - (jmp_rx + 4)); /* no need to flush icache explicitly */ } diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 624248b81e..c2c32fb38f 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -202,7 +202,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 301173c97e..d1339afc66 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -176,7 +176,7 @@ extern bool have_vsx; #define TCG_TARGET_HAS_bitsel_vec have_vsx #define TCG_TARGET_HAS_cmpsel_vec 0 -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 888288d54c..727c8df418 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -161,7 +161,7 @@ typedef enum { #endif /* not defined -- call should be eliminated at compile time */ -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_DEFAULT_MO (0) diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 69576f4a9a..641464eea4 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -146,12 +146,12 @@ enum { TCG_AREG0 = TCG_REG_R10, }; -static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, - uintptr_t jmp_addr, uintptr_t addr) +static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, + uintptr_t jmp_rw, uintptr_t addr) { /* patch the branch destination */ - intptr_t disp = addr - (jmp_addr - 2); - qatomic_set((int32_t *)jmp_addr, disp / 2); + intptr_t disp = addr - (jmp_rx - 2); + qatomic_set((int32_t *)jmp_rw, disp / 2); /* no need to flush icache explicitly */ } diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 9dce305253..95ab9af955 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -169,7 +169,7 @@ extern bool use_vis3_instructions; #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index e8277caee2..bb784e018e 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -199,11 +199,11 @@ void tci_disas(uint8_t opc); #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, - uintptr_t jmp_addr, uintptr_t addr) +static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, + uintptr_t jmp_rw, uintptr_t addr) { /* patch the branch destination */ - qatomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4)); + qatomic_set((int32_t *)jmp_rw, addr - (jmp_rx + 4)); /* no need to flush icache explicitly */ } diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index f9344db283..29294f2804 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -382,7 +382,9 @@ void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr) if (TCG_TARGET_HAS_direct_jump) { uintptr_t offset = tb->jmp_target_arg[n]; uintptr_t tc_ptr = (uintptr_t)tb->tc.ptr; - tb_target_set_jmp_target(tc_ptr, tc_ptr + offset, addr); + uintptr_t jmp_rx = tc_ptr + offset; + uintptr_t jmp_rw = jmp_rx - tcg_splitwx_diff; + tb_target_set_jmp_target(tc_ptr, jmp_rx, jmp_rw, addr); } else { tb->jmp_target_arg[n] = addr; } diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 9ace859db3..fea784cf75 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1340,21 +1340,21 @@ static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *target) } } -void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, - uintptr_t addr) +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, + uintptr_t jmp_rw, uintptr_t addr) { tcg_insn_unit i1, i2; TCGType rt = TCG_TYPE_I64; TCGReg rd = TCG_REG_TMP; uint64_t pair; - ptrdiff_t offset = addr - jmp_addr; + ptrdiff_t offset = addr - jmp_rx; if (offset == sextract64(offset, 0, 26)) { i1 = I3206_B | ((offset >> 2) & 0x3ffffff); i2 = NOP; } else { - offset = (addr >> 12) - (jmp_addr >> 12); + offset = (addr >> 12) - (jmp_rx >> 12); /* patch ADRP */ i1 = I3406_ADRP | (offset & 3) << 29 | (offset & 0x1ffffc) << (5 - 2) | rd; @@ -1362,8 +1362,8 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, i2 = I3401_ADDI | rt << 31 | (addr & 0xfff) << 10 | rd << 5 | rd; } pair = (uint64_t)i2 << 32 | i1; - qatomic_set((uint64_t *)jmp_addr, pair); - flush_idcache_range(jmp_addr, jmp_addr, 8); + qatomic_set((uint64_t *)jmp_rw, pair); + flush_idcache_range(jmp_rx, jmp_rw, 8); } static inline void tcg_out_goto_label(TCGContext *s, TCGLabel *l) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index e9c8c24741..52638e920c 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -2657,11 +2657,11 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ } -void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, - uintptr_t addr) +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, + uintptr_t jmp_rw, uintptr_t addr) { - qatomic_set((uint32_t *)jmp_addr, deposit32(OPC_J, 0, 26, addr >> 2)); - flush_idcache_range(jmp_addr, jmp_addr, 4); + qatomic_set((uint32_t *)jmp_rw, deposit32(OPC_J, 0, 26, addr >> 2)); + flush_idcache_range(jmp_rx, jmp_rw, 4); } typedef struct { diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index a0a5bac13f..0eb9c4ebe2 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1722,13 +1722,13 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) tcg_out32(s, insn); } -void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, - uintptr_t addr) +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, + uintptr_t jmp_rw, uintptr_t addr) { if (TCG_TARGET_REG_BITS == 64) { tcg_insn_unit i1, i2; intptr_t tb_diff = addr - tc_ptr; - intptr_t br_diff = addr - (jmp_addr + 4); + intptr_t br_diff = addr - (jmp_rx + 4); uint64_t pair; /* This does not exercise the range of the branch, but we do @@ -1752,13 +1752,13 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, /* As per the enclosing if, this is ppc64. Avoid the _Static_assert within qatomic_set that would fail to build a ppc32 host. */ - qatomic_set__nocheck((uint64_t *)jmp_addr, pair); - flush_idcache_range(jmp_addr, jmp_addr, 8); + qatomic_set__nocheck((uint64_t *)jmp_rw, pair); + flush_idcache_range(jmp_rx, jmp_rw, 8); } else { - intptr_t diff = addr - jmp_addr; + intptr_t diff = addr - jmp_rx; tcg_debug_assert(in_range_b(diff)); - qatomic_set((uint32_t *)jmp_addr, B | (diff & 0x3fffffc)); - flush_idcache_range(jmp_addr, jmp_addr, 4); + qatomic_set((uint32_t *)jmp_rw, B | (diff & 0x3fffffc)); + flush_idcache_range(jmp_rx, jmp_rw, 4); } } diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 4c81d5f1c2..d599ae27b5 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -1821,11 +1821,11 @@ void tcg_register_jit(const void *buf, size_t buf_size) tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); } -void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, - uintptr_t addr) +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, + uintptr_t jmp_rw, uintptr_t addr) { intptr_t tb_disp = addr - tc_ptr; - intptr_t br_disp = addr - jmp_addr; + intptr_t br_disp = addr - jmp_rx; tcg_insn_unit i1, i2; /* We can reach the entire address space for ILP32. @@ -1834,9 +1834,9 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, tcg_debug_assert(br_disp == (int32_t)br_disp); if (!USE_REG_TB) { - qatomic_set((uint32_t *)jmp_addr, + qatomic_set((uint32_t *)jmp_rw, deposit32(CALL, 0, 30, br_disp >> 2)); - flush_idcache_range(jmp_addr, jmp_addr, 4); + flush_idcache_range(jmp_rx, jmp_rw, 4); return; } @@ -1859,6 +1859,6 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, | INSN_IMM13((tb_disp & 0x3ff) | -0x400)); } - qatomic_set((uint64_t *)jmp_addr, deposit64(i2, 32, 32, i1)); - flush_idcache_range(jmp_addr, jmp_addr, 8); + qatomic_set((uint64_t *)jmp_rw, deposit64(i2, 32, 32, i1)); + flush_idcache_range(jmp_rx, jmp_rw, 8); } From patchwork Thu Jan 7 20:14:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358261 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp784051jai; Thu, 7 Jan 2021 12:27:22 -0800 (PST) X-Google-Smtp-Source: ABdhPJxwXvG5l2yHszNn1x01rCPdgPpNa2fkhWVxZE2tRvqQX+eOUgLHlsACrZvP/g5bDjC4KYrE X-Received: by 2002:a25:2fc3:: with SMTP id v186mr854711ybv.113.1610051242043; Thu, 07 Jan 2021 12:27:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610051242; cv=none; d=google.com; s=arc-20160816; b=BCbhnxv7cKZ3/BcLAf5DRGky+/wWAIc0cjn6QDaVmWuZwf6xU+X0Chw1Nf7jbAPlCO aGKs1MLhMWHeVVjK1ro+G6aRzNl7iX4W0UP7RwmFuntBGNKuUubPFA/CmhzgVIQQcywL tCKctPYX0zLSisOwwKTCiYtG45X9kKTkJIg0NBoQCbfSjBJExsMjom4jvbgQmH8tXduv Vk4pw7f6GX+zIauNzvYMS6E00nlJ1P1mAXZL1VOCiTZcGp467YEWfprm/msCPl8bo8KM KUizPUM+2Y1s32eie/SQATr1fOU9Yx7YQQjUPZP7HplNHd2S4sNDhbreNHEo+e5v4R1m P3OQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=E8w1jAPv5ZMwC9hUfY2h/aIQICFcgu6SGeTKeYT6t3w=; b=f1wVugfFSnt0wNK8o58AcQj3wW9OqgpmaUE99v7lWKYxNfFnvHNxSQpMknj65lJKC6 cztBMwAj9+mAXsmKM9cTeGNyqwSjb2udXnvNZll0CAwV1xf237knujsgd1506XROaGJK XObQl7b4VA9FuofwRq6gvjlLBHNsHMadKts4b3Od+Jpk3Ziohyf2lIL3tt6tUIX5e+vY kZ4ckBn6DjaZy5M7S3EGSmoOUpKxhX4n2m5CzOK5jgQgbfGY/N9tW0YK1rVgBkNACPmP mRnvw57ty6YPSAq32Vd4LFYZJVZ3k6EGAQwNSSWrzHI2vPf5JATyng/ChqxakN4aPjF6 QKvg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XUwSh5CD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 18/47] tcg: Make DisasContextBase.tb const Date: Thu, 7 Jan 2021 10:14:19 -1000 Message-Id: <20210107201448.1152301-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Joelle van Dyne , =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There is nothing within the translators that ought to be changing the TranslationBlock data, so make it const. This does not actually use the read-only copy of the data structure that exists within the rx region. Reviewed-by: Joelle van Dyne Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/gen-icount.h | 4 ++-- include/exec/translator.h | 2 +- include/tcg/tcg-op.h | 2 +- accel/tcg/translator.c | 4 ++-- target/arm/translate-a64.c | 2 +- tcg/tcg-op.c | 2 +- 6 files changed, 8 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 822c43cfd3..aa4b44354a 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -32,7 +32,7 @@ static inline void gen_io_end(void) tcg_temp_free_i32(tmp); } -static inline void gen_tb_start(TranslationBlock *tb) +static inline void gen_tb_start(const TranslationBlock *tb) { TCGv_i32 count, imm; @@ -71,7 +71,7 @@ static inline void gen_tb_start(TranslationBlock *tb) tcg_temp_free_i32(count); } -static inline void gen_tb_end(TranslationBlock *tb, int num_insns) +static inline void gen_tb_end(const TranslationBlock *tb, int num_insns) { if (tb_cflags(tb) & CF_USE_ICOUNT) { /* Update the num_insn immediate parameter now that we know diff --git a/include/exec/translator.h b/include/exec/translator.h index 638e1529c5..24232ead41 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -67,7 +67,7 @@ typedef enum DisasJumpType { * Architecture-agnostic disassembly context. */ typedef struct DisasContextBase { - TranslationBlock *tb; + const TranslationBlock *tb; target_ulong pc_first; target_ulong pc_next; DisasJumpType is_jmp; diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 5b3bdacc39..901b19f32a 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -805,7 +805,7 @@ static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, * be NULL and @idx should be 0. Otherwise, @tb should be valid and * @idx should be one of the TB_EXIT_ values. */ -void tcg_gen_exit_tb(TranslationBlock *tb, unsigned idx); +void tcg_gen_exit_tb(const TranslationBlock *tb, unsigned idx); /** * tcg_gen_goto_tb() - output goto_tb TCG operation diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index fb1e19c585..a49a794065 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -133,8 +133,8 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db, } /* The disas_log hook may use these values rather than recompute. */ - db->tb->size = db->pc_next - db->pc_first; - db->tb->icount = db->num_insns; + tb->size = db->pc_next - db->pc_first; + tb->icount = db->num_insns; #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2e3fdfdf6b..ef63edfc68 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -410,7 +410,7 @@ static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest) static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) { - TranslationBlock *tb; + const TranslationBlock *tb; tb = s->base.tb; if (use_goto_tb(s, n, dest)) { diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index af7ce91ffa..19fa8e4691 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2664,7 +2664,7 @@ void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg) /* QEMU specific operations. */ -void tcg_gen_exit_tb(TranslationBlock *tb, unsigned idx) +void tcg_gen_exit_tb(const TranslationBlock *tb, unsigned idx) { uintptr_t val = (uintptr_t)tb + idx; From patchwork Thu Jan 7 20:14:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358272 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp789071jai; Thu, 7 Jan 2021 12:35:37 -0800 (PST) X-Google-Smtp-Source: ABdhPJyppAPP/Pz4yfa5xvD0DPXyk7Y1WTEM/TRZ3aX/BnAHS/AkpLOl9npHfits0Rl+axN70f2M X-Received: by 2002:a25:dce:: with SMTP id 197mr969264ybn.52.1610051737672; Thu, 07 Jan 2021 12:35:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610051737; cv=none; d=google.com; s=arc-20160816; b=xKtRnvRYQk2KaArPOOoBMFHo98BzBh/4T3n1mhkJBoSvAQ3Y7PmeN3I4FdGV7a7yPK MXAIkMFo8CjfC54rv5WU/ftKkCz+K0D0CwOSmq/ibJrM5bl2jQm1K2bipgV4raXH0jFu ENhnHuXe19Ljo18VbFTJ39cOv+4OyKqBx65mEsg9nriMqWY3uQTCq5p9f6gcje0390bi R8edWMdqp4PV0EQWu0Hf493JrPzLhx/+vPO5Vpk21iVjAg9kTTklUTEFrT1sjcWo0ll1 Pq7Wg2IOycIbzQ7WTRYLdz7oPw+IkFB/R9xOpMbMLAEZaTroVFm9xp9tKR5mYWtBYeO/ PQVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=sunWAzJe6zr/hqJZSTqg1lWjV1jgJ2mUk5ECH6sRN4M=; b=JvFcSOvKfe2YaRXQfKiVC2EhoJS71OLj63iIj2Wxova0mJVB8Jo5bQcJ66rde2/cKe 0FY3G+/o+8mbh4mEvB+YhKG8nBFTnjHraLu92uWDN49GOuuDe4sxxtvAiG6ugJDba9fv /mkoTD34FHGLQuvjYhkEYIqCHvCpQ6beUahhQtn/CXuWrpPxYSWwbTkZgaxyRca73tCS Rr4jkdyWEvefpSKWXJSK1iS1TBhugfkbz1bK8Li4UI91vL32ROZ/YfOqpPvO74S1K0Av nGbpbFaKRMMJ81xFbASOeS8k+AicgxdNRPXDHun6xAg6gpPpiqnU53V3m+WBJr9ekC7W LIww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iitJNpPu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 19/47] tcg: Make tb arg to synchronize_from_tb const Date: Thu, 7 Jan 2021 10:14:20 -1000 Message-Id: <20210107201448.1152301-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Joelle van Dyne , =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There is nothing within the translators that ought to be changing the TranslationBlock data, so make it const. This does not actually use the read-only copy of the data structure that exists within the rx region. Reviewed-by: Joelle van Dyne Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 3 ++- target/arm/cpu.c | 3 ++- target/avr/cpu.c | 3 ++- target/hppa/cpu.c | 3 ++- target/i386/tcg/tcg-cpu.c | 3 ++- target/microblaze/cpu.c | 3 ++- target/mips/cpu.c | 3 ++- target/riscv/cpu.c | 3 ++- target/rx/cpu.c | 3 ++- target/sh4/cpu.c | 3 ++- target/sparc/cpu.c | 3 ++- target/tricore/cpu.c | 2 +- 12 files changed, 23 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 8e7552910d..140fa32a5e 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -189,7 +189,8 @@ struct CPUClass { void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); - void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb); + void (*synchronize_from_tb)(CPUState *cpu, + const struct TranslationBlock *tb); bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d6188f6566..62e319eb6a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -54,7 +54,8 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) } } -static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +static void arm_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 5d9c4ad5bf..6f3d5a9e4a 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -41,7 +41,8 @@ static bool avr_cpu_has_work(CPUState *cs) && cpu_interrupts_enabled(env); } -static void avr_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +static void avr_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { AVRCPU *cpu = AVR_CPU(cs); CPUAVRState *env = &cpu->env; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 71b6aca45d..e28f047d10 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -35,7 +35,8 @@ static void hppa_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.iaoq_b = value + 4; } -static void hppa_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +static void hppa_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { HPPACPU *cpu = HPPA_CPU(cs); diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 628dd29fe7..4fa013720e 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -49,7 +49,8 @@ static void x86_cpu_exec_exit(CPUState *cs) env->eflags = cpu_compute_eflags(env); } -static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +static void x86_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { X86CPU *cpu = X86_CPU(cs); diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 9b2482159d..c8e754cfb1 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -83,7 +83,8 @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.iflags = 0; } -static void mb_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +static void mb_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 2283214c87..b2864d67d7 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -47,7 +47,8 @@ static void mips_cpu_set_pc(CPUState *cs, vaddr value) } } -static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +static void mips_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = &cpu->env; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 254cd83f8b..8227d7aea9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -314,7 +314,8 @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value) env->pc = value; } -static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +static void riscv_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 23ee17a701..2bb14144a7 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -33,7 +33,8 @@ static void rx_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc = value; } -static void rx_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +static void rx_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { RXCPU *cpu = RX_CPU(cs); diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 3c68021c56..1e0f05a15b 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -34,7 +34,8 @@ static void superh_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc = value; } -static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +static void superh_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { SuperHCPU *cpu = SUPERH_CPU(cs); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index d8a8bb1dda..6f14e370ed 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -691,7 +691,8 @@ static void sparc_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.npc = value + 4; } -static void sparc_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +static void sparc_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { SPARCCPU *cpu = SPARC_CPU(cs); diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 2f2e5b029f..4bff1d4718 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -42,7 +42,7 @@ static void tricore_cpu_set_pc(CPUState *cs, vaddr value) } static void tricore_cpu_synchronize_from_tb(CPUState *cs, - TranslationBlock *tb) + const TranslationBlock *tb) { TriCoreCPU *cpu = TRICORE_CPU(cs); CPUTriCoreState *env = &cpu->env; From patchwork Thu Jan 7 20:14:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358259 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp782832jai; Thu, 7 Jan 2021 12:25:11 -0800 (PST) X-Google-Smtp-Source: ABdhPJwvmEpRy7iem7n8sTwWKi0npAXFOhkVnNIaiVfdWLU7RQAL53iZj7Lnrzm+3h2qGW9bLPTs X-Received: by 2002:a05:6902:6af:: with SMTP id j15mr888469ybt.17.1610051111590; Thu, 07 Jan 2021 12:25:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610051111; cv=none; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 20/47] tcg: Use Error with alloc_code_gen_buffer Date: Thu, 7 Jan 2021 10:14:21 -1000 Message-Id: <20210107201448.1152301-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Joelle van Dyne , =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Report better error messages than just "could not allocate". Let alloc_code_gen_buffer set ctx->code_gen_buffer_size and ctx->code_gen_buffer, and simply return bool. Reviewed-by: Joelle van Dyne Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 60 ++++++++++++++++++++++----------------- 1 file changed, 34 insertions(+), 26 deletions(-) -- 2.25.1 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index c0a3c60e1e..ae87b2342a 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -59,6 +59,7 @@ #include "sysemu/cpus.h" #include "sysemu/cpu-timers.h" #include "sysemu/tcg.h" +#include "qapi/error.h" /* #define DEBUG_TB_INVALIDATE */ /* #define DEBUG_TB_FLUSH */ @@ -963,7 +964,7 @@ static void page_lock_pair(PageDesc **ret_p1, tb_page_addr_t phys1, (DEFAULT_CODE_GEN_BUFFER_SIZE_1 < MAX_CODE_GEN_BUFFER_SIZE \ ? DEFAULT_CODE_GEN_BUFFER_SIZE_1 : MAX_CODE_GEN_BUFFER_SIZE) -static inline size_t size_code_gen_buffer(size_t tb_size) +static size_t size_code_gen_buffer(size_t tb_size) { /* Size the buffer. */ if (tb_size == 0) { @@ -1014,7 +1015,7 @@ static inline void *split_cross_256mb(void *buf1, size_t size1) static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] __attribute__((aligned(CODE_GEN_ALIGN))); -static inline void *alloc_code_gen_buffer(void) +static bool alloc_code_gen_buffer(size_t tb_size, Error **errp) { void *buf = static_code_gen_buffer; void *end = static_code_gen_buffer + sizeof(static_code_gen_buffer); @@ -1027,9 +1028,8 @@ static inline void *alloc_code_gen_buffer(void) size = end - buf; /* Honor a command-line option limiting the size of the buffer. */ - if (size > tcg_ctx->code_gen_buffer_size) { - size = QEMU_ALIGN_DOWN(tcg_ctx->code_gen_buffer_size, - qemu_real_host_page_size); + if (size > tb_size) { + size = QEMU_ALIGN_DOWN(tb_size, qemu_real_host_page_size); } tcg_ctx->code_gen_buffer_size = size; @@ -1041,31 +1041,43 @@ static inline void *alloc_code_gen_buffer(void) #endif if (qemu_mprotect_rwx(buf, size)) { - abort(); + error_setg_errno(errp, errno, "mprotect of jit buffer"); + return false; } qemu_madvise(buf, size, QEMU_MADV_HUGEPAGE); - return buf; + tcg_ctx->code_gen_buffer = buf; + return true; } #elif defined(_WIN32) -static inline void *alloc_code_gen_buffer(void) +static bool alloc_code_gen_buffer(size_t size, Error **errp) { - size_t size = tcg_ctx->code_gen_buffer_size; - return VirtualAlloc(NULL, size, MEM_RESERVE | MEM_COMMIT, - PAGE_EXECUTE_READWRITE); + void *buf = VirtualAlloc(NULL, size, MEM_RESERVE | MEM_COMMIT, + PAGE_EXECUTE_READWRITE); + if (buf == NULL) { + error_setg_win32(errp, GetLastError(), + "allocate %zu bytes for jit buffer", size); + return false; + } + + tcg_ctx->code_gen_buffer = buf; + tcg_ctx->code_gen_buffer_size = size; + return true; } #else -static inline void *alloc_code_gen_buffer(void) +static bool alloc_code_gen_buffer(size_t size, Error **errp) { int prot = PROT_WRITE | PROT_READ | PROT_EXEC; int flags = MAP_PRIVATE | MAP_ANONYMOUS; - size_t size = tcg_ctx->code_gen_buffer_size; void *buf; buf = mmap(NULL, size, prot, flags, -1, 0); if (buf == MAP_FAILED) { - return NULL; + error_setg_errno(errp, errno, + "allocate %zu bytes for jit buffer", size); + return false; } + tcg_ctx->code_gen_buffer_size = size; #ifdef __mips__ if (cross_256mb(buf, size)) { @@ -1104,20 +1116,11 @@ static inline void *alloc_code_gen_buffer(void) /* Request large pages for the buffer. */ qemu_madvise(buf, size, QEMU_MADV_HUGEPAGE); - return buf; + tcg_ctx->code_gen_buffer = buf; + return true; } #endif /* USE_STATIC_CODE_GEN_BUFFER, WIN32, POSIX */ -static inline void code_gen_alloc(size_t tb_size) -{ - tcg_ctx->code_gen_buffer_size = size_code_gen_buffer(tb_size); - tcg_ctx->code_gen_buffer = alloc_code_gen_buffer(); - if (tcg_ctx->code_gen_buffer == NULL) { - fprintf(stderr, "Could not allocate dynamic translator buffer\n"); - exit(1); - } -} - static bool tb_cmp(const void *ap, const void *bp) { const TranslationBlock *a = ap; @@ -1144,11 +1147,16 @@ static void tb_htable_init(void) size. */ void tcg_exec_init(unsigned long tb_size) { + bool ok; + tcg_allowed = true; cpu_gen_init(); page_init(); tb_htable_init(); - code_gen_alloc(tb_size); + + ok = alloc_code_gen_buffer(size_code_gen_buffer(tb_size), &error_fatal); + assert(ok); + #if defined(CONFIG_SOFTMMU) /* There's no guest base to take into account, so go ahead and initialize the prologue now. */ From patchwork Thu Jan 7 20:14:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358275 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp789385jai; Thu, 7 Jan 2021 12:36:13 -0800 (PST) X-Google-Smtp-Source: ABdhPJwiIIbKffCQxLhuCTZXpGtrj5Iltemc5YD5cGNkNBSbmAXYm3I5OCfv/2TzMYapHS+fqrJ0 X-Received: by 2002:a25:9b45:: with SMTP id u5mr806573ybo.331.1610051773400; Thu, 07 Jan 2021 12:36:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 21/47] tcg: Add --accel tcg,split-wx property Date: Thu, 7 Jan 2021 10:14:22 -1000 Message-Id: <20210107201448.1152301-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Joelle van Dyne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Plumb the value through to alloc_code_gen_buffer. This is not supported by any os or tcg backend, so for now enabling it will result in an error. Reviewed-by: Joelle van Dyne Signed-off-by: Richard Henderson --- include/sysemu/tcg.h | 3 ++- tcg/aarch64/tcg-target.h | 1 + tcg/arm/tcg-target.h | 1 + tcg/i386/tcg-target.h | 1 + tcg/mips/tcg-target.h | 1 + tcg/ppc/tcg-target.h | 1 + tcg/riscv/tcg-target.h | 1 + tcg/s390/tcg-target.h | 1 + tcg/sparc/tcg-target.h | 1 + tcg/tci/tcg-target.h | 1 + accel/tcg/tcg-all.c | 26 +++++++++++++++++++++++++- accel/tcg/translate-all.c | 35 +++++++++++++++++++++++++++-------- bsd-user/main.c | 2 +- linux-user/main.c | 2 +- qemu-options.hx | 7 +++++++ 15 files changed, 72 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h index d9d3ca8559..00349fb18a 100644 --- a/include/sysemu/tcg.h +++ b/include/sysemu/tcg.h @@ -8,7 +8,8 @@ #ifndef SYSEMU_TCG_H #define SYSEMU_TCG_H -void tcg_exec_init(unsigned long tb_size); +void tcg_exec_init(unsigned long tb_size, int splitwx); + #ifdef CONFIG_TCG extern bool tcg_allowed; #define tcg_enabled() (tcg_allowed) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 5ec30dba25..23bf87db3d 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -155,5 +155,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_SUPPORT_MIRROR 0 #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 8d1fee6327..494837d128 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -142,5 +142,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_SUPPORT_MIRROR 0 #endif diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index b693d3692d..73aa45a665 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -235,5 +235,6 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_SUPPORT_MIRROR 0 #endif diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index c2c32fb38f..fbfe775fb4 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -201,6 +201,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 +#define TCG_TARGET_SUPPORT_MIRROR 0 void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index d1339afc66..ba61a31b3e 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -185,5 +185,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_SUPPORT_MIRROR 0 #endif diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 727c8df418..6263af4dd1 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -171,5 +171,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS #define TCG_TARGET_HAS_MEMORY_BSWAP 0 +#define TCG_TARGET_SUPPORT_MIRROR 0 #endif diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 641464eea4..b8f4296e4b 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -159,5 +159,6 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_SUPPORT_MIRROR 0 #endif diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 95ab9af955..6f6cefaa15 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -172,5 +172,6 @@ extern bool use_vis3_instructions; void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_SUPPORT_MIRROR 0 #endif diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index bb784e018e..d8c78d1dc7 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -198,6 +198,7 @@ void tci_disas(uint8_t opc); #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 +#define TCG_TARGET_SUPPORT_MIRROR 0 static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, uintptr_t jmp_rw, uintptr_t addr) diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 1ac0b76515..2eea8c32ee 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -38,6 +38,7 @@ struct TCGState { AccelState parent_obj; bool mttcg_enabled; + int splitwx_enabled; unsigned long tb_size; }; typedef struct TCGState TCGState; @@ -94,6 +95,13 @@ static void tcg_accel_instance_init(Object *obj) TCGState *s = TCG_STATE(obj); s->mttcg_enabled = default_mttcg_enabled(); + + /* If debugging enabled, default "auto on", otherwise off. */ +#ifdef CONFIG_DEBUG_TCG + s->splitwx_enabled = -1; +#else + s->splitwx_enabled = 0; +#endif } bool mttcg_enabled; @@ -102,7 +110,7 @@ static int tcg_init(MachineState *ms) { TCGState *s = TCG_STATE(current_accel()); - tcg_exec_init(s->tb_size * 1024 * 1024); + tcg_exec_init(s->tb_size * 1024 * 1024, s->splitwx_enabled); mttcg_enabled = s->mttcg_enabled; /* @@ -179,6 +187,18 @@ static void tcg_set_tb_size(Object *obj, Visitor *v, s->tb_size = value; } +static bool tcg_get_splitwx(Object *obj, Error **errp) +{ + TCGState *s = TCG_STATE(obj); + return s->splitwx_enabled; +} + +static void tcg_set_splitwx(Object *obj, bool value, Error **errp) +{ + TCGState *s = TCG_STATE(obj); + s->splitwx_enabled = value; +} + static void tcg_accel_class_init(ObjectClass *oc, void *data) { AccelClass *ac = ACCEL_CLASS(oc); @@ -196,6 +216,10 @@ static void tcg_accel_class_init(ObjectClass *oc, void *data) object_class_property_set_description(oc, "tb-size", "TCG translation block cache size"); + object_class_property_add_bool(oc, "split-wx", + tcg_get_splitwx, tcg_set_splitwx); + object_class_property_set_description(oc, "split-wx", + "Map jit pages into separate RW and RX regions"); } static const TypeInfo tcg_accel_type = { diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index ae87b2342a..022f9c743d 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1015,13 +1015,19 @@ static inline void *split_cross_256mb(void *buf1, size_t size1) static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] __attribute__((aligned(CODE_GEN_ALIGN))); -static bool alloc_code_gen_buffer(size_t tb_size, Error **errp) +static bool alloc_code_gen_buffer(size_t tb_size, int splitwx, Error **errp) { - void *buf = static_code_gen_buffer; - void *end = static_code_gen_buffer + sizeof(static_code_gen_buffer); + void *buf, *end; size_t size; + if (splitwx > 0) { + error_setg(errp, "jit split-wx not supported"); + return false; + } + /* page-align the beginning and end of the buffer */ + buf = static_code_gen_buffer; + end = static_code_gen_buffer + sizeof(static_code_gen_buffer); buf = QEMU_ALIGN_PTR_UP(buf, qemu_real_host_page_size); end = QEMU_ALIGN_PTR_DOWN(end, qemu_real_host_page_size); @@ -1050,9 +1056,16 @@ static bool alloc_code_gen_buffer(size_t tb_size, Error **errp) return true; } #elif defined(_WIN32) -static bool alloc_code_gen_buffer(size_t size, Error **errp) +static bool alloc_code_gen_buffer(size_t size, int splitwx, Error **errp) { - void *buf = VirtualAlloc(NULL, size, MEM_RESERVE | MEM_COMMIT, + void *buf; + + if (splitwx > 0) { + error_setg(errp, "jit split-wx not supported"); + return false; + } + + buf = VirtualAlloc(NULL, size, MEM_RESERVE | MEM_COMMIT, PAGE_EXECUTE_READWRITE); if (buf == NULL) { error_setg_win32(errp, GetLastError(), @@ -1065,12 +1078,17 @@ static bool alloc_code_gen_buffer(size_t size, Error **errp) return true; } #else -static bool alloc_code_gen_buffer(size_t size, Error **errp) +static bool alloc_code_gen_buffer(size_t size, int splitwx, Error **errp) { int prot = PROT_WRITE | PROT_READ | PROT_EXEC; int flags = MAP_PRIVATE | MAP_ANONYMOUS; void *buf; + if (splitwx > 0) { + error_setg(errp, "jit split-wx not supported"); + return false; + } + buf = mmap(NULL, size, prot, flags, -1, 0); if (buf == MAP_FAILED) { error_setg_errno(errp, errno, @@ -1145,7 +1163,7 @@ static void tb_htable_init(void) /* Must be called before using the QEMU cpus. 'tb_size' is the size (in bytes) allocated to the translation buffer. Zero means default size. */ -void tcg_exec_init(unsigned long tb_size) +void tcg_exec_init(unsigned long tb_size, int splitwx) { bool ok; @@ -1154,7 +1172,8 @@ void tcg_exec_init(unsigned long tb_size) page_init(); tb_htable_init(); - ok = alloc_code_gen_buffer(size_code_gen_buffer(tb_size), &error_fatal); + ok = alloc_code_gen_buffer(size_code_gen_buffer(tb_size), + splitwx, &error_fatal); assert(ok); #if defined(CONFIG_SOFTMMU) diff --git a/bsd-user/main.c b/bsd-user/main.c index 9c700c6234..65163e1396 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -909,7 +909,7 @@ int main(int argc, char **argv) } /* init tcg before creating CPUs and to get qemu_host_page_size */ - tcg_exec_init(0); + tcg_exec_init(0, false); cpu_type = parse_cpu_option(cpu_model); cpu = cpu_create(cpu_type); diff --git a/linux-user/main.c b/linux-user/main.c index 750a01118f..bb4e55e8fc 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -701,7 +701,7 @@ int main(int argc, char **argv, char **envp) cpu_type = parse_cpu_option(cpu_model); /* init tcg before creating CPUs and to get qemu_host_page_size */ - tcg_exec_init(0); + tcg_exec_init(0, false); cpu = cpu_create(cpu_type); env = cpu->env_ptr; diff --git a/qemu-options.hx b/qemu-options.hx index 459c916d3d..1698a0c751 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -115,6 +115,7 @@ DEF("accel", HAS_ARG, QEMU_OPTION_accel, " igd-passthru=on|off (enable Xen integrated Intel graphics passthrough, default=off)\n" " kernel-irqchip=on|off|split controls accelerated irqchip support (default=on)\n" " kvm-shadow-mem=size of KVM shadow MMU in bytes\n" + " split-wx=on|off (enable TCG split w^x mapping)\n" " tb-size=n (TCG translation block cache size)\n" " thread=single|multi (enable multi-threaded TCG)\n", QEMU_ARCH_ALL) SRST @@ -140,6 +141,12 @@ SRST ``kvm-shadow-mem=size`` Defines the size of the KVM shadow MMU. + ``split-wx=on|off`` + Controls the use of split w^x mapping for the TCG code generation + buffer. Some operating systems require this to be enabled, and in + such a case this will default on. On other operating systems, this + will default off, but one may enable this for testing or debugging. + ``tb-size=n`` Controls the size (in MiB) of the TCG translation block cache. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 22/47] accel/tcg: Support split-wx for linux with memfd Date: Thu, 7 Jan 2021 10:14:23 -1000 Message-Id: <20210107201448.1152301-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Joelle van Dyne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We cannot use a real temp file, because we would need to find a filesystem that does not have noexec enabled. However, a memfd is not associated with any filesystem. Reviewed-by: Joelle van Dyne Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 84 +++++++++++++++++++++++++++++++++++---- 1 file changed, 76 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 022f9c743d..3b6804578d 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1078,17 +1078,11 @@ static bool alloc_code_gen_buffer(size_t size, int splitwx, Error **errp) return true; } #else -static bool alloc_code_gen_buffer(size_t size, int splitwx, Error **errp) +static bool alloc_code_gen_buffer_anon(size_t size, int prot, + int flags, Error **errp) { - int prot = PROT_WRITE | PROT_READ | PROT_EXEC; - int flags = MAP_PRIVATE | MAP_ANONYMOUS; void *buf; - if (splitwx > 0) { - error_setg(errp, "jit split-wx not supported"); - return false; - } - buf = mmap(NULL, size, prot, flags, -1, 0); if (buf == MAP_FAILED) { error_setg_errno(errp, errno, @@ -1137,6 +1131,80 @@ static bool alloc_code_gen_buffer(size_t size, int splitwx, Error **errp) tcg_ctx->code_gen_buffer = buf; return true; } + +#ifdef CONFIG_POSIX +#include "qemu/memfd.h" + +static bool alloc_code_gen_buffer_splitwx_memfd(size_t size, Error **errp) +{ + void *buf_rw, *buf_rx; + int fd = -1; + + buf_rw = qemu_memfd_alloc("tcg-jit", size, 0, &fd, errp); + if (buf_rw == NULL) { + return false; + } + + buf_rx = mmap(NULL, size, PROT_READ | PROT_EXEC, MAP_SHARED, fd, 0); + if (buf_rx == MAP_FAILED) { + error_setg_errno(errp, errno, + "failed to map shared memory for execute"); + munmap(buf_rw, size); + close(fd); + return false; + } + close(fd); + + tcg_ctx->code_gen_buffer = buf_rw; + tcg_ctx->code_gen_buffer_size = size; + tcg_splitwx_diff = buf_rx - buf_rw; + + /* Request large pages for the buffer and the splitwx. */ + qemu_madvise(buf_rw, size, QEMU_MADV_HUGEPAGE); + qemu_madvise(buf_rx, size, QEMU_MADV_HUGEPAGE); + return true; +} +#endif /* CONFIG_POSIX */ + +static bool alloc_code_gen_buffer_splitwx(size_t size, Error **errp) +{ + if (TCG_TARGET_SUPPORT_MIRROR) { +#ifdef CONFIG_POSIX + return alloc_code_gen_buffer_splitwx_memfd(size, errp); +#endif + } + error_setg(errp, "jit split-wx not supported"); + return false; +} + +static bool alloc_code_gen_buffer(size_t size, int splitwx, Error **errp) +{ + ERRP_GUARD(); + int prot, flags; + + if (splitwx) { + if (alloc_code_gen_buffer_splitwx(size, errp)) { + return true; + } + /* + * If splitwx force-on (1), fail; + * if splitwx default-on (-1), fall through to splitwx off. + */ + if (splitwx > 0) { + return false; + } + error_free_or_abort(errp); + } + + prot = PROT_READ | PROT_WRITE | PROT_EXEC; + flags = MAP_PRIVATE | MAP_ANONYMOUS; +#ifdef CONFIG_TCG_INTERPRETER + /* The tcg interpreter does not need execute permission. */ + prot = PROT_READ | PROT_WRITE; +#endif + + return alloc_code_gen_buffer_anon(size, prot, flags, errp); +} #endif /* USE_STATIC_CODE_GEN_BUFFER, WIN32, POSIX */ static bool tb_cmp(const void *ap, const void *bp) From patchwork Thu Jan 7 20:14:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358271 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp787508jai; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 23/47] accel/tcg: Support split-wx for darwin/iOS with vm_remap Date: Thu, 7 Jan 2021 10:14:24 -1000 Message-Id: <20210107201448.1152301-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Joelle van Dyne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cribbed from code posted by Joelle van Dyne , and rearranged to a cleaner structure. Reviewed-by: Joelle van Dyne Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 67 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) -- 2.25.1 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 3b6804578d..c37718db4d 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1166,9 +1166,71 @@ static bool alloc_code_gen_buffer_splitwx_memfd(size_t size, Error **errp) } #endif /* CONFIG_POSIX */ +#ifdef CONFIG_DARWIN +#include + +extern kern_return_t mach_vm_remap(vm_map_t target_task, + mach_vm_address_t *target_address, + mach_vm_size_t size, + mach_vm_offset_t mask, + int flags, + vm_map_t src_task, + mach_vm_address_t src_address, + boolean_t copy, + vm_prot_t *cur_protection, + vm_prot_t *max_protection, + vm_inherit_t inheritance); + +static bool alloc_code_gen_buffer_splitwx_vmremap(size_t size, Error **errp) +{ + kern_return_t ret; + mach_vm_address_t buf_rw, buf_rx; + vm_prot_t cur_prot, max_prot; + + /* Map the read-write portion via normal anon memory. */ + if (!alloc_code_gen_buffer_anon(size, PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANONYMOUS, errp)) { + return false; + } + + buf_rw = (mach_vm_address_t)tcg_ctx->code_gen_buffer; + buf_rx = 0; + ret = mach_vm_remap(mach_task_self(), + &buf_rx, + size, + 0, + VM_FLAGS_ANYWHERE, + mach_task_self(), + buf_rw, + false, + &cur_prot, + &max_prot, + VM_INHERIT_NONE); + if (ret != KERN_SUCCESS) { + /* TODO: Convert "ret" to a human readable error message. */ + error_setg(errp, "vm_remap for jit splitwx failed"); + munmap((void *)buf_rw, size); + return false; + } + + if (mprotect((void *)buf_rx, size, PROT_READ | PROT_EXEC) != 0) { + error_setg_errno(errp, errno, "mprotect for jit splitwx"); + munmap((void *)buf_rx, size); + munmap((void *)buf_rw, size); + return false; + } + + tcg_splitwx_diff = buf_rx - buf_rw; + return true; +} +#endif /* CONFIG_DARWIN */ + static bool alloc_code_gen_buffer_splitwx(size_t size, Error **errp) { if (TCG_TARGET_SUPPORT_MIRROR) { +#ifdef CONFIG_DARWIN + return alloc_code_gen_buffer_splitwx_vmremap(size, errp); +#endif #ifdef CONFIG_POSIX return alloc_code_gen_buffer_splitwx_memfd(size, errp); #endif @@ -1201,6 +1263,11 @@ static bool alloc_code_gen_buffer(size_t size, int splitwx, Error **errp) #ifdef CONFIG_TCG_INTERPRETER /* The tcg interpreter does not need execute permission. */ prot = PROT_READ | PROT_WRITE; +#elif defined(CONFIG_DARWIN) + /* Applicable to both iOS and macOS (Apple Silicon). */ + if (!splitwx) { + flags |= MAP_JIT; + } #endif return alloc_code_gen_buffer_anon(size, prot, flags, errp); From patchwork Thu Jan 7 20:14:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358270 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp787372jai; Thu, 7 Jan 2021 12:32:48 -0800 (PST) X-Google-Smtp-Source: ABdhPJxaaywFkZSwTxNZ+ClHdsEEzdd92IAuQQ0nAZfIPvWf7jxCfpun6JlvWmtM9ZwF67PKhen4 X-Received: by 2002:a25:4d7:: with SMTP id 206mr962259ybe.306.1610051568577; Thu, 07 Jan 2021 12:32:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610051568; cv=none; d=google.com; s=arc-20160816; b=IhBZyBFeBHgguoFdg5kHmNXxJGM6iyqxBk9/dqr6QtsyXAaqdUcv9kbqXnozkDeREH KxJUIz/pwn8OmrCUrUxey4jw29h6wbFKk4J0WYaG5Z8VbdablJkHsELXJnohDP/KqBy7 FT1yZolIvO0I1v8TRHJqZeasHFejt5L47Bf6bo8wJshRXkmo2NSjNi79ib4jKMSRo1r3 Ne8NsXNitGlgmZjqsrftxZSBKQLl1FcRHmSeqnKSDVhegGU0uQzstzjsqHR8kv6vXOsI Numtda29VFpuj3gr4nZoCxQ0pSsd6IBQYT0DMCzNJvlNm2nMyomCGS5LvVI1Xb+GfXNt i+pQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mXWHgXR1rPfUzE1DKblo9sXuzDnTJrCai9FRrekni9s=; b=akhBGMT+2yzz9yaOL7nJThBFTqjfhNl8dHVTTgREaTZsPqWKJQ9zzw/3dxgkmbO+W2 SwfWjV0G3qK/95ndfNlCyLS5/jJhIOdcgEDrRYTplX3Q4/5sXpy/NWvDGDH2fLbFv+or 48SY9E+2/s40F2ec1QWZdJF5zmTjcHB2ky+rzkIHnIgMrjcr0ahX9RU/qOJZ3ok/Wwe+ LRUYpyTAVp0t/T56fb1b5tml+PFJFX/xEZRILXidM66YfvHGmlfKFcFPmNLyibcakSe2 +yj4QG8mTbcHm+JCzbfl0/NqC/aWZzrKRXGE0wEIQkS0zSXi4pD6G2gtJYJRHwe8qo3k S8yg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EErs6906; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 24/47] tcg: Return the TB pointer from the rx region from exit_tb Date: Thu, 7 Jan 2021 10:14:25 -1000 Message-Id: <20210107201448.1152301-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Joelle van Dyne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This produces a small pc-relative displacement within the generated code to the TB structure that preceeds it. Reviewed-by: Joelle van Dyne Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 35 +++++++++++++++++++++-------------- tcg/tcg-op.c | 13 ++++++++++++- 2 files changed, 33 insertions(+), 15 deletions(-) -- 2.25.1 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 29294f2804..e0df9b6a1d 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -154,13 +154,12 @@ static void init_delay_params(SyncClocks *sc, const CPUState *cpu) * TCG is not considered a security-sensitive part of QEMU so this does not * affect the impact of CFI in environment with high security requirements */ -QEMU_DISABLE_CFI -static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb) +static inline TranslationBlock * QEMU_DISABLE_CFI +cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit) { CPUArchState *env = cpu->env_ptr; uintptr_t ret; TranslationBlock *last_tb; - int tb_exit; const void *tb_ptr = itb->tc.ptr; qemu_log_mask_and_addr(CPU_LOG_EXEC, itb->pc, @@ -188,11 +187,20 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb) ret = tcg_qemu_tb_exec(env, tb_ptr); cpu->can_do_io = 1; - last_tb = (TranslationBlock *)(ret & ~TB_EXIT_MASK); - tb_exit = ret & TB_EXIT_MASK; - trace_exec_tb_exit(last_tb, tb_exit); + /* + * TODO: Delay swapping back to the read-write region of the TB + * until we actually need to modify the TB. The read-only copy, + * coming from the rx region, shares the same host TLB entry as + * the code that executed the exit_tb opcode that arrived here. + * If we insist on touching both the RX and the RW pages, we + * double the host TLB pressure. + */ + last_tb = tcg_splitwx_to_rw((void *)(ret & ~TB_EXIT_MASK)); + *tb_exit = ret & TB_EXIT_MASK; - if (tb_exit > TB_EXIT_IDX1) { + trace_exec_tb_exit(last_tb, *tb_exit); + + if (*tb_exit > TB_EXIT_IDX1) { /* We didn't start executing this TB (eg because the instruction * counter hit zero); we must restore the guest PC to the address * of the start of the TB. @@ -210,7 +218,7 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb) cc->set_pc(cpu, last_tb->pc); } } - return ret; + return last_tb; } #ifndef CONFIG_USER_ONLY @@ -221,6 +229,7 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cycles, { TranslationBlock *tb; uint32_t cflags = curr_cflags() | CF_NOCACHE; + int tb_exit; if (ignore_icount) { cflags &= ~CF_USE_ICOUNT; @@ -238,7 +247,7 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cycles, /* execute the generated code */ trace_exec_tb_nocache(tb, tb->pc); - cpu_tb_exec(cpu, tb); + cpu_tb_exec(cpu, tb, &tb_exit); mmap_lock(); tb_phys_invalidate(tb, -1); @@ -272,6 +281,7 @@ void cpu_exec_step_atomic(CPUState *cpu) uint32_t flags; uint32_t cflags = 1; uint32_t cf_mask = cflags & CF_HASH_MASK; + int tb_exit; if (sigsetjmp(cpu->jmp_env, 0) == 0) { start_exclusive(); @@ -288,7 +298,7 @@ void cpu_exec_step_atomic(CPUState *cpu) cpu_exec_enter(cpu); /* execute the generated code */ trace_exec_tb(tb, pc); - cpu_tb_exec(cpu, tb); + cpu_tb_exec(cpu, tb, &tb_exit); cpu_exec_exit(cpu); } else { /* @@ -684,13 +694,10 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb, TranslationBlock **last_tb, int *tb_exit) { - uintptr_t ret; int32_t insns_left; trace_exec_tb(tb, tb->pc); - ret = cpu_tb_exec(cpu, tb); - tb = (TranslationBlock *)(ret & ~TB_EXIT_MASK); - *tb_exit = ret & TB_EXIT_MASK; + tb = cpu_tb_exec(cpu, tb, tb_exit); if (*tb_exit != TB_EXIT_REQUESTED) { *last_tb = tb; return; diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 19fa8e4691..0374b5d56d 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2666,7 +2666,18 @@ void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg) void tcg_gen_exit_tb(const TranslationBlock *tb, unsigned idx) { - uintptr_t val = (uintptr_t)tb + idx; + /* + * Let the jit code return the read-only version of the + * TranslationBlock, so that we minimize the pc-relative + * distance of the address of the exit_tb code to TB. + * This will improve utilization of pc-relative address loads. + * + * TODO: Move this to translator_loop, so that all const + * TranslationBlock pointers refer to read-only memory. + * This requires coordination with targets that do not use + * the translator_loop. + */ + uintptr_t val = (uintptr_t)tcg_splitwx_to_rx((void *)tb) + idx; if (tb == NULL) { tcg_debug_assert(idx == 0); From patchwork Thu Jan 7 20:14:26 2021 Content-Type: text/plain; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 25/47] tcg/i386: Support split-wx code generation Date: Thu, 7 Jan 2021 10:14:26 -1000 Message-Id: <20210107201448.1152301-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Joelle van Dyne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Joelle van Dyne Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.c.inc | 20 +++++++++++--------- 2 files changed, 12 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 73aa45a665..cb1b138b66 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -235,6 +235,6 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_SUPPORT_MIRROR 0 +#define TCG_TARGET_SUPPORT_MIRROR 1 #endif diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index d272975ff1..34bf0b9a35 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -164,7 +164,7 @@ static bool have_lzcnt; # define have_lzcnt 0 #endif -static tcg_insn_unit *tb_ret_addr; +static const tcg_insn_unit *tb_ret_addr; static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) @@ -172,7 +172,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, value += addend; switch(type) { case R_386_PC32: - value -= (uintptr_t)code_ptr; + value -= (uintptr_t)tcg_splitwx_to_rx(code_ptr); if (value != (int32_t)value) { return false; } @@ -181,7 +181,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, tcg_patch32(code_ptr, value); break; case R_386_PC8: - value -= (uintptr_t)code_ptr; + value -= (uintptr_t)tcg_splitwx_to_rx(code_ptr); if (value != (int8_t)value) { return false; } @@ -1015,7 +1015,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } /* Try a 7 byte pc-relative lea before the 10 byte movq. */ - diff = arg - ((uintptr_t)s->code_ptr + 7); + diff = tcg_pcrel_diff(s, (const void *)arg) - 7; if (diff == (int32_t)diff) { tcg_out_opc(s, OPC_LEA | P_REXW, ret, 0, 0); tcg_out8(s, (LOWREGMASK(ret) << 3) | 5); @@ -1624,7 +1624,7 @@ static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest) tcg_out_branch(s, 1, dest); } -static void tcg_out_jmp(TCGContext *s, tcg_insn_unit *dest) +static void tcg_out_jmp(TCGContext *s, const tcg_insn_unit *dest) { tcg_out_branch(s, 0, dest); } @@ -1795,7 +1795,8 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64, label->datahi_reg = datahi; label->addrlo_reg = addrlo; label->addrhi_reg = addrhi; - label->raddr = raddr; + /* TODO: Cast goes away when all hosts converted */ + label->raddr = (void *)tcg_splitwx_to_rx(raddr); label->label_ptr[0] = label_ptr[0]; if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { label->label_ptr[1] = label_ptr[1]; @@ -2253,7 +2254,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, /* jump displacement must be aligned for atomic patching; * see if we need to add extra nops before jump */ - gap = tcg_pcrel_diff(s, QEMU_ALIGN_PTR_UP(s->code_ptr + 1, 4)); + gap = QEMU_ALIGN_PTR_UP(s->code_ptr + 1, 4) - s->code_ptr; if (gap != 1) { tcg_out_nopn(s, gap - 1); } @@ -3803,11 +3804,12 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - tcg_code_gen_epilogue = s->code_ptr; + /* TODO: Cast goes away when all hosts converted */ + tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_EAX, 0); /* TB epilogue */ - tb_ret_addr = s->code_ptr; + tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); tcg_out_addi(s, TCG_REG_CALL_STACK, stack_addend); From patchwork Thu Jan 7 20:14:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358283 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp793204jai; Thu, 7 Jan 2021 12:43:19 -0800 (PST) X-Google-Smtp-Source: ABdhPJxjdJI0cPA4LFL0nWNaNikWPVHN5F0ILB0Wjs6UzgTBFpQmXbE923alS+S9/R6U30FKUwtM X-Received: by 2002:a25:f509:: with SMTP id a9mr845888ybe.35.1610052199642; Thu, 07 Jan 2021 12:43:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610052199; cv=none; d=google.com; s=arc-20160816; b=UxU3apASpJrGtcEzJLNBn6CNQmpXzrl7rqwc91YIdaJ8W938WbprvkKsjFFMC1AOv+ kBVlFqWwDQYBDDM1j6HGvn/uYQ3ihH6chD6HC6OuPMEL8L+7KAMpIMLycvAP+o6jNjNt M6dv3W7dKm7pPZDkgtIcsvgJM3MvzvCmoovHV+lqisBNYc8GXZ0CihiJKt7eRgWmWBnv BNybeVi67kJTXjnXgjjFmngDozvpN467JsZbIpc+//NEAqG0hfJSR1snDcYreWXmjEnf 6yjh4FYvbAbVgXDQAyjic3OJOk+u99oGf0SgQOYhOBUxfFG4qVlRduCrBjGgcSswtEuB NxfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8LKGM21omgiw4s8pLH3F/GfWnbD4CM5oKLWF8kPN/DI=; b=wHhWuW495Cx+Bad5/0bSnrhXHme7SsCqURIxklgHrAl/UJu2tffloYw/zwhHfUfsi6 C4ChSMxBVu7FKg3gs3Uag7n0FRE0RA4+ulOZgmW+OvBxUBu8Ihsp+yOGkmMgr8/59LmW 2J9Ye2uKvdJatjUDQ6ZK9BETrQUurhhEzHBhzBtRY2o4e6P3DYcyxm46QN4dm5pI0Hmk biID7R5YNjEcGtDznHVcUtb61mJt33poSv/czzGLnsJfAxfpgEIelgMMtS/pRfyWWFFF h30E99LxUfzke6C6BKcprDFc/529wIxiPubRB5Ohz/IxQPflUy7DsVt64vs686lkqnPb AcLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=w+Cadi1K; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 26/47] tcg/aarch64: Use B not BL for tcg_out_goto_long Date: Thu, 7 Jan 2021 10:14:27 -1000 Message-Id: <20210107201448.1152301-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Joelle van Dyne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" A typo generated a branch-and-link insn instead of plain branch. Reviewed-by: Joelle van Dyne Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index fea784cf75..bd888bc66d 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1317,7 +1317,7 @@ static inline void tcg_out_goto_long(TCGContext *s, tcg_insn_unit *target) { ptrdiff_t offset = target - s->code_ptr; if (offset == sextract64(offset, 0, 26)) { - tcg_out_insn(s, 3206, BL, offset); + tcg_out_insn(s, 3206, B, offset); } else { tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, (intptr_t)target); tcg_out_insn(s, 3207, BR, TCG_REG_TMP); From patchwork Thu Jan 7 20:14:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358284 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp793496jai; Thu, 7 Jan 2021 12:43:51 -0800 (PST) X-Google-Smtp-Source: ABdhPJzAWrXYqMQDkOrg+GQfu/8ZVrz8JRF6wmbKM7/m/cDRufe4bhgex3TPD3zsAJ8hGGT4uThV X-Received: by 2002:a25:cf95:: with SMTP id f143mr819171ybg.419.1610052231616; Thu, 07 Jan 2021 12:43:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610052231; cv=none; d=google.com; s=arc-20160816; b=OaMJz4RTd56PzZToi5a/2pYnhhpwWLfpEmOTMJGp3JDWtERDEsLkU8Rn6QUe6+1uCh lEq6TJTwI2FmC+bNQRyyW0Cerif9PDVEzrsQsOPArxltiWlvE0TXCvu70JrMFz/9UFpZ 5NW6j59wjBzw002SEWUp/W4CYwjE5Twpnogj60evbVF7vsbeSpU97nIB75kscnD7Gx3+ hI5tPOvRM0Qu9uYdyIZK4YdEd6u6LjauCRHOLWgdjT7z1tHk8tdppR2JJmJtiK5YQDSG 0190ZswS6ANPt40MTYLwi7Zh9cm7R4YnoIsMAadzOFDrFB8yIP/dSIkdUpyM7JCLVvmJ sqcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=T8AfGj+HO8ldfN1QyJhTtl82SWRrf2P8eJp7eJUkZZU=; b=QjqtxsQ66gXLQWXNzH8KMWHaFO8JsAeDgBmx3i3D38GI0GH1fdRcGu4I6L1wqUcxlG lsvIAfzFBGiwwy/BfBTYrvOcLbE3gi9Fggsuc77r4HRsmujOVxIkpJsYWN01DN8OVH2M XVE+38gM8EZqDDVQBQ459WG3LVOadA9VXjAtNOyobAUsqvRB3RlsAoWcIptm7L8a8Usd XS723EstaYifiEupHXTwAGn58xtj+jkuXpCnu7ilJbaKbIeuiIpB+Dapo0zb2njq96DM W4qzAe5rCZxn0rarshEdEyCLNQmmX/v0gM+OkHS+4N2ZOk2hypWEn1MeVyqxlw0kQlzt 1lZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QjgmX7zq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 27/47] tcg/aarch64: Support split-wx code generation Date: Thu, 7 Jan 2021 10:14:28 -1000 Message-Id: <20210107201448.1152301-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Joelle van Dyne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Joelle van Dyne Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 +- tcg/aarch64/tcg-target.c.inc | 57 ++++++++++++++++++++---------------- 2 files changed, 33 insertions(+), 26 deletions(-) -- 2.25.1 diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 23bf87db3d..079828ea71 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -155,6 +155,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_SUPPORT_MIRROR 0 +#define TCG_TARGET_SUPPORT_MIRROR 1 #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index bd888bc66d..2e33162c03 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -78,38 +78,42 @@ static const int tcg_target_call_oarg_regs[1] = { #define TCG_REG_GUEST_BASE TCG_REG_X28 #endif -static inline bool reloc_pc26(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +static bool reloc_pc26(tcg_insn_unit *src_rw, const tcg_insn_unit *target) { - ptrdiff_t offset = target - code_ptr; + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); + ptrdiff_t offset = target - src_rx; + if (offset == sextract64(offset, 0, 26)) { /* read instruction, mask away previous PC_REL26 parameter contents, set the proper offset, then write back the instruction. */ - *code_ptr = deposit32(*code_ptr, 0, 26, offset); + *src_rw = deposit32(*src_rw, 0, 26, offset); return true; } return false; } -static inline bool reloc_pc19(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +static bool reloc_pc19(tcg_insn_unit *src_rw, const tcg_insn_unit *target) { - ptrdiff_t offset = target - code_ptr; + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); + ptrdiff_t offset = target - src_rx; + if (offset == sextract64(offset, 0, 19)) { - *code_ptr = deposit32(*code_ptr, 5, 19, offset); + *src_rw = deposit32(*src_rw, 5, 19, offset); return true; } return false; } -static inline bool patch_reloc(tcg_insn_unit *code_ptr, int type, - intptr_t value, intptr_t addend) +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, + intptr_t value, intptr_t addend) { tcg_debug_assert(addend == 0); switch (type) { case R_AARCH64_JUMP26: case R_AARCH64_CALL26: - return reloc_pc26(code_ptr, (tcg_insn_unit *)value); + return reloc_pc26(code_ptr, (const tcg_insn_unit *)value); case R_AARCH64_CONDBR19: - return reloc_pc19(code_ptr, (tcg_insn_unit *)value); + return reloc_pc19(code_ptr, (const tcg_insn_unit *)value); default: g_assert_not_reached(); } @@ -1050,12 +1054,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, /* Look for host pointer values within 4G of the PC. This happens often when loading pointers to QEMU's own data structures. */ if (type == TCG_TYPE_I64) { - tcg_target_long disp = value - (intptr_t)s->code_ptr; + intptr_t src_rx = (intptr_t)tcg_splitwx_to_rx(s->code_ptr); + tcg_target_long disp = value - src_rx; if (disp == sextract64(disp, 0, 21)) { tcg_out_insn(s, 3406, ADR, rd, disp); return; } - disp = (value >> 12) - ((intptr_t)s->code_ptr >> 12); + disp = (value >> 12) - (src_rx >> 12); if (disp == sextract64(disp, 0, 21)) { tcg_out_insn(s, 3406, ADRP, rd, disp); if (value & 0xfff) { @@ -1308,14 +1313,14 @@ static void tcg_out_cmp(TCGContext *s, TCGType ext, TCGReg a, static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) { - ptrdiff_t offset = target - s->code_ptr; + ptrdiff_t offset = tcg_pcrel_diff(s, target) >> 2; tcg_debug_assert(offset == sextract64(offset, 0, 26)); tcg_out_insn(s, 3206, B, offset); } -static inline void tcg_out_goto_long(TCGContext *s, tcg_insn_unit *target) +static void tcg_out_goto_long(TCGContext *s, const tcg_insn_unit *target) { - ptrdiff_t offset = target - s->code_ptr; + ptrdiff_t offset = tcg_pcrel_diff(s, target) >> 2; if (offset == sextract64(offset, 0, 26)) { tcg_out_insn(s, 3206, B, offset); } else { @@ -1329,9 +1334,9 @@ static inline void tcg_out_callr(TCGContext *s, TCGReg reg) tcg_out_insn(s, 3207, BLR, reg); } -static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *target) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target) { - ptrdiff_t offset = target - s->code_ptr; + ptrdiff_t offset = tcg_pcrel_diff(s, target) >> 2; if (offset == sextract64(offset, 0, 26)) { tcg_out_insn(s, 3206, BL, offset); } else { @@ -1393,7 +1398,7 @@ static void tcg_out_brcond(TCGContext *s, TCGType ext, TCGCond c, TCGArg a, tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, l, 0); offset = tcg_in32(s) >> 5; } else { - offset = l->u.value_ptr - s->code_ptr; + offset = tcg_pcrel_diff(s, l->u.value_ptr) >> 2; tcg_debug_assert(offset == sextract64(offset, 0, 19)); } @@ -1568,7 +1573,7 @@ static void * const qemu_st_helpers[16] = { [MO_BEQ] = helper_be_stq_mmu, }; -static inline void tcg_out_adr(TCGContext *s, TCGReg rd, void *target) +static inline void tcg_out_adr(TCGContext *s, TCGReg rd, const void *target) { ptrdiff_t offset = tcg_pcrel_diff(s, target); tcg_debug_assert(offset == sextract64(offset, 0, 21)); @@ -1581,7 +1586,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) MemOp opc = get_memop(oi); MemOp size = opc & MO_SIZE; - if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) { + if (!reloc_pc19(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } @@ -1606,7 +1611,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) MemOp opc = get_memop(oi); MemOp size = opc & MO_SIZE; - if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) { + if (!reloc_pc19(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } @@ -1631,7 +1636,8 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, label->type = ext; label->datalo_reg = data_reg; label->addrlo_reg = addr_reg; - label->raddr = raddr; + /* TODO: Cast goes away when all hosts converted */ + label->raddr = (void *)tcg_splitwx_to_rx(raddr); label->label_ptr[0] = label_ptr; } @@ -1849,7 +1855,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, #endif /* CONFIG_SOFTMMU */ } -static tcg_insn_unit *tb_ret_addr; +static const tcg_insn_unit *tb_ret_addr; static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], @@ -2894,11 +2900,12 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - tcg_code_gen_epilogue = s->code_ptr; + /* TODO: Cast goes away when all hosts converted */ + tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_X0, 0); /* TB epilogue */ - tb_ret_addr = s->code_ptr; + tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); /* Remove TCG locals stack space. */ tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_SP, TCG_REG_SP, From patchwork Thu Jan 7 20:14:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358286 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp794804jai; Thu, 7 Jan 2021 12:46:04 -0800 (PST) X-Google-Smtp-Source: ABdhPJwSFzqF9j8jLUIf9pnWxVZPJULe86mncLu+2qQOr/kn+AO6afGdpFMJGmAPUpqGjKrIphng X-Received: by 2002:a25:df05:: with SMTP id w5mr925339ybg.477.1610052364029; Thu, 07 Jan 2021 12:46:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610052364; cv=none; d=google.com; s=arc-20160816; b=FO3uApU5bAh64dHGa9zj0f//nmr+7yA8I/Hp2LONnI4WD0pOYlx6e4c3G7zXAmFkgO G72K+YS28YuWBS0X9GMMaY08n+AUrGeBZNMLqxs2WQM38jSysYQyvMPL4nb0EHMBPX7U xxuH2tqZHE7gl7azfTySy74I/Y4i1Ab14XdjAoozKDPxQ9DJH6LLuy1svpjGNiGQyIxm Itd8i4IrxpKcybdSwRyrkYUJZH92XAO/F0dkO8ga8JtfyX9aPJMHy8vFGHORkaagN48L 3DhcGTMwIoTuydfQfSasmIEmfTaFqPIbJVXE9XV1h8kBduYhXkSueNV5snc50s5UgRg8 mP8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MOmUYS+2+okyDd2n7XwYqRe+eURAl58gvEsSNOVb+48=; b=K8zhV2r4+VcOTanQHmf+R2G9PMTPR7HYK94y/rz2PAs15oXS3b0po63PSFiN/XRFAG XkZbnlGbgfEZVvTnXW1z3J7UmjBAiCVEETVrLsYyS0j3USeAusjmm1w3jDNfJw7OBlGh cnfpXn0aiYiK/+6Jr8d0mBBighuuyHSx1xVeNvNDM/QeP4ZhPbuY3Xgd50qS2CXKr6l2 MDdIpz7xFe7w8BOgdgj+BClkTrAQcFv03lzGml2eY+15PtdI2wBVThm5fr4EAV02iBIq 4SmdnQGnjc/q7168Ve7tId9/ZL4wa+DGHkzk63U2oeKa4ymxRkutPqlTxAUwMxByTv+h QAbA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TchH5REw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 28/47] disas: Push const down through host disassembly Date: Thu, 7 Jan 2021 10:14:29 -1000 Message-Id: <20210107201448.1152301-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Joelle van Dyne , =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Joelle van Dyne Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/disas/dis-asm.h | 4 ++-- disas.c | 4 +--- disas/capstone.c | 2 +- 3 files changed, 4 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h index 2164762b46..d1133a4e04 100644 --- a/include/disas/dis-asm.h +++ b/include/disas/dis-asm.h @@ -358,7 +358,7 @@ typedef struct disassemble_info { (bfd_vma addr, struct disassemble_info * info); /* These are for buffer_read_memory. */ - bfd_byte *buffer; + const bfd_byte *buffer; bfd_vma buffer_vma; int buffer_length; @@ -462,7 +462,7 @@ int print_insn_rx(bfd_vma, disassemble_info *); #ifdef CONFIG_CAPSTONE bool cap_disas_target(disassemble_info *info, uint64_t pc, size_t size); -bool cap_disas_host(disassemble_info *info, void *code, size_t size); +bool cap_disas_host(disassemble_info *info, const void *code, size_t size); bool cap_disas_monitor(disassemble_info *info, uint64_t pc, int count); bool cap_disas_plugin(disassemble_info *info, uint64_t pc, size_t size); #else diff --git a/disas.c b/disas.c index de1de7be94..a61f95b580 100644 --- a/disas.c +++ b/disas.c @@ -299,10 +299,8 @@ char *plugin_disas(CPUState *cpu, uint64_t addr, size_t size) } /* Disassemble this for me please... (debugging). */ -void disas(FILE *out, const void *ccode, unsigned long size) +void disas(FILE *out, const void *code, unsigned long size) { - /* TODO: Push constness through the disas backends. */ - void *code = (void *)ccode; uintptr_t pc; int count; CPUDebug s; diff --git a/disas/capstone.c b/disas/capstone.c index 7462c0e305..20bc8f9669 100644 --- a/disas/capstone.c +++ b/disas/capstone.c @@ -229,7 +229,7 @@ bool cap_disas_target(disassemble_info *info, uint64_t pc, size_t size) } /* Disassemble SIZE bytes at CODE for the host. */ -bool cap_disas_host(disassemble_info *info, void *code, size_t size) +bool cap_disas_host(disassemble_info *info, const void *code, size_t size) { csh handle; const uint8_t *cbuf; From patchwork Thu Jan 7 20:14:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358278 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp791119jai; Thu, 7 Jan 2021 12:39:32 -0800 (PST) X-Google-Smtp-Source: ABdhPJxfPG7098JehAGyO3c4Qptdi23aUzsQj+EzKwxvNc0yUX0Qs5gBoNbTyIwvr3M/KnaLVwP+ X-Received: by 2002:a25:cf08:: with SMTP id f8mr955763ybg.210.1610051972670; Thu, 07 Jan 2021 12:39:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610051972; cv=none; d=google.com; s=arc-20160816; b=NBd/3YuhgTL8YfP107b57GZA6novx+P1S1LviwQOT+IFQ2kW2u4bEb+me0wCJj5UfR 7bwsG+jwwiTw9h39rmqHNXdG+YJTdo2pA5qD/3ZKdezO57CVDuchn4+G0MCm+9f0WVpp 3QHU8bDgoXzstNWc22efDMIFZ/JeBHzrcjkUBL7dDNrrwV0hr04W6Y5YDOcaLCsNbBH0 lq+y67QMMRU166S9ayl0Z76/+uHebkFeMlfGJJ+1gA2g5VZwUQ1Zmu0cqgo511E7JwSU 72dPVn5aeRlxsZDe6YyOLNMOJiW+F7zEQ9ePBIdf6Im78gfZgFICQxQmBx+a64S0ech9 c1UA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=AJQYK8LKfTzhiujiEv/x9kE4WE8MnmVirj6n1IdQE8k=; b=oHvjWrmtdjBtR7useC1Tu9d3sQC7vZRG8gmn7PqR4PkkHF2A/daagqT1d0td04AD1T QNH6FBTj/iT9qdwgibpK5T6ESBGQhCnPVDRxTv1ewp20VIDSwN7KWKLPY4wFQswuKU4p 9OgtrcgbPKNSyRsxJN2HR5c3hsVlwWYKumwmpj8zDD6km9zRkK5XRiM2qm7theqbEyHp o1RV5PQff5tFn9XiB0fP6x7XR8wZ7d9xm70IQPw4jHLRiE+b5HEb06NtX41rR8Qt5SRF DqHC93MAcXOX0EAg6N70d7BJzBxxb9axAnDZaoSnIFoX8NwEksXZUu3ttNQbKNGBwcr4 8MKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oYgkaGUj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 29/47] tcg/tci: Push const down through bytecode reading Date: Thu, 7 Jan 2021 10:14:30 -1000 Message-Id: <20210107201448.1152301-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Joelle van Dyne , =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Joelle van Dyne Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci.c | 60 +++++++++++++++++++++++++++++++------------------------ 1 file changed, 34 insertions(+), 26 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 017887bbc9..2bcc4409be 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -164,34 +164,34 @@ static uint64_t tci_uint64(uint32_t high, uint32_t low) #endif /* Read constant (native size) from bytecode. */ -static tcg_target_ulong tci_read_i(uint8_t **tb_ptr) +static tcg_target_ulong tci_read_i(const uint8_t **tb_ptr) { - tcg_target_ulong value = *(tcg_target_ulong *)(*tb_ptr); + tcg_target_ulong value = *(const tcg_target_ulong *)(*tb_ptr); *tb_ptr += sizeof(value); return value; } /* Read unsigned constant (32 bit) from bytecode. */ -static uint32_t tci_read_i32(uint8_t **tb_ptr) +static uint32_t tci_read_i32(const uint8_t **tb_ptr) { - uint32_t value = *(uint32_t *)(*tb_ptr); + uint32_t value = *(const uint32_t *)(*tb_ptr); *tb_ptr += sizeof(value); return value; } /* Read signed constant (32 bit) from bytecode. */ -static int32_t tci_read_s32(uint8_t **tb_ptr) +static int32_t tci_read_s32(const uint8_t **tb_ptr) { - int32_t value = *(int32_t *)(*tb_ptr); + int32_t value = *(const int32_t *)(*tb_ptr); *tb_ptr += sizeof(value); return value; } #if TCG_TARGET_REG_BITS == 64 /* Read constant (64 bit) from bytecode. */ -static uint64_t tci_read_i64(uint8_t **tb_ptr) +static uint64_t tci_read_i64(const uint8_t **tb_ptr) { - uint64_t value = *(uint64_t *)(*tb_ptr); + uint64_t value = *(const uint64_t *)(*tb_ptr); *tb_ptr += sizeof(value); return value; } @@ -199,7 +199,7 @@ static uint64_t tci_read_i64(uint8_t **tb_ptr) /* Read indexed register (native size) from bytecode. */ static tcg_target_ulong -tci_read_r(const tcg_target_ulong *regs, uint8_t **tb_ptr) +tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { tcg_target_ulong value = tci_read_reg(regs, **tb_ptr); *tb_ptr += 1; @@ -207,7 +207,7 @@ tci_read_r(const tcg_target_ulong *regs, uint8_t **tb_ptr) } /* Read indexed register (8 bit) from bytecode. */ -static uint8_t tci_read_r8(const tcg_target_ulong *regs, uint8_t **tb_ptr) +static uint8_t tci_read_r8(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { uint8_t value = tci_read_reg8(regs, **tb_ptr); *tb_ptr += 1; @@ -216,7 +216,7 @@ static uint8_t tci_read_r8(const tcg_target_ulong *regs, uint8_t **tb_ptr) #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 /* Read indexed register (8 bit signed) from bytecode. */ -static int8_t tci_read_r8s(const tcg_target_ulong *regs, uint8_t **tb_ptr) +static int8_t tci_read_r8s(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { int8_t value = tci_read_reg8s(regs, **tb_ptr); *tb_ptr += 1; @@ -225,7 +225,8 @@ static int8_t tci_read_r8s(const tcg_target_ulong *regs, uint8_t **tb_ptr) #endif /* Read indexed register (16 bit) from bytecode. */ -static uint16_t tci_read_r16(const tcg_target_ulong *regs, uint8_t **tb_ptr) +static uint16_t tci_read_r16(const tcg_target_ulong *regs, + const uint8_t **tb_ptr) { uint16_t value = tci_read_reg16(regs, **tb_ptr); *tb_ptr += 1; @@ -234,7 +235,8 @@ static uint16_t tci_read_r16(const tcg_target_ulong *regs, uint8_t **tb_ptr) #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 /* Read indexed register (16 bit signed) from bytecode. */ -static int16_t tci_read_r16s(const tcg_target_ulong *regs, uint8_t **tb_ptr) +static int16_t tci_read_r16s(const tcg_target_ulong *regs, + const uint8_t **tb_ptr) { int16_t value = tci_read_reg16s(regs, **tb_ptr); *tb_ptr += 1; @@ -243,7 +245,8 @@ static int16_t tci_read_r16s(const tcg_target_ulong *regs, uint8_t **tb_ptr) #endif /* Read indexed register (32 bit) from bytecode. */ -static uint32_t tci_read_r32(const tcg_target_ulong *regs, uint8_t **tb_ptr) +static uint32_t tci_read_r32(const tcg_target_ulong *regs, + const uint8_t **tb_ptr) { uint32_t value = tci_read_reg32(regs, **tb_ptr); *tb_ptr += 1; @@ -252,14 +255,16 @@ static uint32_t tci_read_r32(const tcg_target_ulong *regs, uint8_t **tb_ptr) #if TCG_TARGET_REG_BITS == 32 /* Read two indexed registers (2 * 32 bit) from bytecode. */ -static uint64_t tci_read_r64(const tcg_target_ulong *regs, uint8_t **tb_ptr) +static uint64_t tci_read_r64(const tcg_target_ulong *regs, + const uint8_t **tb_ptr) { uint32_t low = tci_read_r32(regs, tb_ptr); return tci_uint64(tci_read_r32(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS == 64 /* Read indexed register (32 bit signed) from bytecode. */ -static int32_t tci_read_r32s(const tcg_target_ulong *regs, uint8_t **tb_ptr) +static int32_t tci_read_r32s(const tcg_target_ulong *regs, + const uint8_t **tb_ptr) { int32_t value = tci_read_reg32s(regs, **tb_ptr); *tb_ptr += 1; @@ -267,7 +272,8 @@ static int32_t tci_read_r32s(const tcg_target_ulong *regs, uint8_t **tb_ptr) } /* Read indexed register (64 bit) from bytecode. */ -static uint64_t tci_read_r64(const tcg_target_ulong *regs, uint8_t **tb_ptr) +static uint64_t tci_read_r64(const tcg_target_ulong *regs, + const uint8_t **tb_ptr) { uint64_t value = tci_read_reg64(regs, **tb_ptr); *tb_ptr += 1; @@ -277,7 +283,7 @@ static uint64_t tci_read_r64(const tcg_target_ulong *regs, uint8_t **tb_ptr) /* Read indexed register(s) with target address from bytecode. */ static target_ulong -tci_read_ulong(const tcg_target_ulong *regs, uint8_t **tb_ptr) +tci_read_ulong(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { target_ulong taddr = tci_read_r(regs, tb_ptr); #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS @@ -288,7 +294,7 @@ tci_read_ulong(const tcg_target_ulong *regs, uint8_t **tb_ptr) /* Read indexed register or constant (native size) from bytecode. */ static tcg_target_ulong -tci_read_ri(const tcg_target_ulong *regs, uint8_t **tb_ptr) +tci_read_ri(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { tcg_target_ulong value; TCGReg r = **tb_ptr; @@ -302,7 +308,8 @@ tci_read_ri(const tcg_target_ulong *regs, uint8_t **tb_ptr) } /* Read indexed register or constant (32 bit) from bytecode. */ -static uint32_t tci_read_ri32(const tcg_target_ulong *regs, uint8_t **tb_ptr) +static uint32_t tci_read_ri32(const tcg_target_ulong *regs, + const uint8_t **tb_ptr) { uint32_t value; TCGReg r = **tb_ptr; @@ -317,14 +324,16 @@ static uint32_t tci_read_ri32(const tcg_target_ulong *regs, uint8_t **tb_ptr) #if TCG_TARGET_REG_BITS == 32 /* Read two indexed registers or constants (2 * 32 bit) from bytecode. */ -static uint64_t tci_read_ri64(const tcg_target_ulong *regs, uint8_t **tb_ptr) +static uint64_t tci_read_ri64(const tcg_target_ulong *regs, + const uint8_t **tb_ptr) { uint32_t low = tci_read_ri32(regs, tb_ptr); return tci_uint64(tci_read_ri32(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS == 64 /* Read indexed register or constant (64 bit) from bytecode. */ -static uint64_t tci_read_ri64(const tcg_target_ulong *regs, uint8_t **tb_ptr) +static uint64_t tci_read_ri64(const tcg_target_ulong *regs, + const uint8_t **tb_ptr) { uint64_t value; TCGReg r = **tb_ptr; @@ -338,7 +347,7 @@ static uint64_t tci_read_ri64(const tcg_target_ulong *regs, uint8_t **tb_ptr) } #endif -static tcg_target_ulong tci_read_label(uint8_t **tb_ptr) +static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) { tcg_target_ulong label = tci_read_i(tb_ptr); tci_assert(label != 0); @@ -484,8 +493,7 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition) uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, const void *v_tb_ptr) { - /* TODO: Propagate const through this file. */ - uint8_t *tb_ptr = (uint8_t *)v_tb_ptr; + const uint8_t *tb_ptr = v_tb_ptr; tcg_target_ulong regs[TCG_TARGET_NB_REGS]; long tcg_temps[CPU_TEMP_BUF_NLONGS]; uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS); @@ -499,7 +507,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, TCGOpcode opc = tb_ptr[0]; #if defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG) uint8_t op_size = tb_ptr[1]; - uint8_t *old_code_ptr = tb_ptr; + const uint8_t *old_code_ptr = tb_ptr; #endif tcg_target_ulong t0; tcg_target_ulong t1; From patchwork Thu Jan 7 20:14:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358273 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp789179jai; Thu, 7 Jan 2021 12:35:50 -0800 (PST) X-Google-Smtp-Source: ABdhPJwxX6+GeFlSIKAI9nBtg3Yqn9pFr+hyLj+k3Y6ef/H0Rcy1uz/mYvfSo1rWMOhAjqBhVQh+ X-Received: by 2002:a25:d788:: with SMTP id o130mr833122ybg.245.1610051750430; Thu, 07 Jan 2021 12:35:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610051750; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 30/47] tcg: Introduce tcg_tbrel_diff Date: Thu, 7 Jan 2021 10:14:31 -1000 Message-Id: <20210107201448.1152301-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Joelle van Dyne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Joelle van Dyne Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.25.1 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index e744a1ce02..e6fce9a049 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -1146,6 +1146,19 @@ static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, const void *target) return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_ptr)); } +/** + * tcg_tbrel_diff + * @s: the tcg context + * @target: address of the target + * + * Produce a difference, from the beginning of the current TB code + * to the destination address. + */ +static inline ptrdiff_t tcg_tbrel_diff(TCGContext *s, const void *target) +{ + return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_buf)); +} + /** * tcg_current_code_size * @s: the tcg context From patchwork Thu Jan 7 20:14:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358277 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp790421jai; Thu, 7 Jan 2021 12:38:08 -0800 (PST) X-Google-Smtp-Source: ABdhPJyHqXkwuLRAROgaYJPf3L49RXVvyIWV5rDWapr/4h/a2HyMHc4N460bDnNc9dqP4c8DYIHt X-Received: by 2002:a25:26c7:: with SMTP id m190mr840180ybm.464.1610051888881; Thu, 07 Jan 2021 12:38:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610051888; cv=none; d=google.com; s=arc-20160816; b=GfHQFEawUBHwEckI70ts+gaQqnDw0a9yj10kn9OGg25rvS7I8tpiRWQEh0obQw9lDo WfS5XycN65EpJg92RAea6xujXF3qBc4sCvIc1w4x4UrivfIm9WaI7sOb7OuJUBnosj7I R4TcnmjhOHIXONZ+as/9iJ/gGf8yZkE6v6ZEXExNugai1WbnJtpI2adAfLyAUd+uGwry aJmYszcEqFPnY7QF7C4meaw5/elpT5BrhQLdXyRVmzAvVQdqxLX1cAta57o4d0ldJRf0 Yr9GurgLfn9yR1xPPZ34PVWs+VT9J7lyfvGJSFt2Jfql5mW3LCwFExjInB1rwEPfJFdY FUIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qay0jNTmpyZq4ULzg3vkr0em7pJVaOqPAuzaBx5paoU=; b=fVp9kv8csWKcTqTKqVrEm74bVlizoAajk5X+OleEPvOSXlIR9FBgiYN5mDB8mBpXWa 1Qk8hrssg0sLDUCuxPZTGVOBeSjpEnOi6hB7WgXf1B5t+sZK8wWALfupC7ncRsfN8yg/ Xu400aVp+dV9/UPpmELEaATDlSR/wmCpW3OI5GKNl1THmONM4PowO+L55STv4Flnaao5 EPwBqYQzAaH240PSibynWFs2U24Fhpchujuhq3vm8ECHh4F9t/rNkPvF7CQ/hT7jzNlr EaXBD529LOWxlaRhVZqO82LNK6QCZpUdG9h42lwTLNbW2xryR0yROd9BvvTX/WTMIcyJ ZTSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=j4k7cODb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 31/47] tcg/ppc: Use tcg_tbrel_diff Date: Thu, 7 Jan 2021 10:14:32 -1000 Message-Id: <20210107201448.1152301-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use tcg_tbrel_diff when we need a displacement to a label, and with a NULL argument when we need the normalizing addend. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 0eb9c4ebe2..ed7a201578 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -837,7 +837,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, } /* Load addresses within the TB with one insn. */ - tb_diff = arg - (intptr_t)s->code_gen_ptr; + tb_diff = tcg_tbrel_diff(s, (void *)arg); if (!in_prologue && USE_REG_TB && tb_diff == (int16_t)tb_diff) { tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff)); return; @@ -890,7 +890,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, /* Use the constant pool, if possible. */ if (!in_prologue && USE_REG_TB) { new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr, - -(intptr_t)s->code_gen_ptr); + tcg_tbrel_diff(s, NULL)); tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0)); return; } @@ -940,7 +940,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret, */ if (USE_REG_TB) { rel = R_PPC_ADDR16; - add = -(intptr_t)s->code_gen_ptr; + add = tcg_tbrel_diff(s, NULL); } else { rel = R_PPC_ADDR32; add = 0; From patchwork Thu Jan 7 20:14:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358285 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp794126jai; Thu, 7 Jan 2021 12:44:58 -0800 (PST) X-Google-Smtp-Source: ABdhPJwNz7xx1TryJjMTKYeeIgw3zZwK9SN8kNrqDzLdCQvynqt8HOXaO0Vp9jNkEuRNQ/JQTO94 X-Received: by 2002:a25:234c:: with SMTP id j73mr996340ybj.116.1610052297984; Thu, 07 Jan 2021 12:44:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610052297; cv=none; d=google.com; s=arc-20160816; b=dK9byOzTolXRWuIZaH7igcFhxhL2IkpoxkEcddjCC8FrU30qWZ+5pX6Cyj+jt94s/O OLQofRkEjZJEag1pKP9bW+39K+hRMuA7rnvZ8wLcsm2fs9h0hN/K/gggi4M6JrKkE0wl 9KXhzkZQCj/QFy5UygwnRhcoFbD2MAu9muN4fqHn0a248Dkysn3LufzSAJKWkT32ll33 yTRICY8bMiid9kgkhJu+BUdz/xyqODmu/n71bMAo6gwXa9U2WLBiE04Q+nc1S1CIdqwi 6gT9TH9yTJsqpb9SLTqJD8MnCEf55bXV87EoGaKJUL9TUeQaCWqGQJiy6L7bCCpmw8fk mH0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ASquR/6BxZoSVQzDtOnOXOHE8jLTrkcyVCDT0iJkP14=; b=fNOu+uZVngvHG8egpPUIwUppH7Lxco8WBEzT8zD4T6SXLv5jrpu7sJuR1yT1olD3eW Bay6mLI/VKYC8AOuucFJVYzbS2rsUkqoZOK2uUblU94ErmU+u9Z2YK6buZTqVfQWtiVa rONlxN8xFeJF58uzIRDOL+e13H/+Tk16PkPc5vb8P5jM6c+RHPjCyft20BhVGfEROw/m NSYy6jrkL7P7+V5JAb7Fcf1v9NcDd1omkMR+ulC9QdE4YayuxruY2GJGuI0hZslM85TI EXRNbSUDFsIlY0HzfG85gmiO4hwkDL0cOxsUA/w+q+yjCj50RDJmBxElOCG7+UPIXZ3S 2e8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hKm8O3vo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 32/47] tcg/ppc: Use tcg_out_mem_long to reset TCG_REG_TB Date: Thu, 7 Jan 2021 10:14:33 -1000 Message-Id: <20210107201448.1152301-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The maximum TB code gen size is UINT16_MAX, which the current code does not support. Use our utility function to optimally add an arbitrary constant. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index ed7a201578..1f8a446b90 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2392,9 +2392,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, set_jmp_reset_offset(s, args[0]); if (USE_REG_TB) { /* For the unlinked case, need to reset TCG_REG_TB. */ - c = -tcg_current_code_size(s); - assert(c == (int16_t)c); - tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, c)); + tcg_out_mem_long(s, ADDI, ADD, TCG_REG_TB, TCG_REG_TB, + -tcg_current_code_size(s)); } break; case INDEX_op_goto_ptr: From patchwork Thu Jan 7 20:14:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358281 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp792606jai; Thu, 7 Jan 2021 12:42:19 -0800 (PST) X-Google-Smtp-Source: ABdhPJzTEYH/gR7+VqOAZOtU9a6DzL0Lw1ys+23XUOes4ZxwX7q0pq/Q2ONehBxOxU5UOtLDxc6G X-Received: by 2002:a25:dc09:: with SMTP id y9mr867445ybe.231.1610052139189; Thu, 07 Jan 2021 12:42:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610052139; cv=none; d=google.com; s=arc-20160816; b=ndEHVRRWBSse3dauTCdeLLRpRSkqooH74Mc+Zqsu03dvsKm5ZJ3MBl6hZmWisZZVBA uhjpxTDyynh+odkhmAeojyGHrI45PStjxBEggNb00o0rQlQ84bt7dmpkKlPIVbaANOtO /51ri0vkjqqhYRe+gefB/ACMaE7Y613c+0KNAC3DkO0t3hrbxGQIpUqrIMtLv4BTVP0T UrtrYCWf/E/1YNJkVpU5JGWsKUI2a3njPZtIngvl7kQI0u/+/e85nRs5rDyfNQ/eeYBL dZm94FtjuVrlCXO/WuNIixHEF61YRlEK2DfCJwW83Ms9s8PxL+RUwDDeAI2iCMdoTeuI pSng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=k1dwR6fbig20YHFioF/qNG9UvMMCDYRmx+wuQtP3btg=; b=bGoDyJFE0ZtP2s8+7y12zI2Uu08GDIx/Y0CPCaUed0Tx/8QEaIEEdtJe4PFdSm6Ztm m+7d/gW2y/v9tjnGVQaalvyXvjXvX39/OoL9Pm8lhzhRhyw27F2paXzBX1RM9YVFpwI3 ZNHV+5brSjmYsiugLpK7SzjCgVjA6BtzRlA4UCU/7yQvmvhj/Yw+W7Iwn9YMo50N0UqH Uk2NNHtn/7qxqO6IH02JSBie0pjM9NX9nDs1ETSJ7SNO/q7sDArm2m6V81xuZ3FsQzfW HG8ltXufEoRzrjfc2XGJ1syZgzyi6OmcRYaadWxbnwz1fUGt6zDT77FaDB8V3UH4Zd5G +4uQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b8IumhFD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 33/47] tcg/ppc: Support split-wx code generation Date: Thu, 7 Jan 2021 10:14:34 -1000 Message-Id: <20210107201448.1152301-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 2 +- tcg/ppc/tcg-target.c.inc | 53 +++++++++++++++++++++++----------------- 2 files changed, 31 insertions(+), 24 deletions(-) -- 2.25.1 diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index ba61a31b3e..ec51f474a7 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -185,6 +185,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_SUPPORT_MIRROR 0 +#define TCG_TARGET_SUPPORT_MIRROR 1 #endif diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 1f8a446b90..33b5915005 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -62,8 +62,6 @@ #define TCG_CT_CONST_MONE 0x2000 #define TCG_CT_CONST_WSZ 0x4000 -static tcg_insn_unit *tb_ret_addr; - TCGPowerISA have_isa; static bool have_isel; bool have_altivec; @@ -184,35 +182,41 @@ static inline bool in_range_b(tcg_target_long target) return target == sextract64(target, 0, 26); } -static uint32_t reloc_pc24_val(tcg_insn_unit *pc, const tcg_insn_unit *target) +static uint32_t reloc_pc24_val(const tcg_insn_unit *pc, + const tcg_insn_unit *target) { ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); tcg_debug_assert(in_range_b(disp)); return disp & 0x3fffffc; } -static bool reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target) +static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) { - ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); + ptrdiff_t disp = tcg_ptr_byte_diff(target, src_rx); + if (in_range_b(disp)) { - *pc = (*pc & ~0x3fffffc) | (disp & 0x3fffffc); + *src_rw = (*src_rw & ~0x3fffffc) | (disp & 0x3fffffc); return true; } return false; } -static uint16_t reloc_pc14_val(tcg_insn_unit *pc, const tcg_insn_unit *target) +static uint16_t reloc_pc14_val(const tcg_insn_unit *pc, + const tcg_insn_unit *target) { ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); tcg_debug_assert(disp == (int16_t) disp); return disp & 0xfffc; } -static bool reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target) +static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target) { - ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); + ptrdiff_t disp = tcg_ptr_byte_diff(target, src_rx); + if (disp == (int16_t) disp) { - *pc = (*pc & ~0xfffc) | (disp & 0xfffc); + *src_rw = (*src_rw & ~0xfffc) | (disp & 0xfffc); return true; } return false; @@ -673,12 +677,12 @@ static const uint32_t tcg_to_isel[] = { static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { - tcg_insn_unit *target; + const tcg_insn_unit *target; int16_t lo; int32_t hi; value += addend; - target = (tcg_insn_unit *)value; + target = (const tcg_insn_unit *)value; switch (type) { case R_PPC_REL14: @@ -1544,7 +1548,7 @@ static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond, static void tcg_out_bc(TCGContext *s, int bc, TCGLabel *l) { if (l->has_value) { - bc |= reloc_pc14_val(s->code_ptr, l->u.value_ptr); + bc |= reloc_pc14_val(tcg_splitwx_to_rx(s->code_ptr), l->u.value_ptr); } else { tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, l, 0); } @@ -1997,7 +2001,8 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, label->datahi_reg = datahi_reg; label->addrlo_reg = addrlo_reg; label->addrhi_reg = addrhi_reg; - label->raddr = raddr; + /* TODO: Cast goes away when all hosts converted */ + label->raddr = (void *)tcg_splitwx_to_rx(raddr); label->label_ptr[0] = lptr; } @@ -2007,7 +2012,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) MemOp opc = get_memop(oi); TCGReg hi, lo, arg = TCG_REG_R3; - if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) { + if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } @@ -2055,7 +2060,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) MemOp s_bits = opc & MO_SIZE; TCGReg hi, lo, arg = TCG_REG_R3; - if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) { + if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } @@ -2306,10 +2311,10 @@ static void tcg_target_qemu_prologue(TCGContext *s) int i; #ifdef _CALL_AIX - void **desc = (void **)s->code_ptr; - desc[0] = desc + 2; /* entry point */ - desc[1] = 0; /* environment pointer */ - s->code_ptr = (void *)(desc + 2); /* skip over descriptor */ + const void **desc = (const void **)s->code_ptr; + desc[0] = tcg_splitwx_to_rx(desc + 2); /* entry point */ + desc[1] = 0; /* environment pointer */ + s->code_ptr = (void *)(desc + 2); /* skip over descriptor */ #endif tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE, @@ -2341,7 +2346,8 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out32(s, BCCTR | BO_ALWAYS); /* Epilogue */ - tcg_code_gen_epilogue = tb_ret_addr = s->code_ptr; + /* TODO: Cast goes away when all hosts converted */ + tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET); for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { @@ -2362,7 +2368,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, switch (opc) { case INDEX_op_exit_tb: tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]); - tcg_out_b(s, 0, tb_ret_addr); + tcg_out_b(s, 0, tcg_code_gen_epilogue); break; case INDEX_op_goto_tb: if (s->tb_jmp_insn_offset) { @@ -2410,7 +2416,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, uint32_t insn = B; if (l->has_value) { - insn |= reloc_pc24_val(s->code_ptr, l->u.value_ptr); + insn |= reloc_pc24_val(tcg_splitwx_to_rx(s->code_ptr), + l->u.value_ptr); } else { tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, l, 0); } From patchwork Thu Jan 7 20:14:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358264 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp784696jai; Thu, 7 Jan 2021 12:28:28 -0800 (PST) X-Google-Smtp-Source: ABdhPJwefrwe90Zqbtbu/+yUfe6s+eifpk3LpHxQoEb5C8ZUdbwNuC6EOmnkfgvgMzdeRjCI+ava X-Received: by 2002:a25:cb88:: with SMTP id b130mr713140ybg.433.1610051308246; Thu, 07 Jan 2021 12:28:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610051308; cv=none; d=google.com; s=arc-20160816; b=xvSMN4iHgmgkB2PGMfXLFTV49Nc3pOnZKauKxEhnCUPlenUsshz1pzMUTl9zP/tj3/ aWwDU7xeGrjPKxOnD6/z/cQ/Yy+vmuHliH+b+ARizKwpBQeYAN7al8UW+8Y4f2J9c6jc O9fIMZm466R2IX6wEr8pcm+kO0aah9smNPvLsYwFA9garehfebvef2h9Tm260v7A3+X5 lzhu77N9bf66GwMBc9BrpbZ2NPea/2Ds9twSe8Zn2h0/QOh5Wlx/S63qH0+nB5iT/HqJ gx5+nPDwRFTLdf54pxL9Hr/ha9fDdSe9+9TN06IdLQGd5hk9YtPHyKtefv7pL9aO6UJ0 gI4A== ARC-Message-Signature: i=1; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 34/47] tcg/sparc: Use tcg_tbrel_diff Date: Thu, 7 Jan 2021 10:14:35 -1000 Message-Id: <20210107201448.1152301-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c.inc | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index d599ae27b5..8f04fdf981 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -440,7 +440,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, /* A 13-bit constant relative to the TB. */ if (!in_prologue && USE_REG_TB) { - test = arg - (uintptr_t)s->code_gen_ptr; + test = tcg_tbrel_diff(s, (void *)arg); if (check_fit_ptr(test, 13)) { tcg_out_arithi(s, ret, TCG_REG_TB, test, ARITH_ADD); return; @@ -537,15 +537,15 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, return false; } -static void tcg_out_ld_ptr(TCGContext *s, TCGReg ret, uintptr_t arg) +static void tcg_out_ld_ptr(TCGContext *s, TCGReg ret, const void *arg) { - intptr_t diff = arg - (uintptr_t)s->code_gen_ptr; + intptr_t diff = tcg_tbrel_diff(s, arg); if (USE_REG_TB && check_fit_ptr(diff, 13)) { tcg_out_ld(s, TCG_TYPE_PTR, ret, TCG_REG_TB, diff); return; } - tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ff); - tcg_out_ld(s, TCG_TYPE_PTR, ret, ret, arg & 0x3ff); + tcg_out_movi(s, TCG_TYPE_PTR, ret, (uintptr_t)arg & ~0x3ff); + tcg_out_ld(s, TCG_TYPE_PTR, ret, ret, (uintptr_t)arg & 0x3ff); } static inline void tcg_out_sety(TCGContext *s, TCGReg rs) @@ -1313,7 +1313,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_movi_imm13(s, TCG_REG_O0, a0); break; } else if (USE_REG_TB) { - intptr_t tb_diff = a0 - (uintptr_t)s->code_gen_ptr; + intptr_t tb_diff = tcg_tbrel_diff(s, (void *)a0); if (check_fit_ptr(tb_diff, 13)) { tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); /* Note that TCG_REG_TB has been unwound to O1. */ @@ -1345,8 +1345,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } } else { /* indirect jump method */ - tcg_out_ld_ptr(s, TCG_REG_TB, - (uintptr_t)(s->tb_jmp_target_addr + a0)); + tcg_out_ld_ptr(s, TCG_REG_TB, s->tb_jmp_target_addr + a0); tcg_out_arithi(s, TCG_REG_G0, TCG_REG_TB, 0, JMPL); tcg_out_nop(s); } From patchwork Thu Jan 7 20:14:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358279 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp791357jai; Thu, 7 Jan 2021 12:40:03 -0800 (PST) X-Google-Smtp-Source: ABdhPJzvI6ldA8tiHE3i3AGXDcuzFANerRjtHhpdIv5tGgV54bxGH+cglYOoqcDCIdwrne+WipBn X-Received: by 2002:a25:348b:: with SMTP id b133mr988391yba.282.1610052003612; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 35/47] tcg/sparc: Support split-wx code generation Date: Thu, 7 Jan 2021 10:14:36 -1000 Message-Id: <20210107201448.1152301-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.h | 2 +- tcg/sparc/tcg-target.c.inc | 24 +++++++++++++----------- 2 files changed, 14 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 6f6cefaa15..6426e24f17 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -172,6 +172,6 @@ extern bool use_vis3_instructions; void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_SUPPORT_MIRROR 0 +#define TCG_TARGET_SUPPORT_MIRROR 1 #endif diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 8f04fdf981..182124b96c 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -291,14 +291,15 @@ static inline int check_fit_i32(int32_t val, unsigned int bits) # define check_fit_ptr check_fit_i32 #endif -static bool patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(tcg_insn_unit *src_rw, int type, intptr_t value, intptr_t addend) { - uint32_t insn = *code_ptr; + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); + uint32_t insn = *src_rw; intptr_t pcrel; value += addend; - pcrel = tcg_ptr_byte_diff((tcg_insn_unit *)value, code_ptr); + pcrel = tcg_ptr_byte_diff((tcg_insn_unit *)value, src_rx); switch (type) { case R_SPARC_WDISP16: @@ -315,7 +316,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, g_assert_not_reached(); } - *code_ptr = insn; + *src_rw = insn; return true; } @@ -868,8 +869,8 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) } #ifdef CONFIG_SOFTMMU -static tcg_insn_unit *qemu_ld_trampoline[16]; -static tcg_insn_unit *qemu_st_trampoline[16]; +static const tcg_insn_unit *qemu_ld_trampoline[16]; +static const tcg_insn_unit *qemu_st_trampoline[16]; static void emit_extend(TCGContext *s, TCGReg r, int op) { @@ -930,7 +931,7 @@ static void build_trampolines(TCGContext *s) while ((uintptr_t)s->code_ptr & 15) { tcg_out_nop(s); } - qemu_ld_trampoline[i] = s->code_ptr; + qemu_ld_trampoline[i] = tcg_splitwx_to_rx(s->code_ptr); if (SPARC64 || TARGET_LONG_BITS == 32) { ra = TCG_REG_O3; @@ -958,7 +959,7 @@ static void build_trampolines(TCGContext *s) while ((uintptr_t)s->code_ptr & 15) { tcg_out_nop(s); } - qemu_st_trampoline[i] = s->code_ptr; + qemu_st_trampoline[i] = tcg_splitwx_to_rx(s->code_ptr); if (SPARC64) { emit_extend(s, TCG_REG_O2, i); @@ -1038,7 +1039,8 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_nop(s); /* Epilogue for goto_ptr. */ - tcg_code_gen_epilogue = s->code_ptr; + /* TODO: Cast goes away when all hosts converted */ + tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); /* delay slot */ tcg_out_movi_imm13(s, TCG_REG_O0, 0); @@ -1163,7 +1165,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, #ifdef CONFIG_SOFTMMU unsigned memi = get_mmuidx(oi); TCGReg addrz, param; - tcg_insn_unit *func; + const tcg_insn_unit *func; tcg_insn_unit *label_ptr; addrz = tcg_out_tlb_load(s, addr, memi, memop, @@ -1245,7 +1247,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr, #ifdef CONFIG_SOFTMMU unsigned memi = get_mmuidx(oi); TCGReg addrz, param; - tcg_insn_unit *func; + const tcg_insn_unit *func; tcg_insn_unit *label_ptr; addrz = tcg_out_tlb_load(s, addr, memi, memop, From patchwork Thu Jan 7 20:14:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358290 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp796593jai; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 36/47] tcg/s390: Use tcg_tbrel_diff Date: Thu, 7 Jan 2021 10:14:37 -1000 Message-Id: <20210107201448.1152301-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use tcg_tbrel_diff when we need a displacement to a label, and with a NULL argument when we need the normalizing addend. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.c.inc | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index 1444914428..e4c61fc014 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -630,7 +630,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, return; } } else if (USE_REG_TB && !in_prologue) { - ptrdiff_t off = sval - (uintptr_t)s->code_gen_ptr; + ptrdiff_t off = tcg_tbrel_diff(s, (void *)sval); if (off == sextract64(off, 0, 20)) { /* This is certain to be an address within TB, and therefore OFF will be negative; don't try RX_LA. */ @@ -655,7 +655,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, } else if (USE_REG_TB && !in_prologue) { tcg_out_insn(s, RXY, LG, ret, TCG_REG_TB, TCG_REG_NONE, 0); new_pool_label(s, sval, R_390_20, s->code_ptr - 2, - -(intptr_t)s->code_gen_ptr); + tcg_tbrel_diff(s, NULL)); } else { TCGReg base = ret ? ret : TCG_TMP0; tcg_out_insn(s, RIL, LARL, base, 0); @@ -746,7 +746,7 @@ static void tcg_out_ld_abs(TCGContext *s, TCGType type, TCGReg dest, void *abs) } } if (USE_REG_TB) { - ptrdiff_t disp = abs - (void *)s->code_gen_ptr; + ptrdiff_t disp = tcg_tbrel_diff(s, abs); if (disp == sextract64(disp, 0, 20)) { tcg_out_ld(s, type, dest, TCG_REG_TB, disp); return; @@ -956,7 +956,7 @@ static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) if (!maybe_out_small_movi(s, type, TCG_TMP0, val)) { tcg_out_insn(s, RXY, NG, dest, TCG_REG_TB, TCG_REG_NONE, 0); new_pool_label(s, val & valid, R_390_20, s->code_ptr - 2, - -(intptr_t)s->code_gen_ptr); + tcg_tbrel_diff(s, NULL)); return; } } else { @@ -1015,7 +1015,7 @@ static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) } else if (USE_REG_TB) { tcg_out_insn(s, RXY, OG, dest, TCG_REG_TB, TCG_REG_NONE, 0); new_pool_label(s, val, R_390_20, s->code_ptr - 2, - -(intptr_t)s->code_gen_ptr); + tcg_tbrel_diff(s, NULL)); } else { /* Perform the OR via sequential modifications to the high and low parts. Do this via recursion to handle 16-bit vs 32-bit @@ -1050,7 +1050,7 @@ static void tgen_xori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) } else if (USE_REG_TB) { tcg_out_insn(s, RXY, XG, dest, TCG_REG_TB, TCG_REG_NONE, 0); new_pool_label(s, val, R_390_20, s->code_ptr - 2, - -(intptr_t)s->code_gen_ptr); + tcg_tbrel_diff(s, NULL)); } else { /* Perform the xor by parts. */ tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM); @@ -1108,12 +1108,12 @@ static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, op = (is_unsigned ? RXY_CLY : RXY_CY); tcg_out_insn_RXY(s, op, r1, TCG_REG_TB, TCG_REG_NONE, 0); new_pool_label(s, (uint32_t)c2, R_390_20, s->code_ptr - 2, - 4 - (intptr_t)s->code_gen_ptr); + 4 - tcg_tbrel_diff(s, NULL)); } else { op = (is_unsigned ? RXY_CLG : RXY_CG); tcg_out_insn_RXY(s, op, r1, TCG_REG_TB, TCG_REG_NONE, 0); new_pool_label(s, c2, R_390_20, s->code_ptr - 2, - -(intptr_t)s->code_gen_ptr); + tcg_tbrel_diff(s, NULL)); } goto exit; } else { From patchwork Thu Jan 7 20:14:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358291 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp797617jai; Thu, 7 Jan 2021 12:51:01 -0800 (PST) X-Google-Smtp-Source: ABdhPJwo5ZO+ROZv7+J1+xC2NP0QTbrdBUMjlexP6MhCtHGnbbU6oV3LBn2Wmy81Fwzlzq5IgZIy X-Received: by 2002:a25:6c05:: with SMTP id h5mr955819ybc.450.1610052661134; Thu, 07 Jan 2021 12:51:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610052661; cv=none; d=google.com; s=arc-20160816; b=YonYZZh5IjDJrpPnCHuGavuUmkE1LapotvUo8sgXrDXknufMWwHiBpaoFCQeNYXgSk uhMAWpWk684eQ9Q4j2YsNl5mqa0sUVUCGliSPYamtYQxDfChZvjaG0yLE+NbP8+/mIEN KIt34E2Mia49fsk+ekqRGR60bGyotd3Zbnc66pZS3QFJdHDom59z1CnG8Som3udhb+gM vmjTDU1Qt1qw82OKPr0QPP2ow0HOavUaTze96BOHkp5uoR310TGyfVfy+deGvYAzYyjx a9qjBoPaes6XlDgbx++J7hMDgfR6ahLeslTNAhOOC5SkEkCd82Zu9DYhMkWMHdTg3MCC zkDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=XwAGDhPsMBTlCDYICLuTcDF1WAEZQ1i2iAFKQ493O/8=; b=p+IWmOnWNA8B2gweKXC/qOlVaC5ZYyGlZKPb4tu8eItDVtr0PViw0cDWVVZeHHRyIZ Xh9Es4gh5QhOz6Qd/YdMSDVicDFJotkxV7qJIpqhUTIsZJJBBzAl3JX0ipbs9L5oaSCi bd7mjFyWcpZnEG6H8EtFdgVwjXS1fWK51LM1aC9VpN+80EC7GN6uYzWCRgdMvuO5nkNu zFOZiQgf/tLfpz+loqD2V05Mdrrl5jb8sMsSjdRh7yMJSC4XWsJ1HIdMNfkHYmoi1EXo S6kGg1i3zoL0nYTV/ITBI92vjYhK5U5WIWwtvXxdenRP/pRNuYOV27AcAO/Q6y6mgh03 Ptbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O2UId8To; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 37/47] tcg/s390: Support split-wx code generation Date: Thu, 7 Jan 2021 10:14:38 -1000 Message-Id: <20210107201448.1152301-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.h | 2 +- tcg/s390/tcg-target.c.inc | 69 +++++++++++++++++---------------------- 2 files changed, 31 insertions(+), 40 deletions(-) -- 2.25.1 diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index b8f4296e4b..4edcb06044 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -159,6 +159,6 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_SUPPORT_MIRROR 0 +#define TCG_TARGET_SUPPORT_MIRROR 1 #endif diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index e4c61fc014..582a8ef941 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -363,36 +363,37 @@ static void * const qemu_st_helpers[16] = { }; #endif -static tcg_insn_unit *tb_ret_addr; +static const tcg_insn_unit *tb_ret_addr; uint64_t s390_facilities; -static bool patch_reloc(tcg_insn_unit *code_ptr, int type, +static bool patch_reloc(tcg_insn_unit *src_rw, int type, intptr_t value, intptr_t addend) { + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); intptr_t pcrel2; uint32_t old; value += addend; - pcrel2 = (tcg_insn_unit *)value - code_ptr; + pcrel2 = (tcg_insn_unit *)value - src_rx; switch (type) { case R_390_PC16DBL: if (pcrel2 == (int16_t)pcrel2) { - tcg_patch16(code_ptr, pcrel2); + tcg_patch16(src_rw, pcrel2); return true; } break; case R_390_PC32DBL: if (pcrel2 == (int32_t)pcrel2) { - tcg_patch32(code_ptr, pcrel2); + tcg_patch32(src_rw, pcrel2); return true; } break; case R_390_20: if (value == sextract64(value, 0, 20)) { - old = *(uint32_t *)code_ptr & 0xf00000ff; + old = *(uint32_t *)src_rw & 0xf00000ff; old |= ((value & 0xfff) << 16) | ((value & 0xff000) >> 4); - tcg_patch32(code_ptr, old); + tcg_patch32(src_rw, old); return true; } break; @@ -730,7 +731,8 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, } /* load data from an absolute host address */ -static void tcg_out_ld_abs(TCGContext *s, TCGType type, TCGReg dest, void *abs) +static void tcg_out_ld_abs(TCGContext *s, TCGType type, + TCGReg dest, const void *abs) { intptr_t addr = (intptr_t)abs; @@ -1304,7 +1306,7 @@ static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src, static void tgen_gotoi(TCGContext *s, int cc, const tcg_insn_unit *dest) { - ptrdiff_t off = dest - s->code_ptr; + ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1; if (off == (int16_t)off) { tcg_out_insn(s, RI, BRC, cc, off); } else if (off == (int32_t)off) { @@ -1333,34 +1335,18 @@ static void tgen_branch(TCGContext *s, int cc, TCGLabel *l) static void tgen_compare_branch(TCGContext *s, S390Opcode opc, int cc, TCGReg r1, TCGReg r2, TCGLabel *l) { - intptr_t off = 0; - - if (l->has_value) { - off = l->u.value_ptr - s->code_ptr; - tcg_debug_assert(off == (int16_t)off); - } else { - tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); - } - + tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); tcg_out16(s, (opc & 0xff00) | (r1 << 4) | r2); - tcg_out16(s, off); + tcg_out16(s, 0); tcg_out16(s, cc << 12 | (opc & 0xff)); } static void tgen_compare_imm_branch(TCGContext *s, S390Opcode opc, int cc, TCGReg r1, int i2, TCGLabel *l) { - tcg_target_long off = 0; - - if (l->has_value) { - off = l->u.value_ptr - s->code_ptr; - tcg_debug_assert(off == (int16_t)off); - } else { - tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); - } - + tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); tcg_out16(s, (opc & 0xff00) | (r1 << 4) | cc); - tcg_out16(s, off); + tcg_out16(s, 0); tcg_out16(s, (i2 << 8) | (opc & 0xff)); } @@ -1417,7 +1403,7 @@ static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c, static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest) { - ptrdiff_t off = dest - s->code_ptr; + ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1; if (off == (int32_t)off) { tcg_out_insn(s, RIL, BRASL, TCG_REG_R14, off); } else { @@ -1601,7 +1587,8 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, label->oi = oi; label->datalo_reg = data; label->addrlo_reg = addr; - label->raddr = raddr; + /* TODO: Cast goes away when all hosts converted */ + label->raddr = (void *)tcg_splitwx_to_rx(raddr); label->label_ptr[0] = label_ptr; } @@ -1613,7 +1600,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) MemOp opc = get_memop(oi); if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, - (intptr_t)s->code_ptr, 2)) { + (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { return false; } @@ -1638,7 +1625,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) MemOp opc = get_memop(oi); if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, - (intptr_t)s->code_ptr, 2)) { + (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { return false; } @@ -1766,7 +1753,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_goto_tb: a0 = args[0]; if (s->tb_jmp_insn_offset) { - /* branch displacement must be aligned for atomic patching; + /* + * branch displacement must be aligned for atomic patching; * see if we need to add extra nop before branch */ if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) { @@ -1779,7 +1767,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } else { /* load address stored at s->tb_jmp_target_addr + a0 */ tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_REG_TB, - s->tb_jmp_target_addr + a0); + tcg_splitwx_to_rx(s->tb_jmp_target_addr + a0)); /* and go there */ tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_TB); } @@ -1789,8 +1777,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, TCG_REG_TB to the beginning of this TB. */ if (USE_REG_TB) { int ofs = -tcg_current_code_size(s); - assert(ofs == (int16_t)ofs); - tcg_out_insn(s, RI, AGHI, TCG_REG_TB, ofs); + /* All TB are restricted to 64KiB by unwind info. */ + tcg_debug_assert(ofs == sextract64(ofs, 0, 20)); + tcg_out_insn(s, RXY, LAY, TCG_REG_TB, + TCG_REG_TB, TCG_REG_NONE, ofs); } break; @@ -2561,11 +2551,12 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - tcg_code_gen_epilogue = s->code_ptr; + /* TODO: Cast goes away when all hosts converted */ + tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, 0); /* TB epilogue */ - tb_ret_addr = s->code_ptr; + tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); /* lmg %r6,%r15,fs+48(%r15) (restore registers) */ tcg_out_insn(s, RXY, LMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, From patchwork Thu Jan 7 20:14:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358293 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp799711jai; Thu, 7 Jan 2021 12:54:50 -0800 (PST) X-Google-Smtp-Source: ABdhPJy5gUVp7dBop/ojNRaVxX93RzAl43xCvBVnfaUlPoP896C4FSCLNoD+dwtqZBpYAQWmiEL4 X-Received: by 2002:a25:2d68:: with SMTP id s40mr972821ybe.163.1610052890262; Thu, 07 Jan 2021 12:54:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610052890; cv=none; d=google.com; s=arc-20160816; b=ihDjflQYKANFStbI79xSB9ILhe/Oy893Fr0+iNi47OLAdIY+LIZVS37gBJH7vCsY/B +W0IQiUEoInYaxE3sHCu/ksqYelJv4rmSx0CgahDB4GIbxKesZSk6XG/VYAHbE3czIdq vbBexiKsNY/Ia9kacuJporISkD70qLMmuwJmAIRjE4bqeDA5SaCOcqMshrBiGtYqhQZ/ 23Nm90YrGd8w4pJdMNOWIhQQ+vFMo7lxcmlYp9yB3m9QhrTNgCrCjXRlW9ffvaZsCLT9 5ZURmru9cvc+mpqXTJzBKNXpsITD/5MIUbMwZpfk4SS9+dZXqnGoMbHADMjdtA2fOM4q hU5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=sam4hUV/EzcXgGAJgfUtLyaqNJNq9uqdrP2iGsKVsYI=; b=eXsVv6IBilrSUfm4KmauOr5reMIOTBIGILq0GcP4Vv4usvNeoletDpfMu3YLzAwxWC QkcNwICD21EOw4fGNQnYA4WafLFMQxMxO2PVJ0K13T4IXqwJ12OphYAk1JJScIY1Rr5+ rh6iCG8ET1QV+9BBoEFrL5tAZuwKclJjJFP0+B/TKv+X3FVtmz6aj+D6kEj0cxIvgmlS 8Dj793NvC6s8uW5R6INfzqYYnTuW45X/pbat68FX7qqLRIJkqkY131/QRqzDoNqJKBcz s1c6RZfgrLSbPOoFocSf2h64aE1d3aj13FQit88cwvoB8vjUi38BAc9KQowXx6r0ujpl PGog== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=skTYE0F0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 38/47] tcg/riscv: Fix branch range checks Date: Thu, 7 Jan 2021 10:14:39 -1000 Message-Id: <20210107201448.1152301-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The offset even checks were folded into the range check incorrectly. By offsetting by 1, and not decrementing the width, we silently allowed out of range branches. Assert that the offset is always even instead. Move tcg_out_goto down into the CONFIG_SOFTMMU block so that it is not unused. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) -- 2.25.1 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 0518595742..5b4c500a4b 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -429,7 +429,8 @@ static bool reloc_sbimm12(tcg_insn_unit *code_ptr, tcg_insn_unit *target) { intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; - if (offset == sextreg(offset, 1, 12) << 1) { + tcg_debug_assert((offset & 1) == 0); + if (offset == sextreg(offset, 0, 12)) { code_ptr[0] |= encode_sbimm12(offset); return true; } @@ -441,7 +442,8 @@ static bool reloc_jimm20(tcg_insn_unit *code_ptr, tcg_insn_unit *target) { intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; - if (offset == sextreg(offset, 1, 20) << 1) { + tcg_debug_assert((offset & 1) == 0); + if (offset == sextreg(offset, 0, 20)) { code_ptr[0] |= encode_ujimm20(offset); return true; } @@ -854,28 +856,21 @@ static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, g_assert_not_reached(); } -static inline void tcg_out_goto(TCGContext *s, tcg_insn_unit *target) -{ - ptrdiff_t offset = tcg_pcrel_diff(s, target); - tcg_debug_assert(offset == sextreg(offset, 1, 20) << 1); - tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, offset); -} - static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) { TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; ptrdiff_t offset = tcg_pcrel_diff(s, arg); int ret; - if (offset == sextreg(offset, 1, 20) << 1) { + tcg_debug_assert((offset & 1) == 0); + if (offset == sextreg(offset, 0, 20)) { /* short jump: -2097150 to 2097152 */ tcg_out_opc_jump(s, OPC_JAL, link, offset); - } else if (TCG_TARGET_REG_BITS == 32 || - offset == sextreg(offset, 1, 31) << 1) { + } else if (TCG_TARGET_REG_BITS == 32 || offset == (int32_t)offset) { /* long jump: -2147483646 to 2147483648 */ tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0); tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0); - ret = reloc_call(s->code_ptr - 2, arg);\ + ret = reloc_call(s->code_ptr - 2, arg); tcg_debug_assert(ret == true); } else if (TCG_TARGET_REG_BITS == 64) { /* far jump: 64-bit */ @@ -962,6 +957,13 @@ QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); +static void tcg_out_goto(TCGContext *s, tcg_insn_unit *target) +{ + tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0); + bool ok = reloc_jimm20(s->code_ptr - 1, target); + tcg_debug_assert(ok); +} + static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, TCGReg addrh, TCGMemOpIdx oi, tcg_insn_unit **label_ptr, bool is_load) From patchwork Thu Jan 7 20:14:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358287 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp795698jai; Thu, 7 Jan 2021 12:47:37 -0800 (PST) X-Google-Smtp-Source: ABdhPJwffrvud0XkBOIbXZUF9GVezjcGjZw0DBnWMmzyN1Vx4D4aPiBID2GbltaEBJ5/gMMqHmRX X-Received: by 2002:a25:bd07:: with SMTP id f7mr924760ybk.159.1610052457623; Thu, 07 Jan 2021 12:47:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610052457; cv=none; d=google.com; s=arc-20160816; b=RBGOGOCh+0LBXG+2dRSOpjOAHM7Cyn/CS0YLU+DOzfMBKDq4Vo4Ndp2rYeFdkx1Vxo Je48vcvIQue0LV2+lvU5Y/7Q0UbaNqPiM6WgaLwh+pVDlyxFm6MM2hsjZJmu81OIAug8 5nmrDL4qCrGbRYx4kSCbg8Yj7xxcCf9+vgFdiHJ2e/T5XRn228s0F82WOp8FQPdXBxaH brrEzQpWVHCygNeyAGfudAfo0es+BizjN1uDfqaXZflPGh7q8OcT4YJ6NlDVyBCYw58O lASe9R89AmBw/w0GkuqsS/mDVaRCKQyOkePmAr8hM4v7GGWuNDen9TSFyhcUU0q3xrsy wxVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=2ceeCrB5ObxXqiOq+gfMl3DKYMpwFGb7NLNLd4oEq1k=; b=WH+0WuMmCyJtmAqVewRIGgQytjWnKWDwpflEzSZpnqIJcRLq1Wq59htpCXZsUBd3KU THbxSfdQpaaPGsXd1qJAo813XAVGtE/Vf6SSKi3xUf5yO8dxRRxUB2jq/39jniAcFgIB DrwZjQ1TZQSsE0/jcF8R5/iulsIOpbfy3TL3KK7VvWTqCnFeyVLiEBbRmaP9fiongPrY k8mw2s0OKYLVLQihFZhqK0P/hszhnxvOL0ST8vjv5cIU5INAGV3EDgD52ctPmY/AERy/ LSgccVxaeq7INL4KFw3jYDTC0LuZHhsQ6ugGnEisp54ELZKLpLmIIM0eFXGLi1EDuZUk YWVg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N9pVmwDP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 39/47] tcg/riscv: Remove branch-over-branch fallback Date: Thu, 7 Jan 2021 10:14:40 -1000 Message-Id: <20210107201448.1152301-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since 7ecd02a06f8, we are prepared to re-start code generation with a smaller TB if a relocation is out of range. We no longer need to leave a nop in the stream Just In Case. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 56 ++++---------------------------------- 1 file changed, 6 insertions(+), 50 deletions(-) -- 2.25.1 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 5b4c500a4b..34bee9c5a7 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -469,43 +469,16 @@ static bool reloc_call(tcg_insn_unit *code_ptr, const tcg_insn_unit *target) static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { - uint32_t insn = *code_ptr; - intptr_t diff; - bool short_jmp; - tcg_debug_assert(addend == 0); - switch (type) { case R_RISCV_BRANCH: - diff = value - (uintptr_t)code_ptr; - short_jmp = diff == sextreg(diff, 0, 12); - if (short_jmp) { - return reloc_sbimm12(code_ptr, (tcg_insn_unit *)value); - } else { - /* Invert the condition */ - insn = insn ^ (1 << 12); - /* Clear the offset */ - insn &= 0x01fff07f; - /* Set the offset to the PC + 8 */ - insn |= encode_sbimm12(8); - - /* Move forward */ - code_ptr[0] = insn; - - /* Overwrite the NOP with jal x0,value */ - diff = value - (uintptr_t)(code_ptr + 1); - insn = encode_uj(OPC_JAL, TCG_REG_ZERO, diff); - code_ptr[1] = insn; - - return true; - } - break; + return reloc_sbimm12(code_ptr, (tcg_insn_unit *)value); case R_RISCV_JAL: return reloc_jimm20(code_ptr, (tcg_insn_unit *)value); case R_RISCV_CALL: return reloc_call(code_ptr, (tcg_insn_unit *)value); default: - tcg_abort(); + g_assert_not_reached(); } } @@ -779,21 +752,8 @@ static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, arg2 = t; } - if (l->has_value) { - intptr_t diff = tcg_pcrel_diff(s, l->u.value_ptr); - if (diff == sextreg(diff, 0, 12)) { - tcg_out_opc_branch(s, op, arg1, arg2, diff); - } else { - /* Invert the conditional branch. */ - tcg_out_opc_branch(s, op ^ (1 << 12), arg1, arg2, 8); - tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, diff - 4); - } - } else { - tcg_out_reloc(s, s->code_ptr, R_RISCV_BRANCH, l, 0); - tcg_out_opc_branch(s, op, arg1, arg2, 0); - /* NOP to allow patching later */ - tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0); - } + tcg_out_reloc(s, s->code_ptr, R_RISCV_BRANCH, l, 0); + tcg_out_opc_branch(s, op, arg1, arg2, 0); } static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, @@ -1009,8 +969,6 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, /* Compare masked address with the TLB entry. */ label_ptr[0] = s->code_ptr; tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); - /* NOP to allow patching later */ - tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0); /* TLB Hit - translate address using addend. */ if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { @@ -1054,8 +1012,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) } /* resolve label address */ - if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, - (intptr_t) s->code_ptr, 0)) { + if (!reloc_sbimm12(l->label_ptr[0], s->code_ptr)) { return false; } @@ -1089,8 +1046,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) } /* resolve label address */ - if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, - (intptr_t) s->code_ptr, 0)) { + if (!reloc_sbimm12(l->label_ptr[0], s->code_ptr)) { return false; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.15.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:15:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 40/47] tcg/riscv: Support split-wx code generation Date: Thu, 7 Jan 2021 10:14:41 -1000 Message-Id: <20210107201448.1152301-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.h | 2 +- tcg/riscv/tcg-target.c.inc | 41 +++++++++++++++++++++----------------- 2 files changed, 24 insertions(+), 19 deletions(-) -- 2.25.1 diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 6263af4dd1..c50ecf4dab 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -171,6 +171,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS #define TCG_TARGET_HAS_MEMORY_BSWAP 0 -#define TCG_TARGET_SUPPORT_MIRROR 0 +#define TCG_TARGET_SUPPORT_MIRROR 1 #endif diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 34bee9c5a7..4d595b01d6 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -425,41 +425,44 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count) * Relocations */ -static bool reloc_sbimm12(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +static bool reloc_sbimm12(tcg_insn_unit *src_rw, const tcg_insn_unit *target) { - intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); + intptr_t offset = (intptr_t)target - (intptr_t)src_rx; tcg_debug_assert((offset & 1) == 0); if (offset == sextreg(offset, 0, 12)) { - code_ptr[0] |= encode_sbimm12(offset); + *src_rw |= encode_sbimm12(offset); return true; } return false; } -static bool reloc_jimm20(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +static bool reloc_jimm20(tcg_insn_unit *src_rw, const tcg_insn_unit *target) { - intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); + intptr_t offset = (intptr_t)target - (intptr_t)src_rx; tcg_debug_assert((offset & 1) == 0); if (offset == sextreg(offset, 0, 20)) { - code_ptr[0] |= encode_ujimm20(offset); + *src_rw |= encode_ujimm20(offset); return true; } return false; } -static bool reloc_call(tcg_insn_unit *code_ptr, const tcg_insn_unit *target) +static bool reloc_call(tcg_insn_unit *src_rw, const tcg_insn_unit *target) { - intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); + intptr_t offset = (intptr_t)target - (intptr_t)src_rx; int32_t lo = sextreg(offset, 0, 12); int32_t hi = offset - lo; if (offset == hi + lo) { - code_ptr[0] |= encode_uimm20(hi); - code_ptr[1] |= encode_imm12(lo); + src_rw[0] |= encode_uimm20(hi); + src_rw[1] |= encode_imm12(lo); return true; } @@ -532,7 +535,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, if (tmp == (int32_t)tmp) { tcg_out_opc_upper(s, OPC_AUIPC, rd, 0); tcg_out_opc_imm(s, OPC_ADDI, rd, rd, 0); - ret = reloc_call(s->code_ptr - 2, (tcg_insn_unit *)val); + ret = reloc_call(s->code_ptr - 2, (const tcg_insn_unit *)val); tcg_debug_assert(ret == true); return; } @@ -917,7 +920,7 @@ QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); -static void tcg_out_goto(TCGContext *s, tcg_insn_unit *target) +static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) { tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0); bool ok = reloc_jimm20(s->code_ptr - 1, target); @@ -993,7 +996,8 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, label->datahi_reg = datahi; label->addrlo_reg = addrlo; label->addrhi_reg = addrhi; - label->raddr = raddr; + /* TODO: Cast goes away when all hosts converted */ + label->raddr = (void *)tcg_splitwx_to_rx(raddr); label->label_ptr[0] = label_ptr[0]; } @@ -1012,7 +1016,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) } /* resolve label address */ - if (!reloc_sbimm12(l->label_ptr[0], s->code_ptr)) { + if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } @@ -1046,7 +1050,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) } /* resolve label address */ - if (!reloc_sbimm12(l->label_ptr[0], s->code_ptr)) { + if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } @@ -1232,7 +1236,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) #endif } -static tcg_insn_unit *tb_ret_addr; +static const tcg_insn_unit *tb_ret_addr; static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) @@ -1780,11 +1784,12 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); /* Return path for goto_ptr. Set return value to 0 */ - tcg_code_gen_epilogue = s->code_ptr; + /* TODO: Cast goes away when all hosts converted */ + tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO); /* TB epilogue */ - tb_ret_addr = s->code_ptr; + tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], TCG_REG_SP, SAVE_OFS + i * REG_SIZE); From patchwork Thu Jan 7 20:14:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358295 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp800894jai; Thu, 7 Jan 2021 12:57:08 -0800 (PST) X-Google-Smtp-Source: ABdhPJwd7Jma8bRHkRRkOMw1gtSBQfpRSNb5obqx4QEMp4KKeYXP+vgbZn2QOTKjCglcNoyEFxr2 X-Received: by 2002:a25:c54b:: with SMTP id v72mr1017895ybe.258.1610053027940; Thu, 07 Jan 2021 12:57:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610053027; cv=none; d=google.com; s=arc-20160816; b=Gz18pAMMOZSrHnEQFMCSZ9AJnfJvgxLmSJ/Os7sR921ZTNYYRsicFW2c4IxsxqF/l2 l2kTPQytSIbZbJg/y4dTceGaxrBuIfx6K3+zTklOx7IKjJDJ1ZwmnnLipJ0ALkU8anwL lX0TqYDhZbfLWhP6ttGDn2z3x22Yc8vmw7ig7DHF/SaQG0pmE8Xcg7pEKSsmQORm38Cl prsQLU35LnIkE/huJYNuTzxmJvqFAnpU0QlJg5jSdvnrB//2Q5gFyxGuUmVohS7zlvwx qJIbDNmJfioCtw3fcL6tuaiZguoH0cLDPTX6hWXwivXi7ivq8H2TcGbZjIwCR5+5C4En YkJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=LaTXN69dgwbs1ISFkqvlbDLmQMLsIvhLpgwyriKzsQg=; b=al5NfxdZrmWZ22Mr27tK1KMGFS+iQYeaG/qkZcMzc7s09Z8YUQdk57s2I6j79PYKTd d+s2WP0H2pAG+zg3J9cUISlZ0Ad6FGAnoUTyHBJVAQWhFhpBYEhMyFSS/85dXJcEtvze veEDgCxC1Bnihlkw5B8LX+vyednJmEVkuI/hpzboCaAJdZSbxAQU8wWmfPnwwZW/2+iE Qh7HNkLctFzaGnbZtql5UakgwVIqACxlx+9VZsLI92o4t1sP1fcnJUOS/mzwT2r7dpZo 66iOZfvIuk3CFZYQaQxDBEC4ihYflpFBdjdXPVYnnxZwXN0ZIYhZzRJfT4IaA4UUYoz6 c5ZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oTLAhLju; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.16.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:16:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 41/47] accel/tcg: Add mips support to alloc_code_gen_buffer_splitwx_memfd Date: Thu, 7 Jan 2021 10:14:42 -1000 Message-Id: <20210107201448.1152301-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Re-use the 256MiB region handling from alloc_code_gen_buffer_anon, and replace that with the shared file mapping. Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 46 ++++++++++++++++++++++++++++++++------- 1 file changed, 38 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index c37718db4d..02e1b05c42 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1137,24 +1137,40 @@ static bool alloc_code_gen_buffer_anon(size_t size, int prot, static bool alloc_code_gen_buffer_splitwx_memfd(size_t size, Error **errp) { - void *buf_rw, *buf_rx; + void *buf_rw = NULL, *buf_rx = MAP_FAILED; int fd = -1; +#ifdef __mips__ + /* Find space for the RX mapping, vs the 256MiB regions. */ + if (!alloc_code_gen_buffer_anon(size, PROT_NONE, + MAP_PRIVATE | MAP_ANONYMOUS | + MAP_NORESERVE, errp)) { + return false; + } + /* The size of the mapping may have been adjusted. */ + size = tcg_ctx->code_gen_buffer_size; + buf_rx = tcg_ctx->code_gen_buffer; +#endif + buf_rw = qemu_memfd_alloc("tcg-jit", size, 0, &fd, errp); if (buf_rw == NULL) { - return false; + goto fail; } +#ifdef __mips__ + void *tmp = mmap(buf_rx, size, PROT_READ | PROT_EXEC, + MAP_SHARED | MAP_FIXED, fd, 0); + if (tmp != buf_rx) { + goto fail_rx; + } +#else buf_rx = mmap(NULL, size, PROT_READ | PROT_EXEC, MAP_SHARED, fd, 0); if (buf_rx == MAP_FAILED) { - error_setg_errno(errp, errno, - "failed to map shared memory for execute"); - munmap(buf_rw, size); - close(fd); - return false; + goto fail_rx; } - close(fd); +#endif + close(fd); tcg_ctx->code_gen_buffer = buf_rw; tcg_ctx->code_gen_buffer_size = size; tcg_splitwx_diff = buf_rx - buf_rw; @@ -1163,6 +1179,20 @@ static bool alloc_code_gen_buffer_splitwx_memfd(size_t size, Error **errp) qemu_madvise(buf_rw, size, QEMU_MADV_HUGEPAGE); qemu_madvise(buf_rx, size, QEMU_MADV_HUGEPAGE); return true; + + fail_rx: + error_setg_errno(errp, errno, "failed to map shared memory for execute"); + fail: + if (buf_rx != MAP_FAILED) { + munmap(buf_rx, size); + } + if (buf_rw) { + munmap(buf_rw, size); + } + if (fd >= 0) { + close(fd); + } + return false; } #endif /* CONFIG_POSIX */ From patchwork Thu Jan 7 20:14:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358294 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp799816jai; Thu, 7 Jan 2021 12:55:02 -0800 (PST) X-Google-Smtp-Source: ABdhPJwV5rRhsnw/gOGTS16ZXb6oYyaLBsPpIA9Q86NfUsCLJH1ChUoj3eL+k3PNzJbXfrN7Qa/P X-Received: by 2002:a25:7c87:: with SMTP id x129mr891413ybc.461.1610052902710; Thu, 07 Jan 2021 12:55:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610052902; cv=none; d=google.com; s=arc-20160816; b=gQw3JvPWKQrxa7kiGNsqjTowP25a07BB/lThTNAvBgMgVOqrXiVqOyluRkKZb+x32l 3EOfWGUnnWZT50+nWOnR/8TEmB378N7J7aGTkYcceCaaBsih5rycy3veSH7Mf35+PipG KNKPaMSB13hqexsCm6WrCA5fUVUU34008eJEor55Y5zk6la+NrWT6jkxWHLytZJKATM3 3NmGJdeUGvm93/4yxb1KysEubvvHZUwMZyEuRcoaSdZZwTESbRujgQacaBEIxKTBBlry G5a30b+YITZ+YntO9jQEaG1LonYHkLy70l+tqb3g1ryPYlcBXiC+o9OBf0JiQrMsI6hi 6/ow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9/TRkK1ohPG7NzFVdGar1E3FliGdhxt5t+NNXefLhVw=; b=ei2d6gKBa9TA2YVGzFBw3Za0FWesbOKbI99xeMI9OyaO/UVSlJMo1wUZeT+sbRyDTm hXe3q1JvMBxWGf6046piBg4eQ/RpHvW2v1n6/0Ek7x/LXktKbx8sWzZVr7xsqAXDQyHl jteXLYHNnsJ6JJQEQCBaJ+kp4gKaV+tUcZF5k4AAVDY5oEneJMHQpuWiqp7likH1TRg/ NFefXxFhvlni8LN7hhBAG+NvQKTDSP/IJtjJyeh4BhjDNOGHGUBtoUee4nIS85JgfV/o XMcbAguPC0hzL3QrMGEQm4bjJ5ww0mdTIT7OC597nr2ma/ZWIyACa2fbvgpFbkjYWbs4 StFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OdBATOSB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.16.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:16:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 42/47] tcg/mips: Do not assert on relocation overflow Date: Thu, 7 Jan 2021 10:14:43 -1000 Message-Id: <20210107201448.1152301-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This target was not updated with 7ecd02a06f8, and so did not allow re-compilation with relocation overflow. Remove reloc_26 and reloc_26_val as unused. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 53 ++++++++++++++------------------------- 1 file changed, 19 insertions(+), 34 deletions(-) -- 2.25.1 diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 52638e920c..37faf1356c 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -144,29 +144,15 @@ static tcg_insn_unit *bswap32_addr; static tcg_insn_unit *bswap32u_addr; static tcg_insn_unit *bswap64_addr; -static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, - const tcg_insn_unit *target) +static bool reloc_pc16(tcg_insn_unit *pc, const tcg_insn_unit *target) { /* Let the compiler perform the right-shift as part of the arithmetic. */ ptrdiff_t disp = target - (pc + 1); - tcg_debug_assert(disp == (int16_t)disp); - return disp & 0xffff; -} - -static inline void reloc_pc16(tcg_insn_unit *pc, const tcg_insn_unit *target) -{ - *pc = deposit32(*pc, 0, 16, reloc_pc16_val(pc, target)); -} - -static inline uint32_t reloc_26_val(tcg_insn_unit *pc, tcg_insn_unit *target) -{ - tcg_debug_assert((((uintptr_t)pc ^ (uintptr_t)target) & 0xf0000000) == 0); - return ((uintptr_t)target >> 2) & 0x3ffffff; -} - -static inline void reloc_26(tcg_insn_unit *pc, tcg_insn_unit *target) -{ - *pc = deposit32(*pc, 0, 26, reloc_26_val(pc, target)); + if (disp == (int16_t)disp) { + *pc = deposit32(*pc, 0, 16, disp); + return true; + } + return false; } static bool patch_reloc(tcg_insn_unit *code_ptr, int type, @@ -174,8 +160,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, { tcg_debug_assert(type == R_MIPS_PC16); tcg_debug_assert(addend == 0); - reloc_pc16(code_ptr, (tcg_insn_unit *)value); - return true; + return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); } #define TCG_CT_CONST_ZERO 0x100 @@ -925,11 +910,7 @@ static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, } tcg_out_opc_br(s, b_opc, arg1, arg2); - if (l->has_value) { - reloc_pc16(s->code_ptr - 1, l->u.value_ptr); - } else { - tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0); - } + tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0); tcg_out_nop(s); } @@ -1316,9 +1297,10 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) int i; /* resolve label address */ - reloc_pc16(l->label_ptr[0], s->code_ptr); - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - reloc_pc16(l->label_ptr[1], s->code_ptr); + if (!reloc_pc16(l->label_ptr[0], s->code_ptr) + || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS + && !reloc_pc16(l->label_ptr[1], s->code_ptr))) { + return false; } i = 1; @@ -1346,7 +1328,9 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) } tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); - reloc_pc16(s->code_ptr - 1, l->raddr); + if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { + return false; + } /* delay slot */ if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) { @@ -1366,9 +1350,10 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) int i; /* resolve label address */ - reloc_pc16(l->label_ptr[0], s->code_ptr); - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - reloc_pc16(l->label_ptr[1], s->code_ptr); + if (!reloc_pc16(l->label_ptr[0], s->code_ptr) + || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS + && !reloc_pc16(l->label_ptr[1], s->code_ptr))) { + return false; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.16.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:16:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 43/47] tcg/mips: Support split-wx code generation Date: Thu, 7 Jan 2021 10:14:44 -1000 Message-Id: <20210107201448.1152301-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 2 +- tcg/mips/tcg-target.c.inc | 43 ++++++++++++++++++++++----------------- 2 files changed, 25 insertions(+), 20 deletions(-) -- 2.25.1 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index fbfe775fb4..ed5c347374 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -201,7 +201,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -#define TCG_TARGET_SUPPORT_MIRROR 0 +#define TCG_TARGET_SUPPORT_MIRROR 1 void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 37faf1356c..a2201bd1dd 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -139,17 +139,18 @@ static const TCGReg tcg_target_call_oarg_regs[2] = { TCG_REG_V1 }; -static tcg_insn_unit *tb_ret_addr; -static tcg_insn_unit *bswap32_addr; -static tcg_insn_unit *bswap32u_addr; -static tcg_insn_unit *bswap64_addr; +static const tcg_insn_unit *tb_ret_addr; +static const tcg_insn_unit *bswap32_addr; +static const tcg_insn_unit *bswap32u_addr; +static const tcg_insn_unit *bswap64_addr; -static bool reloc_pc16(tcg_insn_unit *pc, const tcg_insn_unit *target) +static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) { /* Let the compiler perform the right-shift as part of the arithmetic. */ - ptrdiff_t disp = target - (pc + 1); + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); + ptrdiff_t disp = target - (src_rx + 1); if (disp == (int16_t)disp) { - *pc = deposit32(*pc, 0, 16, disp); + *src_rw = deposit32(*src_rw, 0, 16, disp); return true; } return false; @@ -505,7 +506,7 @@ static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) { uintptr_t dest = (uintptr_t)target; - uintptr_t from = (uintptr_t)s->code_ptr + 4; + uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4; int32_t inst; /* The pc-region branch happens within the 256MB region of @@ -617,7 +618,7 @@ static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg) } } -static void tcg_out_bswap_subr(TCGContext *s, tcg_insn_unit *sub) +static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) { bool ok = tcg_out_opc_jmp(s, OPC_JAL, sub); tcg_debug_assert(ok); @@ -1282,7 +1283,8 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, label->datahi_reg = datahi; label->addrlo_reg = addrlo; label->addrhi_reg = addrhi; - label->raddr = raddr; + /* TODO: Cast goes away when all hosts converted */ + label->raddr = (void *)tcg_splitwx_to_rx(raddr); label->label_ptr[0] = label_ptr[0]; if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { label->label_ptr[1] = label_ptr[1]; @@ -1291,15 +1293,16 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { + const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); TCGMemOpIdx oi = l->oi; MemOp opc = get_memop(oi); TCGReg v0; int i; /* resolve label address */ - if (!reloc_pc16(l->label_ptr[0], s->code_ptr) + if (!reloc_pc16(l->label_ptr[0], tgt_rx) || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS - && !reloc_pc16(l->label_ptr[1], s->code_ptr))) { + && !reloc_pc16(l->label_ptr[1], tgt_rx))) { return false; } @@ -1344,15 +1347,16 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { + const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); TCGMemOpIdx oi = l->oi; MemOp opc = get_memop(oi); MemOp s_bits = opc & MO_SIZE; int i; /* resolve label address */ - if (!reloc_pc16(l->label_ptr[0], s->code_ptr) + if (!reloc_pc16(l->label_ptr[0], tgt_rx) || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS - && !reloc_pc16(l->label_ptr[1], s->code_ptr))) { + && !reloc_pc16(l->label_ptr[1], tgt_rx))) { return false; } @@ -2469,11 +2473,12 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - tcg_code_gen_epilogue = s->code_ptr; + /* TODO: Cast goes away when all hosts converted */ + tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); /* TB epilogue */ - tb_ret_addr = s->code_ptr; + tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], TCG_REG_SP, SAVE_OFS + i * REG_SIZE); @@ -2493,7 +2498,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) /* * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. */ - bswap32_addr = align_code_ptr(s); + bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s)); /* t3 = (ssss)d000 */ tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); /* t1 = 000a */ @@ -2521,7 +2526,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) /* * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. */ - bswap32u_addr = align_code_ptr(s); + bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s)); /* t1 = (0000)000d */ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); /* t3 = 000a */ @@ -2547,7 +2552,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) /* * bswap64 -- 64-bit swap. a0 = abcdefgh */ - bswap64_addr = align_code_ptr(s); + bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s)); /* t3 = h0000000 */ tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); /* t1 = 0000000a */ From patchwork Thu Jan 7 20:14:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358268 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp786661jai; Thu, 7 Jan 2021 12:31:38 -0800 (PST) X-Google-Smtp-Source: ABdhPJxy2mUPKcKYc84qECRiphSJ+65AZmvc8TbnUwO632zB6XWHsPfRe7CJ7iqwSHU/HtIH4z3y X-Received: by 2002:a25:d295:: with SMTP id j143mr967804ybg.20.1610051498571; Thu, 07 Jan 2021 12:31:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610051498; cv=none; d=google.com; s=arc-20160816; b=l00TOdKEjutegDjf5Nqyw8JQvVfQx/9NuBdO30TzoRbXy7GABAWs7UoFNweYkkhNXM K+SPcyNAkKFvFY1xonu1is1T5V8PzvSjFZQvMk31WdyoO2cZ2Lw54RXtqa3z2bJK0ZqA OjH1IBUz1I7UIn29RCXlOoWPQMOkJqLd4rCRGnBynsZ36nkwl9l6uM0NLLrAkDPfYJ8N Wsmcta9rRmrIIxb3034DtjXLZtta8Rw56BiG2jnABVtGJmACgmCFxivK8A49e+izjp99 W6MUKn8KXgC2cN92HEc1PV7LsaP3MdnoVTpUQ6UE8tvVsP6JeS7i6Dj5ek1hLvhv8Vkm D1gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RjsLWt3F7DefhddvmyHDtzHbHX1tk83XD8LIVsXHpX8=; b=UTc5gDEvP8L+ijoFRC503YwCoNF50zvhjq/0rYgOYQe30vmW8xofSo90iCwxywhJ6S D80KN6nruazcsbH2J5rBiHNh4OSMe3ZKFgqPS3ULnQRaCPf7gZRpSs5346M/xyAj3cMX jfpC4M4iUhQyZRmrzONe86OjjJW+VIrprgy/1DXX95+beQyqfw79ZN16wj6kSQztQfoh tAOWPzXtbgucQDDvNYvaVKg5y5tY4MJJW6YUYdM9XgBBCytIRMY/qqJHTFqwa0C3H5d2 ABPQWWsQ9VsuIHFBKWmaL/3VIXAczVUJOTR9fy2YrlZgeKEvCqYwgq70HW/sdgf7M4Gs b/uQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="iF/sgumt"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.16.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:16:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 44/47] tcg/arm: Support split-wx code generation Date: Thu, 7 Jan 2021 10:14:45 -1000 Message-Id: <20210107201448.1152301-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 2 +- tcg/arm/tcg-target.c.inc | 37 +++++++++++++++++++++---------------- 2 files changed, 22 insertions(+), 17 deletions(-) -- 2.25.1 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 494837d128..fdf75ba93f 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -142,6 +142,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_SUPPORT_MIRROR 0 +#define TCG_TARGET_SUPPORT_MIRROR 1 #endif diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 9b9400f164..3d2717aeb0 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -187,29 +187,32 @@ static const uint8_t tcg_cond_to_arm_cond[] = { [TCG_COND_GTU] = COND_HI, }; -static inline bool reloc_pc24(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) { - ptrdiff_t offset = (tcg_ptr_byte_diff(target, code_ptr) - 8) >> 2; + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); + ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) >> 2; + if (offset == sextract32(offset, 0, 24)) { - *code_ptr = (*code_ptr & ~0xffffff) | (offset & 0xffffff); + *src_rw = deposit32(*src_rw, 0, 24, offset); return true; } return false; } -static inline bool reloc_pc13(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +static bool reloc_pc13(tcg_insn_unit *src_rw, const tcg_insn_unit *target) { - ptrdiff_t offset = tcg_ptr_byte_diff(target, code_ptr) - 8; + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); + ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8; if (offset >= -0xfff && offset <= 0xfff) { - tcg_insn_unit insn = *code_ptr; + tcg_insn_unit insn = *src_rw; bool u = (offset >= 0); if (!u) { offset = -offset; } insn = deposit32(insn, 23, 1, u); insn = deposit32(insn, 0, 12, offset); - *code_ptr = insn; + *src_rw = insn; return true; } return false; @@ -221,9 +224,9 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, tcg_debug_assert(addend == 0); if (type == R_ARM_PC24) { - return reloc_pc24(code_ptr, (tcg_insn_unit *)value); + return reloc_pc24(code_ptr, (const tcg_insn_unit *)value); } else if (type == R_ARM_PC13) { - return reloc_pc13(code_ptr, (tcg_insn_unit *)value); + return reloc_pc13(code_ptr, (const tcg_insn_unit *)value); } else { g_assert_not_reached(); } @@ -617,7 +620,7 @@ static void tcg_out_movi32(TCGContext *s, int cond, int rd, uint32_t arg) /* Check for a pc-relative address. This will usually be the TB, or within the TB, which is immediately before the code block. */ - diff = arg - ((intptr_t)s->code_ptr + 8); + diff = tcg_pcrel_diff(s, (void *)arg) - 8; if (diff >= 0) { rot = encode_imm(diff); if (rot >= 0) { @@ -1337,7 +1340,8 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, label->datahi_reg = datahi; label->addrlo_reg = addrlo; label->addrhi_reg = addrhi; - label->raddr = raddr; + /* TODO: Cast goes away when all hosts converted */ + label->raddr = (void *)tcg_splitwx_to_rx(raddr); label->label_ptr[0] = label_ptr; } @@ -1348,7 +1352,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) MemOp opc = get_memop(oi); void *func; - if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) { + if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } @@ -1411,7 +1415,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) TCGMemOpIdx oi = lb->oi; MemOp opc = get_memop(oi); - if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) { + if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } @@ -1762,8 +1766,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGReg base = TCG_REG_PC; tcg_debug_assert(s->tb_jmp_insn_offset == 0); - ptr = (intptr_t)(s->tb_jmp_target_addr + args[0]); - dif = ptr - ((intptr_t)s->code_ptr + 8); + ptr = (intptr_t)tcg_splitwx_to_rx(s->tb_jmp_target_addr + args[0]); + dif = tcg_pcrel_diff(s, (void *)ptr) - 8; dil = sextract32(dif, 0, 12); if (dif != dil) { /* The TB is close, but outside the 12 bits addressable by @@ -2297,7 +2301,8 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - tcg_code_gen_epilogue = s->code_ptr; + /* TODO: Cast goes away when all hosts converted */ + tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0); tcg_out_epilogue(s); } From patchwork Thu Jan 7 20:14:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358269 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp787073jai; Thu, 7 Jan 2021 12:32:18 -0800 (PST) X-Google-Smtp-Source: ABdhPJy4KzKicTUzx8qxUOAMeU1wmzNfB8Qwfga+m0h/5BctwnhVEEWUeAfpPTh5kFzCvJmkFNzY X-Received: by 2002:a25:778c:: with SMTP id s134mr823344ybc.411.1610051538680; Thu, 07 Jan 2021 12:32:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610051538; cv=none; d=google.com; s=arc-20160816; b=Y3k+KfH1rNVbj3Cnjo7NBwNbWY7UVJQR/dEteN7GJHTUCEjM138r4yuk5gwASq2+Fl gtxHl/eR56zWyoRB73VwDNNidUaLi9w1SbxQFSQsz7dqlbmE+/eAis1w4wIBq/gdkdak 7L1KEKgFqD/k1vqucHCuBGvH/pxXy+2zJPbXLBwodseQGlp/htD7GHNl3nSb3vjkfWyt sPQxEZObyRG71Ga4bGf8biWEUhwagx3rGV/QfpYplpiDM+4yNurJrXgUN48oGI0X9FUE w4vUsAeC1tbbTEdtj2/8vTsFeE2VEevjHfagIuLxN5eaZoxTCxg/8H6n2L567VWY3Unb CKVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=gCTNNZGR2Nv/YxZ5iu2Rwl94cKut5s9Wts7t2uaTEAo=; b=mbLBiIc3yU+ncZq4A+L/M8Of04YqgQcCIcbyiL4TQ1wkTCMZwcXMCjpR93nslgH8eW Fyy1/IhOxFvreYuT6K63fs+kM7KBOoXc0fqbJGwATuuIqyoLrXZa5RqGqPnCAlw9bOQg /l9WwYSZNpGl42x0OVC+7uHrFd9NrD2z4YGmU01LYKkiWDTML3surF3UoV/PaoAbWB+U Hf8nB6eB66V8Repkb7Ogl2i/YNiLjkvn9+DJlqYV/uERNKXT1c5ZF1lgEG4ZkudMWfzY jCTQAGWOp8uWbleqNaef7D1szYmNuJzpQRNvTXG/iF+Eu96pQGzXBuvJed4mymxMx4Nc jr/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Jnruojja; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.16.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:16:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 45/47] tcg: Remove TCG_TARGET_SUPPORT_MIRROR Date: Thu, 7 Jan 2021 10:14:46 -1000 Message-Id: <20210107201448.1152301-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Joelle van Dyne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that all native tcg hosts support splitwx, remove the define. Replace the one use with a test for CONFIG_TCG_INTERPRETER. Reviewed-by: Joelle van Dyne Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 1 - tcg/arm/tcg-target.h | 1 - tcg/i386/tcg-target.h | 1 - tcg/mips/tcg-target.h | 1 - tcg/ppc/tcg-target.h | 1 - tcg/riscv/tcg-target.h | 1 - tcg/s390/tcg-target.h | 1 - tcg/sparc/tcg-target.h | 1 - tcg/tci/tcg-target.h | 1 - accel/tcg/translate-all.c | 16 +++++++++------- 10 files changed, 9 insertions(+), 16 deletions(-) -- 2.25.1 diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 079828ea71..5ec30dba25 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -155,6 +155,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_SUPPORT_MIRROR 1 #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index fdf75ba93f..8d1fee6327 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -142,6 +142,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_SUPPORT_MIRROR 1 #endif diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index cb1b138b66..b693d3692d 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -235,6 +235,5 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_SUPPORT_MIRROR 1 #endif diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index ed5c347374..c2c32fb38f 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -201,7 +201,6 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -#define TCG_TARGET_SUPPORT_MIRROR 1 void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index ec51f474a7..d1339afc66 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -185,6 +185,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_SUPPORT_MIRROR 1 #endif diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index c50ecf4dab..727c8df418 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -171,6 +171,5 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS #define TCG_TARGET_HAS_MEMORY_BSWAP 0 -#define TCG_TARGET_SUPPORT_MIRROR 1 #endif diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 4edcb06044..641464eea4 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -159,6 +159,5 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, #define TCG_TARGET_NEED_LDST_LABELS #endif #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_SUPPORT_MIRROR 1 #endif diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 6426e24f17..95ab9af955 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -172,6 +172,5 @@ extern bool use_vis3_instructions; void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS -#define TCG_TARGET_SUPPORT_MIRROR 1 #endif diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index d8c78d1dc7..bb784e018e 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -198,7 +198,6 @@ void tci_disas(uint8_t opc); #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -#define TCG_TARGET_SUPPORT_MIRROR 0 static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, uintptr_t jmp_rw, uintptr_t addr) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 02e1b05c42..e9de6ff9dd 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1132,6 +1132,7 @@ static bool alloc_code_gen_buffer_anon(size_t size, int prot, return true; } +#ifndef CONFIG_TCG_INTERPRETER #ifdef CONFIG_POSIX #include "qemu/memfd.h" @@ -1254,17 +1255,18 @@ static bool alloc_code_gen_buffer_splitwx_vmremap(size_t size, Error **errp) return true; } #endif /* CONFIG_DARWIN */ +#endif /* CONFIG_TCG_INTERPRETER */ static bool alloc_code_gen_buffer_splitwx(size_t size, Error **errp) { - if (TCG_TARGET_SUPPORT_MIRROR) { -#ifdef CONFIG_DARWIN - return alloc_code_gen_buffer_splitwx_vmremap(size, errp); +#ifndef CONFIG_TCG_INTERPRETER +# ifdef CONFIG_DARWIN + return alloc_code_gen_buffer_splitwx_vmremap(size, errp); +# endif +# ifdef CONFIG_POSIX + return alloc_code_gen_buffer_splitwx_memfd(size, errp); +# endif #endif -#ifdef CONFIG_POSIX - return alloc_code_gen_buffer_splitwx_memfd(size, errp); -#endif - } error_setg(errp, "jit split-wx not supported"); return false; } From patchwork Thu Jan 7 20:14:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358288 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp795904jai; Thu, 7 Jan 2021 12:47:59 -0800 (PST) X-Google-Smtp-Source: ABdhPJyWxhOOTRrkPdBM7eV/rpMWF/QReysu0/SlBI6ldhVoUelEO7zSnz0RmQp6D4+/vkTeEl0F X-Received: by 2002:a25:4107:: with SMTP id o7mr840405yba.459.1610052479090; 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.16.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:16:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 46/47] tcg: Constify tcg_code_gen_epilogue Date: Thu, 7 Jan 2021 10:14:47 -1000 Message-Id: <20210107201448.1152301-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Joelle van Dyne , =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that all native tcg hosts support splitwx, make this pointer const. Reviewed-by: Joelle van Dyne Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 2 +- tcg/tcg.c | 2 +- tcg/aarch64/tcg-target.c.inc | 3 +-- tcg/arm/tcg-target.c.inc | 3 +-- tcg/i386/tcg-target.c.inc | 3 +-- tcg/mips/tcg-target.c.inc | 3 +-- tcg/ppc/tcg-target.c.inc | 3 +-- tcg/riscv/tcg-target.c.inc | 3 +-- tcg/s390/tcg-target.c.inc | 3 +-- tcg/sparc/tcg-target.c.inc | 3 +-- 10 files changed, 10 insertions(+), 18 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index e6fce9a049..95fe5604eb 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -677,7 +677,7 @@ struct TCGContext { extern TCGContext tcg_init_ctx; extern __thread TCGContext *tcg_ctx; -extern void *tcg_code_gen_epilogue; +extern const void *tcg_code_gen_epilogue; extern uintptr_t tcg_splitwx_diff; extern TCGv_env cpu_env; diff --git a/tcg/tcg.c b/tcg/tcg.c index f278772512..472bf1755b 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -161,7 +161,7 @@ static int tcg_out_ldst_finalize(TCGContext *s); static TCGContext **tcg_ctxs; static unsigned int n_tcg_ctxs; TCGv_env cpu_env = 0; -void *tcg_code_gen_epilogue; +const void *tcg_code_gen_epilogue; uintptr_t tcg_splitwx_diff; #ifndef CONFIG_TCG_INTERPRETER diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 2e33162c03..0b7eb09a27 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2900,8 +2900,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - /* TODO: Cast goes away when all hosts converted */ - tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); + tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_X0, 0); /* TB epilogue */ diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 3d2717aeb0..d6cb19ca9f 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2301,8 +2301,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - /* TODO: Cast goes away when all hosts converted */ - tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); + tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0); tcg_out_epilogue(s); } diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 34bf0b9a35..91400d575c 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -3804,8 +3804,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - /* TODO: Cast goes away when all hosts converted */ - tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); + tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_EAX, 0); /* TB epilogue */ diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index a2201bd1dd..18fd474593 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -2473,8 +2473,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - /* TODO: Cast goes away when all hosts converted */ - tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); + tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); /* TB epilogue */ diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 33b5915005..5f191c03d9 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2346,8 +2346,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out32(s, BCCTR | BO_ALWAYS); /* Epilogue */ - /* TODO: Cast goes away when all hosts converted */ - tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); + tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET); for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 4d595b01d6..c76dc9f9ca 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1784,8 +1784,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); /* Return path for goto_ptr. Set return value to 0 */ - /* TODO: Cast goes away when all hosts converted */ - tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); + tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO); /* TB epilogue */ diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index 582a8ef941..b3660ffedf 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -2551,8 +2551,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) * Return path for goto_ptr. Set return value to 0, a-la exit_tb, * and fall through to the rest of the epilogue. */ - /* TODO: Cast goes away when all hosts converted */ - tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); + tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, 0); /* TB epilogue */ diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 182124b96c..922ae96481 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -1039,8 +1039,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_nop(s); /* Epilogue for goto_ptr. */ - /* TODO: Cast goes away when all hosts converted */ - tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr); + tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); /* delay slot */ tcg_out_movi_imm13(s, TCG_REG_O0, 0); From patchwork Thu Jan 7 20:14:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 358282 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp792905jai; Thu, 7 Jan 2021 12:42:49 -0800 (PST) X-Google-Smtp-Source: ABdhPJxQsE2lsQ+lLI3fiLKG3HeUwTtu7fWRhu85mRahWZMpJFYRQ00AHnI8Xyw/nJwYLPKqS3Cs X-Received: by 2002:a25:3206:: with SMTP id y6mr934254yby.127.1610052169041; Thu, 07 Jan 2021 12:42:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610052169; cv=none; d=google.com; s=arc-20160816; b=FEqiHwIReD+MUVIF/4RKa4ysOXtxviOfBY2euLOgU9nVyaeQ/E53u0qiSnimqEvVpq 1pu2d4DrUEOB/qUJNRr+fo9cqxnxfJGQByfgSD8DC6RTJjIhGcwbf556r5PCkZcwBVtu P7TGQv5HnDCvAj8M5QZYxHs0MTolnH1MXph8S8iRgyUIxKPTGUbNNLzDc28GRXT0AOMP 5X7mFmepC7XX239hZs/OjM1jhsvDTnJ4vcsbUEMdOYYjq+K11In5yhLDBAwYZ8n72mFV ppO7ijMlY+KK4YCwB1HSpi/vmJF7PPPqs07JGs1kTkjeRGoQszOYbaBk5R9AZ5mRWzsd WI+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/axlOMlK9mP+17efpjcCMV26tl84bU61W0fMNh0sRdI=; b=MGsof3o2xP3rwh2eJzjKaAn0/kYrOTVFuTbDUyni73Ir13RABNQQowKbxThdKvyVuR ox+Q8uSNV5ooSPwtfWQepZvehQkexQv9fKexbA4FL0GsPDm3NMYH/IPC0vs80buA/DP3 jffZGEtQKffXOefUhvHc4sAjkzGo/G2zgymvuoMB/mZkpsfl3R1C60OOzYoLdBV2v0cW 4oOg/la34DD6tUORfz/mLxfSwLht2RjrgVVvyhhqT6il4Y4GTXZwzpbD2Jzox5FGrn0e IL4Zi4ECh1bcscceDo+dvo5Z60xR5RfPeVUTfw+g5z4X9kcvMGPWWoSwOktJFq23KN4o Urow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Mvlb87Ax; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id v6sm6516265pfi.31.2021.01.07.12.16.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 12:16:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 47/47] tcg: Constify TCGLabelQemuLdst.raddr Date: Thu, 7 Jan 2021 10:14:48 -1000 Message-Id: <20210107201448.1152301-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107201448.1152301-1-richard.henderson@linaro.org> References: <20210107201448.1152301-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Joelle van Dyne , =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that all native tcg hosts support splitwx, make this pointer const. Reviewed-by: Joelle van Dyne Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 3 +-- tcg/arm/tcg-target.c.inc | 3 +-- tcg/i386/tcg-target.c.inc | 3 +-- tcg/mips/tcg-target.c.inc | 3 +-- tcg/ppc/tcg-target.c.inc | 3 +-- tcg/riscv/tcg-target.c.inc | 3 +-- tcg/s390/tcg-target.c.inc | 3 +-- tcg/tcg-ldst.c.inc | 2 +- 8 files changed, 8 insertions(+), 15 deletions(-) -- 2.25.1 diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 0b7eb09a27..ab199b143f 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1636,8 +1636,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, label->type = ext; label->datalo_reg = data_reg; label->addrlo_reg = addr_reg; - /* TODO: Cast goes away when all hosts converted */ - label->raddr = (void *)tcg_splitwx_to_rx(raddr); + label->raddr = tcg_splitwx_to_rx(raddr); label->label_ptr[0] = label_ptr; } diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index d6cb19ca9f..0fd1126454 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1340,8 +1340,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, label->datahi_reg = datahi; label->addrlo_reg = addrlo; label->addrhi_reg = addrhi; - /* TODO: Cast goes away when all hosts converted */ - label->raddr = (void *)tcg_splitwx_to_rx(raddr); + label->raddr = tcg_splitwx_to_rx(raddr); label->label_ptr[0] = label_ptr; } diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 91400d575c..46e856f442 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1795,8 +1795,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64, label->datahi_reg = datahi; label->addrlo_reg = addrlo; label->addrhi_reg = addrhi; - /* TODO: Cast goes away when all hosts converted */ - label->raddr = (void *)tcg_splitwx_to_rx(raddr); + label->raddr = tcg_splitwx_to_rx(raddr); label->label_ptr[0] = label_ptr[0]; if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { label->label_ptr[1] = label_ptr[1]; diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 18fd474593..add157f6c3 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1283,8 +1283,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, label->datahi_reg = datahi; label->addrlo_reg = addrlo; label->addrhi_reg = addrhi; - /* TODO: Cast goes away when all hosts converted */ - label->raddr = (void *)tcg_splitwx_to_rx(raddr); + label->raddr = tcg_splitwx_to_rx(raddr); label->label_ptr[0] = label_ptr[0]; if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { label->label_ptr[1] = label_ptr[1]; diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 5f191c03d9..19a4a12f15 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2001,8 +2001,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, label->datahi_reg = datahi_reg; label->addrlo_reg = addrlo_reg; label->addrhi_reg = addrhi_reg; - /* TODO: Cast goes away when all hosts converted */ - label->raddr = (void *)tcg_splitwx_to_rx(raddr); + label->raddr = tcg_splitwx_to_rx(raddr); label->label_ptr[0] = lptr; } diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index c76dc9f9ca..c60b91ba58 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -996,8 +996,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, label->datahi_reg = datahi; label->addrlo_reg = addrlo; label->addrhi_reg = addrhi; - /* TODO: Cast goes away when all hosts converted */ - label->raddr = (void *)tcg_splitwx_to_rx(raddr); + label->raddr = tcg_splitwx_to_rx(raddr); label->label_ptr[0] = label_ptr[0]; } diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index b3660ffedf..d7ef079055 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -1587,8 +1587,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi, label->oi = oi; label->datalo_reg = data; label->addrlo_reg = addr; - /* TODO: Cast goes away when all hosts converted */ - label->raddr = (void *)tcg_splitwx_to_rx(raddr); + label->raddr = tcg_splitwx_to_rx(raddr); label->label_ptr[0] = label_ptr; } diff --git a/tcg/tcg-ldst.c.inc b/tcg/tcg-ldst.c.inc index 05f9b3ccd6..c3ce88e69d 100644 --- a/tcg/tcg-ldst.c.inc +++ b/tcg/tcg-ldst.c.inc @@ -28,7 +28,7 @@ typedef struct TCGLabelQemuLdst { TCGReg addrhi_reg; /* reg index for high word of guest virtual addr */ TCGReg datalo_reg; /* reg index for low word to be loaded or stored */ TCGReg datahi_reg; /* reg index for high word to be loaded or stored */ - tcg_insn_unit *raddr; /* gen code addr of the next IR of qemu_ld/st IR */ + const tcg_insn_unit *raddr; /* addr of the next IR of qemu_ld/st IR */ tcg_insn_unit *label_ptr[2]; /* label pointers to be updated */ QSIMPLEQ_ENTRY(TCGLabelQemuLdst) next; } TCGLabelQemuLdst;