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[60.251.58.169]) by smtp.gmail.com with ESMTPSA id y189sm1739191pfb.155.2021.01.06.00.53.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jan 2021 00:53:56 -0800 (PST) From: Renius Chen To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, ben.chuang@genesyslogic.com.tw, greg.tu@genesyslogic.com.tw, Renius Chen Subject: [PATCH] mmc: sdhci-pci-gli: Add a switch to enable/disable CQHCI support Date: Wed, 6 Jan 2021 16:53:32 +0800 Message-Id: <20210106085332.5494-1-reniuschengl@gmail.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add a vendor-specific bit named GLI_9763E_MB_ERP_ON at the bit7 of register 888h to decide whether to enhance random R/W performance of GL9763E. CQHCI support will be enabled if and only if the bit is set and the GLI_9763E_MB_CMQ_OFF bit is not set. Signed-off-by: Renius Chen --- drivers/mmc/host/sdhci-pci-gli.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c index b85edd62e7f0..c6a107d7c742 100644 --- a/drivers/mmc/host/sdhci-pci-gli.c +++ b/drivers/mmc/host/sdhci-pci-gli.c @@ -84,6 +84,7 @@ #define GLI_9763E_VHS_REV_W 0x2 #define PCIE_GLI_9763E_MB 0x888 #define GLI_9763E_MB_CMDQ_OFF BIT(19) +#define GLI_9763E_MB_ERP_ON BIT(7) #define PCIE_GLI_9763E_SCR 0x8E0 #define GLI_9763E_SCR_AXI_REQ BIT(9) @@ -814,7 +815,8 @@ static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot) pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value); if (!(value & GLI_9763E_MB_CMDQ_OFF)) - host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; + if (value & GLI_9763E_MB_ERP_ON) + host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; gli_pcie_enable_msi(slot); host->mmc_host_ops.hs400_enhanced_strobe =