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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id 3-v6si1085583pls.721.2018.02.21.03.04.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 21 Feb 2018 03:04:33 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Xh/qvMMO; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id D127921FD73F2; Wed, 21 Feb 2018 02:58:33 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::244; helo=mail-wr0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x244.google.com (mail-wr0-x244.google.com [IPv6:2a00:1450:400c:c0c::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8F04820954CC0 for ; Wed, 21 Feb 2018 02:58:32 -0800 (PST) Received: by mail-wr0-x244.google.com with SMTP id k9so3256584wre.9 for ; Wed, 21 Feb 2018 03:04:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=7roRdp+xOVp0L8oaDijEEDQ2mO/FIdIDskJ7zSvDDk8=; b=Xh/qvMMOWV8usZ7EO3uCchr0O36Bt05qb5gPGRnEPBktypfrGAahb6oMd9AI4ZUSkw bLjIQXlASr3Em3todQxv20ceti2dmVAC2+H8tRHBkbUZQ46ldyL4ua11S27RVqXQaBHj 9JjB1nhJz+RL504hm+VDhibMT1f+ZuFF4e1lY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=7roRdp+xOVp0L8oaDijEEDQ2mO/FIdIDskJ7zSvDDk8=; b=bPyL7aNhgfeR/lXq3dgESzRkWhkW4GVGBuG6r41PfQtOS2razv4XWre7DG59ekoXtJ zCdLAtqkyvi74Y4XY8uWWbd4oZ3cGbPSkyPD/dyaQ/CndceQXMvyQYApdnQfVLyFea45 Lja5pQ/ohPxNil1TsyHvKJz2YIyNIGf1zbtyIi7bVNRHNQGtx/LwNI7NgHQFytvGO2/+ cq0E67Fl2pnqihp4L07xJW04+B7xIB4qHioMUJxMcc4qISvksxX0+XiBMj2mgXap07mw 5HCnoq8IuCypYAMpRnbREgjnKaKq26sPk9g6cRK9oCkUqwhQT/T1Amd0FnbY8OtrfHbH Wukw== X-Gm-Message-State: APf1xPB2oMGjnU++Rw0SusomofMeNcb5NnlnsrN94Rf8Dp2BSkwtDwXo jgneo20sQLENaSE8eMdFhlu7TpOyMY4= X-Received: by 10.28.193.134 with SMTP id r128mr1792700wmf.85.1519211069589; Wed, 21 Feb 2018 03:04:29 -0800 (PST) Received: from localhost.localdomain ([105.149.187.179]) by smtp.gmail.com with ESMTPSA id i6sm27695658wrc.46.2018.02.21.03.04.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 21 Feb 2018 03:04:28 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 21 Feb 2018 11:04:21 +0000 Message-Id: <20180221110421.18435-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Subject: [edk2] [PATCH edk2-platforms v2] Silicon/Socionext/SynQuacerI2cDxe: fix TPL handling bug X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Currently, SynQuacerI2cStartRequest() increases the TPL to TPL_HIGH_LEVEL while accessing the I2C controller hardware, but fails to restore the TPL to the original level if the call to SynQuacerI2cMasterStart() fails, and returns right away. Given the TPL_HIGH_LEVEL implies that interrupts are disabled, this results in a complete system hang. So instead, break out of the loop, so that the TPL restore will occur before leaving the function. Note that this will result in the bus control bits to be de-asserted in case of a failure to send the START condition, which is an appropriate cleanup action to take after SynQuacerI2cMasterStart() fails. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- v2: clarify comment and commit log to explain that releasing the bus controls is an appropriate action for this failure mode Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c index 46c512a20151..5e70f9d921c3 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c @@ -324,7 +324,7 @@ SynQuacerI2cStartRequest ( Status = SynQuacerI2cMasterStart (I2c, SlaveAddress, Op); if (EFI_ERROR (Status)) { - return Status; + break; } Status = WaitForInterrupt (I2c); @@ -397,7 +397,7 @@ SynQuacerI2cStartRequest ( } while (BufIdx < Op->LengthInBytes); } - // Stop the transfer + // Force bus state to idle, terminating any ongoing transfer MmioWrite8 (I2c->MmioBase + F_I2C_REG_BCR, 0); if (!AtRuntime) {