From patchwork Tue Jan 12 01:56:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 361138 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3364045jai; Mon, 11 Jan 2021 18:01:59 -0800 (PST) X-Google-Smtp-Source: ABdhPJxgZAvsvq3jLN15iOcKNnpPotNWrwheWvpKhTgUE7Whzh4ZZmid9bzegxKrb0eoVrksNYyK X-Received: by 2002:a17:906:a015:: with SMTP id p21mr1603703ejy.49.1610416919392; Mon, 11 Jan 2021 18:01:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610416919; cv=none; d=google.com; s=arc-20160816; b=u8o3fZBxisximZgPjBQR+onDGHhSmfUpSYCQvnn0ZvEa2e0Vm4vhwN2ia0w2bKWn2p 6gcBItBkZNWDGEX+3qzXqFJwYfD2cLTx4uAbUIWBos9SQYGHsvbzXSfLyfEiV89ityCC gef44ML0nkY8sk4h6kZe6zrak64Ow4M6Syuyktagih1TqlpirWoKtfe1PDcq5nxQ1hGc al9irbx+b1i8n+mM6rFgP2QZyt+wJOOFmERAHO/CZ71ouWoIZLGx3yStzcTgS2w6/Rwr YQsOQWYrQhKfBmZKRksB+ZCqO/JRe20EKvSxb32rjYa7fayIOvXyAfbdzgmuNANLk6u9 VSiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=1d0ivLCSrX+9H524c1Vojlc6XhJRw7mc+WdrngL9/Ag=; b=naSC0Mf2zShRT0twXVh8lVvG40a/ctWTK86FH+mJfLRVxaRB/eqjhibFHmsK5TD+D6 Ykj8hw8RiUYpXjemabmgTXkQuCfz7oHty4oVMA/S79Socv1OwvwlSt3HAEPpRV2azm8D qHVjLRI5V0MYdoK7ZUFuLOGOJZomwI2KOTebbvwu1+OgmwcDsoZgk5yfDxFk6fZ99UEZ BdRK7fswnTAAtR4lC3KxPBiSKejVeBX5l9+gwL3qEqk2w00Rw/TTbX9SAvErzT77K6wy ZO/SdVLfBQDviCoEV3AN7wKSBA4wtasr5hT4qXoEzHMiwepnioBnw4zXcP44/oQPriYS fdsA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id pw3si472761ejb.186.2021.01.11.18.01.59; Mon, 11 Jan 2021 18:01:59 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730604AbhALCBf (ORCPT + 6 others); Mon, 11 Jan 2021 21:01:35 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:11091 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729283AbhALCBd (ORCPT ); Mon, 11 Jan 2021 21:01:33 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4DFDKL0KHBzMHXc; Tue, 12 Jan 2021 09:59:34 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.176.220) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.498.0; Tue, 12 Jan 2021 10:00:43 +0800 From: Zhen Lei To: Russell King , Greg Kroah-Hartman , Will Deacon , "Haojian Zhuang" , Arnd Bergmann , Rob Herring , Wei Xu , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH v3 1/3] ARM: LPAE: Use phys_addr_t instead of unsigned long in outercache hooks Date: Tue, 12 Jan 2021 09:56:00 +0800 Message-ID: <20210112015602.497-2-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20210112015602.497-1-thunder.leizhen@huawei.com> References: <20210112015602.497-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.176.220] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The outercache of some Hisilicon SOCs support physical addresses wider than 32-bits. The unsigned long datatype is not sufficient for mapping physical addresses >= 4GB. The commit ad6b9c9d78b9 ("ARM: 6671/1: LPAE: use phys_addr_t instead of unsigned long in outercache functions") has already modified the outercache functions. But the parameters of the outercache hooks are not changed. This patch use phys_addr_t instead of unsigned long in outercache hooks: inv_range, clean_range, flush_range. To ensure the outercache that does not support LPAE works properly, do cast phys_addr_t to unsigned long by adding a group of temporary variables. For example: -static void l2c220_inv_range(unsigned long start, unsigned long end) +static void l2c220_inv_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; Note that the outercache functions have been doing this cast before this patch. So now, the cast is just moved into the outercache hook functions. No functional change. Signed-off-by: Zhen Lei --- arch/arm/include/asm/outercache.h | 6 ++-- arch/arm/mm/cache-feroceon-l2.c | 15 ++++++++-- arch/arm/mm/cache-l2x0.c | 50 ++++++++++++++++++++++--------- arch/arm/mm/cache-tauros2.c | 15 ++++++++-- arch/arm/mm/cache-uniphier.c | 6 ++-- arch/arm/mm/cache-xsc3l2.c | 12 ++++++-- 6 files changed, 75 insertions(+), 29 deletions(-) -- 2.26.0.106.g9fadedd diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h index 3364637755e86aa..4cee1ea0c15449a 100644 --- a/arch/arm/include/asm/outercache.h +++ b/arch/arm/include/asm/outercache.h @@ -14,9 +14,9 @@ struct l2x0_regs; struct outer_cache_fns { - void (*inv_range)(unsigned long, unsigned long); - void (*clean_range)(unsigned long, unsigned long); - void (*flush_range)(unsigned long, unsigned long); + void (*inv_range)(phys_addr_t, phys_addr_t); + void (*clean_range)(phys_addr_t, phys_addr_t); + void (*flush_range)(phys_addr_t, phys_addr_t); void (*flush_all)(void); void (*disable)(void); #ifdef CONFIG_OUTER_CACHE_SYNC diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c index 5c1b7a7b9af6300..10f909744d5e963 100644 --- a/arch/arm/mm/cache-feroceon-l2.c +++ b/arch/arm/mm/cache-feroceon-l2.c @@ -168,8 +168,11 @@ static unsigned long calc_range_end(unsigned long start, unsigned long end) return range_end; } -static void feroceon_l2_inv_range(unsigned long start, unsigned long end) +static void feroceon_l2_inv_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; + /* * Clean and invalidate partial first cache line. */ @@ -198,8 +201,11 @@ static void feroceon_l2_inv_range(unsigned long start, unsigned long end) dsb(); } -static void feroceon_l2_clean_range(unsigned long start, unsigned long end) +static void feroceon_l2_clean_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; + /* * If L2 is forced to WT, the L2 will always be clean and we * don't need to do anything here. @@ -217,8 +223,11 @@ static void feroceon_l2_clean_range(unsigned long start, unsigned long end) dsb(); } -static void feroceon_l2_flush_range(unsigned long start, unsigned long end) +static void feroceon_l2_flush_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; + start &= ~(CACHE_LINE_SIZE - 1); end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1); while (start != end) { diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 43d91bfd2360086..cdaddd772b09ede 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -184,8 +184,10 @@ static void __l2c210_op_pa_range(void __iomem *reg, unsigned long start, } } -static void l2c210_inv_range(unsigned long start, unsigned long end) +static void l2c210_inv_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; void __iomem *base = l2x0_base; if (start & (CACHE_LINE_SIZE - 1)) { @@ -203,8 +205,10 @@ static void l2c210_inv_range(unsigned long start, unsigned long end) __l2c210_cache_sync(base); } -static void l2c210_clean_range(unsigned long start, unsigned long end) +static void l2c210_clean_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; void __iomem *base = l2x0_base; start &= ~(CACHE_LINE_SIZE - 1); @@ -212,8 +216,10 @@ static void l2c210_clean_range(unsigned long start, unsigned long end) __l2c210_cache_sync(base); } -static void l2c210_flush_range(unsigned long start, unsigned long end) +static void l2c210_flush_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; void __iomem *base = l2x0_base; start &= ~(CACHE_LINE_SIZE - 1); @@ -304,8 +310,10 @@ static unsigned long l2c220_op_pa_range(void __iomem *reg, unsigned long start, return flags; } -static void l2c220_inv_range(unsigned long start, unsigned long end) +static void l2c220_inv_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; void __iomem *base = l2x0_base; unsigned long flags; @@ -331,8 +339,10 @@ static void l2c220_inv_range(unsigned long start, unsigned long end) raw_spin_unlock_irqrestore(&l2x0_lock, flags); } -static void l2c220_clean_range(unsigned long start, unsigned long end) +static void l2c220_clean_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; void __iomem *base = l2x0_base; unsigned long flags; @@ -350,8 +360,10 @@ static void l2c220_clean_range(unsigned long start, unsigned long end) raw_spin_unlock_irqrestore(&l2x0_lock, flags); } -static void l2c220_flush_range(unsigned long start, unsigned long end) +static void l2c220_flush_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; void __iomem *base = l2x0_base; unsigned long flags; @@ -464,8 +476,10 @@ static const struct l2c_init_data l2c220_data = { * Affects: store buffer * store buffer is not automatically drained. */ -static void l2c310_inv_range_erratum(unsigned long start, unsigned long end) +static void l2c310_inv_range_erratum(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; void __iomem *base = l2x0_base; if ((start | end) & (CACHE_LINE_SIZE - 1)) { @@ -496,8 +510,10 @@ static void l2c310_inv_range_erratum(unsigned long start, unsigned long end) __l2c210_cache_sync(base); } -static void l2c310_flush_range_erratum(unsigned long start, unsigned long end) +static void l2c310_flush_range_erratum(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; raw_spinlock_t *lock = &l2x0_lock; unsigned long flags; void __iomem *base = l2x0_base; @@ -1400,12 +1416,12 @@ static void aurora_pa_range(unsigned long start, unsigned long end, start = range_end; } } -static void aurora_inv_range(unsigned long start, unsigned long end) +static void aurora_inv_range(phys_addr_t start, phys_addr_t end) { aurora_pa_range(start, end, AURORA_INVAL_RANGE_REG); } -static void aurora_clean_range(unsigned long start, unsigned long end) +static void aurora_clean_range(phys_addr_t start, phys_addr_t end) { /* * If L2 is forced to WT, the L2 will always be clean and we @@ -1415,7 +1431,7 @@ static void aurora_clean_range(unsigned long start, unsigned long end) aurora_pa_range(start, end, AURORA_CLEAN_RANGE_REG); } -static void aurora_flush_range(unsigned long start, unsigned long end) +static void aurora_flush_range(phys_addr_t start, phys_addr_t end) { if (l2_wt_override) aurora_pa_range(start, end, AURORA_INVAL_RANGE_REG); @@ -1604,8 +1620,10 @@ static inline unsigned long bcm_l2_phys_addr(unsigned long addr) return addr + BCM_VC_EMI_OFFSET; } -static void bcm_inv_range(unsigned long start, unsigned long end) +static void bcm_inv_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; unsigned long new_start, new_end; BUG_ON(start < BCM_SYS_EMI_START_ADDR); @@ -1631,8 +1649,10 @@ static void bcm_inv_range(unsigned long start, unsigned long end) new_end); } -static void bcm_clean_range(unsigned long start, unsigned long end) +static void bcm_clean_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; unsigned long new_start, new_end; BUG_ON(start < BCM_SYS_EMI_START_ADDR); @@ -1658,8 +1678,10 @@ static void bcm_clean_range(unsigned long start, unsigned long end) new_end); } -static void bcm_flush_range(unsigned long start, unsigned long end) +static void bcm_flush_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; unsigned long new_start, new_end; BUG_ON(start < BCM_SYS_EMI_START_ADDR); diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c index 88255bea65e41e6..d768bbb5e05c690 100644 --- a/arch/arm/mm/cache-tauros2.c +++ b/arch/arm/mm/cache-tauros2.c @@ -66,8 +66,11 @@ static inline void tauros2_inv_pa(unsigned long addr) */ #define CACHE_LINE_SIZE 32 -static void tauros2_inv_range(unsigned long start, unsigned long end) +static void tauros2_inv_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; + /* * Clean and invalidate partial first cache line. */ @@ -95,8 +98,11 @@ static void tauros2_inv_range(unsigned long start, unsigned long end) dsb(); } -static void tauros2_clean_range(unsigned long start, unsigned long end) +static void tauros2_clean_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; + start &= ~(CACHE_LINE_SIZE - 1); while (start < end) { tauros2_clean_pa(start); @@ -106,8 +112,11 @@ static void tauros2_clean_range(unsigned long start, unsigned long end) dsb(); } -static void tauros2_flush_range(unsigned long start, unsigned long end) +static void tauros2_flush_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; + start &= ~(CACHE_LINE_SIZE - 1); while (start < end) { tauros2_clean_inv_pa(start); diff --git a/arch/arm/mm/cache-uniphier.c b/arch/arm/mm/cache-uniphier.c index ff2881458504329..e2508358e9f4082 100644 --- a/arch/arm/mm/cache-uniphier.c +++ b/arch/arm/mm/cache-uniphier.c @@ -250,17 +250,17 @@ static void uniphier_cache_maint_all(u32 operation) __uniphier_cache_maint_all(data, operation); } -static void uniphier_cache_inv_range(unsigned long start, unsigned long end) +static void uniphier_cache_inv_range(phys_addr_t start, phys_addr_t end) { uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_INV); } -static void uniphier_cache_clean_range(unsigned long start, unsigned long end) +static void uniphier_cache_clean_range(phys_addr_t start, phys_addr_t end) { uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_CLEAN); } -static void uniphier_cache_flush_range(unsigned long start, unsigned long end) +static void uniphier_cache_flush_range(phys_addr_t start, phys_addr_t end) { uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_FLUSH); } diff --git a/arch/arm/mm/cache-xsc3l2.c b/arch/arm/mm/cache-xsc3l2.c index d20d7af02d10fc0..5814731653d9091 100644 --- a/arch/arm/mm/cache-xsc3l2.c +++ b/arch/arm/mm/cache-xsc3l2.c @@ -83,8 +83,10 @@ static inline unsigned long l2_map_va(unsigned long pa, unsigned long prev_va) #endif } -static void xsc3_l2_inv_range(unsigned long start, unsigned long end) +static void xsc3_l2_inv_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; unsigned long vaddr; if (start == 0 && end == -1ul) { @@ -127,8 +129,10 @@ static void xsc3_l2_inv_range(unsigned long start, unsigned long end) dsb(); } -static void xsc3_l2_clean_range(unsigned long start, unsigned long end) +static void xsc3_l2_clean_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; unsigned long vaddr; vaddr = -1; /* to force the first mapping */ @@ -165,8 +169,10 @@ static inline void xsc3_l2_flush_all(void) dsb(); } -static void xsc3_l2_flush_range(unsigned long start, unsigned long end) +static void xsc3_l2_flush_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; unsigned long vaddr; if (start == 0 && end == -1ul) { From patchwork Tue Jan 12 01:56:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 361136 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3364003jai; Mon, 11 Jan 2021 18:01:56 -0800 (PST) X-Google-Smtp-Source: ABdhPJxYneqc3hEdQBePJk37h8W3Rhgd5GPRa8KX6NHaN57+FxmDg9RnZd0BiojDFTRHvAu/tbSq X-Received: by 2002:a17:907:417f:: with SMTP id oe23mr1444777ejb.259.1610416915828; Mon, 11 Jan 2021 18:01:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; 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[23.128.96.18]) by mx.google.com with ESMTP id pw3si472761ejb.186.2021.01.11.18.01.55; Mon, 11 Jan 2021 18:01:55 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729284AbhALCBc (ORCPT + 6 others); Mon, 11 Jan 2021 21:01:32 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:10707 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725957AbhALCBc (ORCPT ); Mon, 11 Jan 2021 21:01:32 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4DFDKL1jlbzl3xG; Tue, 12 Jan 2021 09:59:34 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.176.220) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.498.0; Tue, 12 Jan 2021 10:00:44 +0800 From: Zhen Lei To: Russell King , Greg Kroah-Hartman , Will Deacon , "Haojian Zhuang" , Arnd Bergmann , Rob Herring , Wei Xu , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH v3 2/3] dt-bindings: arm: hisilicon: Add binding for L3 cache controller Date: Tue, 12 Jan 2021 09:56:01 +0800 Message-ID: <20210112015602.497-3-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20210112015602.497-1-thunder.leizhen@huawei.com> References: <20210112015602.497-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.176.220] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add devicetree binding for Hisilicon L3 cache controller. Signed-off-by: Zhen Lei --- .../bindings/arm/hisilicon/l3cache.yaml | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/l3cache.yaml -- 2.26.0.106.g9fadedd diff --git a/Documentation/devicetree/bindings/arm/hisilicon/l3cache.yaml b/Documentation/devicetree/bindings/arm/hisilicon/l3cache.yaml new file mode 100644 index 000000000000000..f411818bad23741 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/l3cache.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/l3cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon L3 cache controller + +maintainers: + - Wei Xu + +description: | + The Hisilicon L3 outer cache controller supports a maximum of 36-bit physical + addresses. The data cached in the L3 outer cache can be operated based on the + physical address range or the entire cache. + +properties: + compatible: + items: + - const: hisilicon,l3cache + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + l3cache@f302b000 { + compatible = "hisilicon,l3cache"; + reg = <0xf302b000 0x1000>; + }; +... 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[23.128.96.18]) by mx.google.com with ESMTP id pw3si472761ejb.186.2021.01.11.18.01.57; Mon, 11 Jan 2021 18:01:57 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731808AbhALCBi (ORCPT + 6 others); Mon, 11 Jan 2021 21:01:38 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:11092 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730698AbhALCBh (ORCPT ); Mon, 11 Jan 2021 21:01:37 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4DFDKR0Jr4zMJ6R; Tue, 12 Jan 2021 09:59:39 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.176.220) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.498.0; Tue, 12 Jan 2021 10:00:45 +0800 From: Zhen Lei To: Russell King , Greg Kroah-Hartman , Will Deacon , "Haojian Zhuang" , Arnd Bergmann , Rob Herring , Wei Xu , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH v3 3/3] ARM: Add Hisilicon L3 cache controller support Date: Tue, 12 Jan 2021 09:56:02 +0800 Message-ID: <20210112015602.497-4-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20210112015602.497-1-thunder.leizhen@huawei.com> References: <20210112015602.497-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.176.220] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Support for the Hisilicon L3 cache controller as used with Hi1215 and Hi1381. These Hisilicon SoCs support LPAE, so the physical addresses is wider than 32-bits, but the actual bit width does not exceed 36 bits. When the cache operation is performed based on the address range, the upper 30 bits of the physical address are recorded in registers L3_MAINT_START and L3_MAINT_END, and ignore the lower 6 bits cacheline offset. Signed-off-by: Zhen Lei --- arch/arm/mm/Kconfig | 9 +++ arch/arm/mm/Makefile | 1 + arch/arm/mm/cache-hisi-l3.c | 153 ++++++++++++++++++++++++++++++++++++ arch/arm/mm/cache-hisi-l3.h | 30 +++++++ 4 files changed, 193 insertions(+) create mode 100644 arch/arm/mm/cache-hisi-l3.c create mode 100644 arch/arm/mm/cache-hisi-l3.h -- 2.26.0.106.g9fadedd diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 02692fbe2db5c59..73cd28419d731df 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -1070,6 +1070,15 @@ config CACHE_XSC3L2 help This option enables the L2 cache on XScale3. +config CACHE_HISI_L3 + bool "Enable the L3 cache on Hisilicon SoCs" + depends on ARCH_HISI && OF + default y + select OUTER_CACHE + help + This option enables the L3 cache on Hisilicon SoCs. It supports a maximum + of 36-bit physical addresses. + config ARM_L1_CACHE_SHIFT_6 bool default y if CPU_V7 diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index 3510503bc5e688b..745d55ecb2ed4fd 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -112,6 +112,7 @@ obj-$(CONFIG_CACHE_L2X0_PMU) += cache-l2x0-pmu.o obj-$(CONFIG_CACHE_XSC3L2) += cache-xsc3l2.o obj-$(CONFIG_CACHE_TAUROS2) += cache-tauros2.o obj-$(CONFIG_CACHE_UNIPHIER) += cache-uniphier.o +obj-$(CONFIG_CACHE_HISI_L3) += cache-hisi-l3.o KASAN_SANITIZE_kasan_init.o := n obj-$(CONFIG_KASAN) += kasan_init.o diff --git a/arch/arm/mm/cache-hisi-l3.c b/arch/arm/mm/cache-hisi-l3.c new file mode 100644 index 000000000000000..7aa590f378a1ef3 --- /dev/null +++ b/arch/arm/mm/cache-hisi-l3.c @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021 Hisilicon Limited. + */ + +#include +#include +#include +#include + +#include + +#include "cache-hisi-l3.h" + +static DEFINE_SPINLOCK(l3cache_lock); +static void __iomem *l3_ctrl_base; + + +static void l3cache_maint_common(u32 range, u32 op_type) +{ + u32 reg; + + reg = readl(l3_ctrl_base + L3_MAINT_CTRL); + reg &= ~(L3_MAINT_RANGE_MASK | L3_MAINT_TYPE_MASK); + reg |= range | op_type; + reg |= L3_MAINT_STATUS_START; + writel(reg, l3_ctrl_base + L3_MAINT_CTRL); + + /* Wait until the hardware maintenance operation is complete. */ + do { + cpu_relax(); + reg = readl(l3_ctrl_base + L3_MAINT_CTRL); + } while ((reg & L3_MAINT_STATUS_MASK) != L3_MAINT_STATUS_END); +} + +static void l3cache_maint_range(phys_addr_t start, phys_addr_t end, u32 op_type) +{ + start = start >> L3_CACHE_LINE_SHITF; + end = ((end - 1) >> L3_CACHE_LINE_SHITF) + 1; + + writel(start, l3_ctrl_base + L3_MAINT_START); + writel(end, l3_ctrl_base + L3_MAINT_END); + + l3cache_maint_common(L3_MAINT_RANGE_ADDR, op_type); +} + +static inline void l3cache_flush_all_nolock(void) +{ + l3cache_maint_common(L3_MAINT_RANGE_ALL, L3_MAINT_TYPE_FLUSH); +} + +static void l3cache_flush_all(void) +{ + unsigned long flags; + + spin_lock_irqsave(&l3cache_lock, flags); + l3cache_flush_all_nolock(); + spin_unlock_irqrestore(&l3cache_lock, flags); +} + +static void l3cache_inv_range(phys_addr_t start, phys_addr_t end) +{ + unsigned long flags; + + spin_lock_irqsave(&l3cache_lock, flags); + l3cache_maint_range(start, end, L3_MAINT_TYPE_INV); + spin_unlock_irqrestore(&l3cache_lock, flags); +} + +static void l3cache_clean_range(phys_addr_t start, phys_addr_t end) +{ + unsigned long flags; + + spin_lock_irqsave(&l3cache_lock, flags); + l3cache_maint_range(start, end, L3_MAINT_TYPE_CLEAN); + spin_unlock_irqrestore(&l3cache_lock, flags); +} + +static void l3cache_flush_range(phys_addr_t start, phys_addr_t end) +{ + unsigned long flags; + + spin_lock_irqsave(&l3cache_lock, flags); + l3cache_maint_range(start, end, L3_MAINT_TYPE_FLUSH); + spin_unlock_irqrestore(&l3cache_lock, flags); +} + +static void l3cache_disable(void) +{ + unsigned long flags; + + spin_lock_irqsave(&l3cache_lock, flags); + l3cache_flush_all_nolock(); + writel(L3_CTRL_DISABLE, l3_ctrl_base + L3_CTRL); + spin_unlock_irqrestore(&l3cache_lock, flags); +} + +static const struct of_device_id l3cache_ids[] __initconst = { + {.compatible = "hisilicon,l3cache", .data = NULL}, + {} +}; + +static int __init l3cache_init(void) +{ + u32 reg; + struct device_node *node; + + node = of_find_matching_node(NULL, l3cache_ids); + if (!node) + return -ENODEV; + + l3_ctrl_base = of_iomap(node, 0); + if (!l3_ctrl_base) { + pr_err("failed to map l3cache control registers\n"); + return -ENOMEM; + } + + reg = readl(l3_ctrl_base + L3_CTRL); + if (!(reg & L3_CTRL_ENABLE)) { + unsigned long flags; + + spin_lock_irqsave(&l3cache_lock, flags); + + /* + * Ensure that no L3 cache hardware maintenance operations are + * being performed before enabling the L3 cache. Wait for it to + * finish. + */ + do { + cpu_relax(); + reg = readl(l3_ctrl_base + L3_MAINT_CTRL); + } while ((reg & L3_MAINT_STATUS_MASK) != L3_MAINT_STATUS_END); + + reg = readl(l3_ctrl_base + L3_AUCTRL); + reg |= L3_AUCTRL_EVENT_EN | L3_AUCTRL_ECC_EN; + writel(reg, l3_ctrl_base + L3_AUCTRL); + + writel(L3_CTRL_ENABLE, l3_ctrl_base + L3_CTRL); + + spin_unlock_irqrestore(&l3cache_lock, flags); + } + + outer_cache.inv_range = l3cache_inv_range; + outer_cache.clean_range = l3cache_clean_range; + outer_cache.flush_range = l3cache_flush_range; + outer_cache.flush_all = l3cache_flush_all; + outer_cache.disable = l3cache_disable; + + pr_info("Hisilicon l3cache controller enabled\n"); + + return 0; +} +arch_initcall(l3cache_init); diff --git a/arch/arm/mm/cache-hisi-l3.h b/arch/arm/mm/cache-hisi-l3.h new file mode 100644 index 000000000000000..6ec3ee21ae01417 --- /dev/null +++ b/arch/arm/mm/cache-hisi-l3.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __CACHE_HISI_L3_H +#define __CACHE_HISI_L3_H + +#define L3_CACHE_LINE_SHITF 6 + +#define L3_CTRL 0x0 +#define L3_CTRL_ENABLE (1U << 0) +#define L3_CTRL_DISABLE (0U << 0) + +#define L3_AUCTRL 0x4 +#define L3_AUCTRL_EVENT_EN BIT(23) +#define L3_AUCTRL_ECC_EN BIT(8) + +#define L3_MAINT_CTRL 0x20 +#define L3_MAINT_RANGE_MASK GENMASK(3, 3) +#define L3_MAINT_RANGE_ALL (0U << 3) +#define L3_MAINT_RANGE_ADDR (1U << 3) +#define L3_MAINT_TYPE_MASK GENMASK(2, 1) +#define L3_MAINT_TYPE_CLEAN (1U << 1) +#define L3_MAINT_TYPE_INV (2U << 1) +#define L3_MAINT_TYPE_FLUSH (3U << 1) +#define L3_MAINT_STATUS_MASK GENMASK(0, 0) +#define L3_MAINT_STATUS_START (1U << 0) +#define L3_MAINT_STATUS_END (0U << 0) + +#define L3_MAINT_START 0x24 +#define L3_MAINT_END 0x28 + +#endif