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[198.145.21.10]) by mx.google.com with ESMTPS id c18si1241096pgv.519.2018.02.23.00.53.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 00:53:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=RdzF8LQz; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 270BC22436952; Fri, 23 Feb 2018 00:47:48 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::244; helo=mail-pf0-x244.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf0-x244.google.com (mail-pf0-x244.google.com [IPv6:2607:f8b0:400e:c00::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 86A772243694C for ; Fri, 23 Feb 2018 00:47:47 -0800 (PST) Received: by mail-pf0-x244.google.com with SMTP id y186so2580771pfb.2 for ; Fri, 23 Feb 2018 00:53:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EgMXjdbPi0RyUHr9/f3hsdNcmB6zDIDaFA9iWRJI2D8=; b=RdzF8LQzlb7ifyl572tJHMtxk8B6unjHaQU/bTW/eMFkZT8f5a9qIKsCcPj/20vVlR MPaJ+sUwE3ZkGBY77jFF+8fiaZNXdKj8llNhEAvV5ufEBxiKZntqy1dE5jhpT9UmWj99 sbK4tym9JF7Q6SAr4LRwtvB6vuyAoeWHyrnNk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EgMXjdbPi0RyUHr9/f3hsdNcmB6zDIDaFA9iWRJI2D8=; b=Ul9bXFqo9UODhpzzUzmCPDZjPUDKn89bfR1P/C5eZADSXP0lfGl3XmzwNNRwSjljHC KNQtv7q/f9gJkNDQItLYPi5XqOChYL1EHmgEa0dgh71q1iBWD/6kvt8/FrNfz9Z6p4ej i9T3kb1snuGc7OydU6jDMx7GhfTsOWRDqe6XqqL2ck7F6acXNLiaIT7iycWwEXOcCI9Z 5AUG9B7Q3nCBZqUxntdG/QXh4UC63aY7IuReS2pFMpjbbfREUSXkwlCMPovzjHjGF35b ARV0ta+CFQds/1LzudpEHt4w1p9W0adFU3ukzTd/Fx6epCgbK0RbZDxM8NaBXb+8D2im pjIA== X-Gm-Message-State: APf1xPDdlVxzQtthWMHH0CST2nNQq/6EUTe+N9i0UCvxD7b4bylEFj0m ukaISF/+a7CDrfOfvGHG50YCHPpCbfU= X-Received: by 10.98.155.194 with SMTP id e63mr1016288pfk.95.1519376028538; Fri, 23 Feb 2018 00:53:48 -0800 (PST) Received: from localhost.localdomain ([45.56.152.187]) by smtp.gmail.com with ESMTPSA id j25sm3422694pgn.92.2018.02.23.00.53.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 23 Feb 2018 00:53:47 -0800 (PST) From: Heyi Guo To: edk2-devel@lists.01.org Date: Fri, 23 Feb 2018 16:53:26 +0800 Message-Id: <1519376008-110662-2-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519376008-110662-1-git-send-email-heyi.guo@linaro.org> References: <1519376008-110662-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [RFC v3 1/3] MdeModulePkg/PciHostBridgeDxe: Add support for address translation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Eric Dong , Ard Biesheuvel , Heyi Guo , Michael D Kinney , Laszlo Ersek , Star Zeng MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" PCI address translation is necessary for some non-x86 platforms. On such platforms, address value (denoted as "device address" or "address in PCI view") set to PCI BAR registers in configuration space might be different from the address which is used by CPU to access the registers in memory BAR or IO BAR spaces (denoted as "host address" or "address in CPU view"). The difference between the two addresses is called "Address Translation Offset" or simply "translation", and can be represented by "Address Translation Offset" in ACPI QWORD Address Space Descriptor (Offset 0x1E). However UEFI and ACPI differs on the definitions of QWORD Address Space Descriptor, and we will follow UEFI definition on UEFI protocols, such as PCI root bridge IO protocol and PCI IO protocol. In UEFI 2.7, "Address Translation Offset" is "Offset to apply to the Starting address to convert it to a PCI address". This means: 1. Translation = device address - host address. 2. PciRootBridgeIo->Configuration should return CPU view address, as well as PciIo->GetBarAttributes. Summary of addresses used: 1. Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address, for it is easy to check whether the address is below 4G or above 4G. 2. Address returned by EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL::GetProposedResources is device address, or else PCI bus driver cannot set correct address into PCI BAR registers. 3. Address returned by PciRootBridgeIo->Configuration is host address per UEFI 2.7 definition. 4. Addresses used in GCD manipulation are host address. 5. Addresses in ResAllocNode of PCI_ROOT_BRIDGE_INSTANCE are host address, for they are allocated from GCD. 6. Address passed to PciHostBridgeResourceConflict is host address, for it comes from ResAllocNode. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo Cc: Ruiyu Ni Cc: Ard Biesheuvel Cc: Star Zeng Cc: Eric Dong Cc: Laszlo Ersek Cc: Michael D Kinney --- .../Bus/Pci/PciHostBridgeDxe/PciHostBridge.c | 74 +++++++++++--- .../Bus/Pci/PciHostBridgeDxe/PciHostResource.h | 2 + .../Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 112 ++++++++++++++++++--- MdeModulePkg/Include/Library/PciHostBridgeLib.h | 8 ++ 4 files changed, 167 insertions(+), 29 deletions(-) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c index 1494848..e8979eb 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c @@ -32,6 +32,29 @@ EDKII_IOMMU_PROTOCOL *mIoMmuProtocol; EFI_EVENT mIoMmuEvent; VOID *mIoMmuRegistration; +STATIC +UINT64 +GetTranslationByResourceType ( + IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge, + IN PCI_RESOURCE_TYPE ResourceType + ) +{ + switch (ResourceType) { + case TypeIo: + return RootBridge->Io.Translation; + case TypeMem32: + return RootBridge->Mem.Translation; + case TypePMem32: + return RootBridge->PMem.Translation; + case TypeMem64: + return RootBridge->MemAbove4G.Translation; + case TypePMem64: + return RootBridge->PMemAbove4G.Translation; + default: + return 0; + } +} + /** Ensure the compatibility of an IO space descriptor with the IO aperture. @@ -411,8 +434,12 @@ InitializePciHostBridge ( } if (RootBridges[Index].Io.Base <= RootBridges[Index].Io.Limit) { + // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address. + // According to UEFI 2.7, device address = host address + Translation. + // For GCD resource manipulation, we should use host address, so + // Translation is subtracted from device address here. Status = AddIoSpace ( - RootBridges[Index].Io.Base, + RootBridges[Index].Io.Base - RootBridges[Index].Io.Translation, RootBridges[Index].Io.Limit - RootBridges[Index].Io.Base + 1 ); ASSERT_EFI_ERROR (Status); @@ -422,7 +449,7 @@ InitializePciHostBridge ( EfiGcdIoTypeIo, 0, RootBridges[Index].Io.Limit - RootBridges[Index].Io.Base + 1, - &RootBridges[Index].Io.Base, + &RootBridges[Index].Io.Base - RootBridges[Index].Io.Translation, gImageHandle, NULL ); @@ -443,14 +470,18 @@ InitializePciHostBridge ( for (MemApertureIndex = 0; MemApertureIndex < ARRAY_SIZE (MemApertures); MemApertureIndex++) { if (MemApertures[MemApertureIndex]->Base <= MemApertures[MemApertureIndex]->Limit) { + // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address. + // According to UEFI 2.7, device address = host address + Translation. + // For GCD resource manipulation, we should use host address, so + // Translation is subtracted from device address here. Status = AddMemoryMappedIoSpace ( - MemApertures[MemApertureIndex]->Base, + MemApertures[MemApertureIndex]->Base - MemApertures[MemApertureIndex]->Translation, MemApertures[MemApertureIndex]->Limit - MemApertures[MemApertureIndex]->Base + 1, EFI_MEMORY_UC ); ASSERT_EFI_ERROR (Status); Status = gDS->SetMemorySpaceAttributes ( - MemApertures[MemApertureIndex]->Base, + MemApertures[MemApertureIndex]->Base - MemApertures[MemApertureIndex]->Translation, MemApertures[MemApertureIndex]->Limit - MemApertures[MemApertureIndex]->Base + 1, EFI_MEMORY_UC ); @@ -463,7 +494,7 @@ InitializePciHostBridge ( EfiGcdMemoryTypeMemoryMappedIo, 0, MemApertures[MemApertureIndex]->Limit - MemApertures[MemApertureIndex]->Base + 1, - &MemApertures[MemApertureIndex]->Base, + &MemApertures[MemApertureIndex]->Base - MemApertures[MemApertureIndex]->Translation, gImageHandle, NULL ); @@ -824,12 +855,17 @@ NotifyPhase ( switch (Index) { case TypeIo: + // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address. + // According to UEFI 2.7, device address = host address + Translation. + // For AllocateResource is manipulating GCD resource, we should use + // host address here, so Translation is subtracted from Base and + // Limit. BaseAddress = AllocateResource ( FALSE, RootBridge->ResAllocNode[Index].Length, MIN (15, BitsOfAlignment), - ALIGN_VALUE (RootBridge->Io.Base, Alignment + 1), - RootBridge->Io.Limit + ALIGN_VALUE (RootBridge->Io.Base, Alignment + 1) - RootBridge->Io.Translation, + RootBridge->Io.Limit - RootBridge->Io.Translation ); break; @@ -838,8 +874,8 @@ NotifyPhase ( TRUE, RootBridge->ResAllocNode[Index].Length, MIN (63, BitsOfAlignment), - ALIGN_VALUE (RootBridge->MemAbove4G.Base, Alignment + 1), - RootBridge->MemAbove4G.Limit + ALIGN_VALUE (RootBridge->MemAbove4G.Base, Alignment + 1) - RootBridge->MemAbove4G.Translation, + RootBridge->MemAbove4G.Limit - RootBridge->MemAbove4G.Translation ); if (BaseAddress != MAX_UINT64) { break; @@ -853,8 +889,8 @@ NotifyPhase ( TRUE, RootBridge->ResAllocNode[Index].Length, MIN (31, BitsOfAlignment), - ALIGN_VALUE (RootBridge->Mem.Base, Alignment + 1), - RootBridge->Mem.Limit + ALIGN_VALUE (RootBridge->Mem.Base, Alignment + 1) - RootBridge->Mem.Translation, + RootBridge->Mem.Limit - RootBridge->Mem.Translation ); break; @@ -863,8 +899,8 @@ NotifyPhase ( TRUE, RootBridge->ResAllocNode[Index].Length, MIN (63, BitsOfAlignment), - ALIGN_VALUE (RootBridge->PMemAbove4G.Base, Alignment + 1), - RootBridge->PMemAbove4G.Limit + ALIGN_VALUE (RootBridge->PMemAbove4G.Base, Alignment + 1) - RootBridge->PMemAbove4G.Translation, + RootBridge->PMemAbove4G.Limit - RootBridge->PMemAbove4G.Translation ); if (BaseAddress != MAX_UINT64) { break; @@ -877,8 +913,8 @@ NotifyPhase ( TRUE, RootBridge->ResAllocNode[Index].Length, MIN (31, BitsOfAlignment), - ALIGN_VALUE (RootBridge->PMem.Base, Alignment + 1), - RootBridge->PMem.Limit + ALIGN_VALUE (RootBridge->PMem.Base, Alignment + 1) - RootBridge->PMem.Translation, + RootBridge->PMem.Limit - RootBridge->PMem.Translation ); break; @@ -1152,6 +1188,7 @@ StartBusEnumeration ( Descriptor->AddrSpaceGranularity = 0; Descriptor->AddrRangeMin = RootBridge->Bus.Base; Descriptor->AddrRangeMax = 0; + // Ignore translation offset for bus Descriptor->AddrTranslationOffset = 0; Descriptor->AddrLen = RootBridge->Bus.Limit - RootBridge->Bus.Base + 1; @@ -1421,7 +1458,12 @@ GetProposedResources ( Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;; Descriptor->GenFlag = 0; - Descriptor->AddrRangeMin = RootBridge->ResAllocNode[Index].Base; + // AddrRangeMin in Resource Descriptor here should be device address + // instead of host address, or else PCI bus driver cannot set correct + // address into PCI BAR registers. + // Base in ResAllocNode is a host address, so Translation is added. + Descriptor->AddrRangeMin = RootBridge->ResAllocNode[Index].Base + + GetTranslationByResourceType (RootBridge, Index); Descriptor->AddrRangeMax = 0; Descriptor->AddrTranslationOffset = (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : PCI_RESOURCE_LESS; Descriptor->AddrLen = RootBridge->ResAllocNode[Index].Length; diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h index 8612c0c..662c2dd 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h @@ -38,6 +38,8 @@ typedef enum { typedef struct { PCI_RESOURCE_TYPE Type; + // Base is a host address instead of a device address when address translation + // exists and host address != device address UINT64 Base; UINT64 Length; UINT64 Alignment; diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c index dc06c16..04ed411 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c @@ -86,12 +86,23 @@ CreateRootBridge ( (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0 ? L"CombineMemPMem " : L"", (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) != 0 ? L"Mem64Decode" : L"" )); + // We don't see any scenario for bus translation, so translation for bus is just ignored. DEBUG ((EFI_D_INFO, " Bus: %lx - %lx\n", Bridge->Bus.Base, Bridge->Bus.Limit)); - DEBUG ((EFI_D_INFO, " Io: %lx - %lx\n", Bridge->Io.Base, Bridge->Io.Limit)); - DEBUG ((EFI_D_INFO, " Mem: %lx - %lx\n", Bridge->Mem.Base, Bridge->Mem.Limit)); - DEBUG ((EFI_D_INFO, " MemAbove4G: %lx - %lx\n", Bridge->MemAbove4G.Base, Bridge->MemAbove4G.Limit)); - DEBUG ((EFI_D_INFO, " PMem: %lx - %lx\n", Bridge->PMem.Base, Bridge->PMem.Limit)); - DEBUG ((EFI_D_INFO, " PMemAbove4G: %lx - %lx\n", Bridge->PMemAbove4G.Base, Bridge->PMemAbove4G.Limit)); + DEBUG ((DEBUG_INFO, " Io: %lx - %lx translation=%lx\n", + Bridge->Io.Base, Bridge->Io.Limit, Bridge->Io.Translation + )); + DEBUG ((DEBUG_INFO, " Mem: %lx - %lx translation=%lx\n", + Bridge->Mem.Base, Bridge->Mem.Limit, Bridge->Mem.Translation + )); + DEBUG ((DEBUG_INFO, " MemAbove4G: %lx - %lx translation=%lx\n", + Bridge->MemAbove4G.Base, Bridge->MemAbove4G.Limit, Bridge->MemAbove4G.Translation + )); + DEBUG ((DEBUG_INFO, " PMem: %lx - %lx translation=%lx\n", + Bridge->PMem.Base, Bridge->PMem.Limit, Bridge->PMem.Translation + )); + DEBUG ((DEBUG_INFO, " PMemAbove4G: %lx - %lx translation=%lx\n", + Bridge->PMemAbove4G.Base, Bridge->PMemAbove4G.Limit, Bridge->PMemAbove4G.Translation + )); // // Make sure Mem and MemAbove4G apertures are valid @@ -206,7 +217,10 @@ CreateRootBridge ( } RootBridge->ResAllocNode[Index].Type = Index; if (Bridge->ResourceAssigned && (Aperture->Limit >= Aperture->Base)) { - RootBridge->ResAllocNode[Index].Base = Aperture->Base; + // Base in ResAllocNode is a host address, while Base in Aperture is a + // device address, so translation needs to be subtracted. + RootBridge->ResAllocNode[Index].Base = Aperture->Base - + Aperture->Translation; RootBridge->ResAllocNode[Index].Length = Aperture->Limit - Aperture->Base + 1; RootBridge->ResAllocNode[Index].Status = ResAllocated; } else { @@ -403,6 +417,28 @@ RootBridgeIoCheckParameter ( return EFI_SUCCESS; } +EFI_STATUS +RootBridgeIoGetMemTranslationByAddress ( + IN PCI_ROOT_BRIDGE_INSTANCE *RootBridge, + IN UINT64 Address, + IN OUT UINT64 *Translation + ) +{ + if (Address >= RootBridge->Mem.Base && Address <= RootBridge->Mem.Limit) { + *Translation = RootBridge->Mem.Translation; + } else if (Address >= RootBridge->PMem.Base && Address <= RootBridge->PMem.Limit) { + *Translation = RootBridge->PMem.Translation; + } else if (Address >= RootBridge->MemAbove4G.Base && Address <= RootBridge->MemAbove4G.Limit) { + *Translation = RootBridge->MemAbove4G.Translation; + } else if (Address >= RootBridge->PMemAbove4G.Base && Address <= RootBridge->PMemAbove4G.Limit) { + *Translation = RootBridge->PMemAbove4G.Translation; + } else { + return EFI_INVALID_PARAMETER; + } + + return EFI_SUCCESS; +} + /** Polls an address in memory mapped I/O space until an exit condition is met, or a timeout occurs. @@ -658,13 +694,24 @@ RootBridgeIoMemRead ( ) { EFI_STATUS Status; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + UINT64 Translation; Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address, Count, Buffer); if (EFI_ERROR (Status)) { return Status; } - return mCpuIo->Mem.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address, Count, Buffer); + + RootBridge = ROOT_BRIDGE_FROM_THIS (This); + Status = RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, &Translation); + if (EFI_ERROR (Status)) { + return Status; + } + + // Address passed to CpuIo->Mem.Read should be a host address instead of + // device address, so Translation should be subtracted. + return mCpuIo->Mem.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address - Translation, Count, Buffer); } /** @@ -705,13 +752,24 @@ RootBridgeIoMemWrite ( ) { EFI_STATUS Status; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + UINT64 Translation; Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address, Count, Buffer); if (EFI_ERROR (Status)) { return Status; } - return mCpuIo->Mem.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address, Count, Buffer); + + RootBridge = ROOT_BRIDGE_FROM_THIS (This); + Status = RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, &Translation); + if (EFI_ERROR (Status)) { + return Status; + } + + // Address passed to CpuIo->Mem.Write should be a host address instead of + // device address, so Translation should be subtracted. + return mCpuIo->Mem.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address - Translation, Count, Buffer); } /** @@ -746,6 +804,8 @@ RootBridgeIoIoRead ( ) { EFI_STATUS Status; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + Status = RootBridgeIoCheckParameter ( This, IoOperation, Width, Address, Count, Buffer @@ -753,7 +813,12 @@ RootBridgeIoIoRead ( if (EFI_ERROR (Status)) { return Status; } - return mCpuIo->Io.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address, Count, Buffer); + + RootBridge = ROOT_BRIDGE_FROM_THIS (This); + + // Address passed to CpuIo->Io.Read should be a host address instead of + // device address, so Translation should be subtracted. + return mCpuIo->Io.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address - RootBridge->Io.Translation, Count, Buffer); } /** @@ -788,6 +853,8 @@ RootBridgeIoIoWrite ( ) { EFI_STATUS Status; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + Status = RootBridgeIoCheckParameter ( This, IoOperation, Width, Address, Count, Buffer @@ -795,7 +862,12 @@ RootBridgeIoIoWrite ( if (EFI_ERROR (Status)) { return Status; } - return mCpuIo->Io.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address, Count, Buffer); + + RootBridge = ROOT_BRIDGE_FROM_THIS (This); + + // Address passed to CpuIo->Io.Write should be a host address instead of + // device address, so Translation should be subtracted. + return mCpuIo->Io.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address - RootBridge->Io.Translation, Count, Buffer); } /** @@ -1615,25 +1687,39 @@ RootBridgeIoConfiguration ( Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3; + // According to UEFI 2.7, RootBridgeIo->Configuration should return address + // range in CPU view (host address), and ResAllocNode->Base is already a CPU + // view address (host address). Descriptor->AddrRangeMin = ResAllocNode->Base; Descriptor->AddrRangeMax = ResAllocNode->Base + ResAllocNode->Length - 1; Descriptor->AddrLen = ResAllocNode->Length; switch (ResAllocNode->Type) { case TypeIo: - Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO; + Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO; + Descriptor->AddrTranslationOffset = RootBridge->Io.Translation; break; case TypePMem32: - Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE; + Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE; + Descriptor->AddrTranslationOffset = RootBridge->PMem.Translation; + Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM; + Descriptor->AddrSpaceGranularity = 32; + break; + case TypeMem32: + Descriptor->AddrTranslationOffset = RootBridge->Mem.Translation; Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM; Descriptor->AddrSpaceGranularity = 32; break; case TypePMem64: - Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE; + Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE; + Descriptor->AddrTranslationOffset = RootBridge->PMemAbove4G.Translation; + Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM; + Descriptor->AddrSpaceGranularity = 64; case TypeMem64: + Descriptor->AddrTranslationOffset = RootBridge->MemAbove4G.Translation; Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM; Descriptor->AddrSpaceGranularity = 64; break; diff --git a/MdeModulePkg/Include/Library/PciHostBridgeLib.h b/MdeModulePkg/Include/Library/PciHostBridgeLib.h index d42e9ec..21ee8cd 100644 --- a/MdeModulePkg/Include/Library/PciHostBridgeLib.h +++ b/MdeModulePkg/Include/Library/PciHostBridgeLib.h @@ -20,8 +20,16 @@ // (Base > Limit) indicates an aperture is not available. // typedef struct { + // Base and Limit are the device address instead of host address when + // Translation is not zero UINT64 Base; UINT64 Limit; + // According to UEFI 2.7, Device Address = Host Address + Translation, + // so Translation = Device Address - Host Address. + // On platforms where Translation is not zero, Translation is probably + // negative for we may translate an above-4G host address into a below-4G + // device address for legacy PCIe device compatibility. + UINT64 Translation; } PCI_ROOT_BRIDGE_APERTURE; typedef struct { From patchwork Fri Feb 23 08:53:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 129335 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp361999lja; Fri, 23 Feb 2018 00:53:54 -0800 (PST) X-Google-Smtp-Source: AH8x225neDeFoF5o1eXv9u5nGBxiOfz/6cjFPnXfgm66X6gS4haNQYlLTvaFlW6ZRVGCv5xWZEME X-Received: by 10.98.112.70 with SMTP id l67mr1038048pfc.196.1519376034614; Fri, 23 Feb 2018 00:53:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519376034; cv=none; d=google.com; s=arc-20160816; b=vf/Vqviadyqcipt8RBKSCMNPFcmH3wSqa5ndVFsXt89hB8c+/4zlEaLckA8kGKNl/I 797euTGGVEUlu94LGytN3SpAmZX5OS3elaE/MtTH28DbFoQqknc0MPj0gtkg8nQYkTIT i0+cjw78LspILfi3Pg7vpPXEgRxviJA82n4R9vKPtQr29Pqfk4Y4H3Bho5NLg/2tuQlG 3SBqZpaJcQoe+S+S/EGxVzJTiemzBUOZfuZYTJRTEH96IsqCLhzaz45KSgAbscOR398s TnL8jLu3zLeMBfcPfle+e0i/fFfz9iUJj49tT4z7dT/BDnfGtTWVAICLlTZADA5TbtNr w2tg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=5tJsCC5q11YwLeQSHbHEKDTDXMI0eyxTYsHx6pTgu8A=; b=g2C7noXLhLIKaCCqbyMf5B9Ly/5u9oMo/KlXySA6R2tnzeGOkrfT924upznm1dKaX8 pqGRrikso6KFPdpFPXVQSTl/6aUyAhpGeEqVY6T20fUe9ehQtNVGmJtanhyLLzHb/SpE 8L/rm7YCffPWgQzjlmF2WWhY9nPQXgj+LnJHQoOt//e+aWRxojBNlk3LVL8vQmx++20V FuNZwy4b2WNVhx/ExRGAWRbIGpWfrMZCFwVmqK+gsXrBu2ZgGFD4b7gz2Gdf6Y7S7/ym b4l5DxGfmYLh5ZKmhwZrAVK2+JmvztxkSTArlKmMx99yqVcl3YKmL8QYkqSfSrnXQcDU zJCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=LGL4HG4/; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id d26si1274661pge.98.2018.02.23.00.53.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 00:53:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=LGL4HG4/; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 8801422436955; Fri, 23 Feb 2018 00:47:52 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::242; helo=mail-pl0-x242.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x242.google.com (mail-pl0-x242.google.com [IPv6:2607:f8b0:400e:c01::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 173BC2243694C for ; Fri, 23 Feb 2018 00:47:51 -0800 (PST) Received: by mail-pl0-x242.google.com with SMTP id i6so4554180plt.7 for ; Fri, 23 Feb 2018 00:53:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Gtgz/orTjry0vbMrGO3p7NEXe4kq4V+xay6Y0/ltgaw=; b=LGL4HG4/VGXPQf7swJxOXVm7pRsJLaRgmFCvBh6SIsZGjygLJAIcnWWu1YCszzgAuX k7+FMw0hK+b5F1oS4zNyM2yl7PAAtXQ5HS/n0b1es84m0nH8aqZOu2umRk5ulY0Xe+pZ eJ76TrX0atzDbKA5fTkQLS8JSKnxy70jvLPJU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Gtgz/orTjry0vbMrGO3p7NEXe4kq4V+xay6Y0/ltgaw=; b=KFWwifTDxZjT/yyFUthAH0wKzCN+cYmhhMzIzbJaOUWZRp4l7YVTwGOFH3K+0I34Um MyOhZvVna5TkwFosVFB8UP+Ej0BWRHjTS3xdtXaAVW7ABqbhR7vztUXk5dH5dq2AdvNs dR/Gnx98oAvmpWygc4JHyiVd7f8co4SmqTWhoucpjIeWZ4G3qCYPAatyxMVjfXPu6ChJ G8NMAaei2vuTKUceWrgjUK1z80JCgt48VwIF7O6A5WSH7nCFZHKwrOFx0DT8R5Zl8CNP Ea/ywJ1416c/i54hEZok7ZiQtcnxX+1Cv84f8uZRyayVn5P0GMbtm+BsQiTohC1a/wcV dJLg== X-Gm-Message-State: APf1xPAvbm2MlNYIohA5RBFHfoIEuoVBH4RNBP/33DijdMLZxln3Ko7d cVDVvgtLovOX93WKb7TK2QQyi3TbhSQ= X-Received: by 2002:a17:902:461:: with SMTP id 88-v6mr1047242ple.88.1519376032217; Fri, 23 Feb 2018 00:53:52 -0800 (PST) Received: from localhost.localdomain ([45.56.152.187]) by smtp.gmail.com with ESMTPSA id j25sm3422694pgn.92.2018.02.23.00.53.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 23 Feb 2018 00:53:51 -0800 (PST) From: Heyi Guo To: edk2-devel@lists.01.org Date: Fri, 23 Feb 2018 16:53:27 +0800 Message-Id: <1519376008-110662-3-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519376008-110662-1-git-send-email-heyi.guo@linaro.org> References: <1519376008-110662-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [RFC v3 2/3] MdeModulePkg/PciBus: convert host address to device address X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Eric Dong , Ard Biesheuvel , Heyi Guo , Michael D Kinney , Laszlo Ersek , Star Zeng MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" According to UEFI spec 2.7, PciRootBridgeIo->Configuration() should return host address (CPU view ddress) rather than device address (PCI view address), so in function GetMmioAddressTranslationOffset we need to convert the range to device address before comparing. And device address = host address + translation offset. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo Cc: Ruiyu Ni Cc: Ard Biesheuvel Cc: Star Zeng Cc: Eric Dong Cc: Laszlo Ersek Cc: Michael D Kinney --- MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c index 190f4b0..fef3ece 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c @@ -1812,10 +1812,14 @@ GetMmioAddressTranslationOffset ( return (UINT64) -1; } + // According to UEFI 2.7, EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL::Configuration() + // returns host address instead of device address, while AddrTranslationOffset + // is not zero, and device address = host address + AddrTranslationOffset, so + // we convert host address to device address for range compare. while (Configuration->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) { if ((Configuration->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) && - (Configuration->AddrRangeMin <= AddrRangeMin) && - (Configuration->AddrRangeMin + Configuration->AddrLen >= AddrRangeMin + AddrLen) + (Configuration->AddrRangeMin + Configuration->AddrTranslationOffset <= AddrRangeMin) && + (Configuration->AddrRangeMin + Configuration->AddrLen + Configuration->AddrTranslationOffset >= AddrRangeMin + AddrLen) ) { return Configuration->AddrTranslationOffset; } From patchwork Fri Feb 23 08:53:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 129336 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp362085lja; Fri, 23 Feb 2018 00:54:00 -0800 (PST) X-Google-Smtp-Source: AH8x227JMbzcv0RXLSLG67I7QWsrDZMliRRTH5e4wSNdjgltffz08lZhpJGLqJgsmSeWeb/5t/GV X-Received: by 10.101.93.135 with SMTP id f7mr858845pgt.82.1519376040050; Fri, 23 Feb 2018 00:54:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519376040; cv=none; d=google.com; s=arc-20160816; b=QJJDm+8rlfvH/GkCvhdhRJSH2t2RF2PEk0OzLkS02XDDt/DilV+uRvwVXC8DZPxGEa Q+V8okBfxUyyBBNl3gt3ysQo1KWkld5TxNgu0lMaj9nRBmJd9muQtBSJJmjNrZpUoSrC u8CEUWviqXyhGRPpd6C5br4mu4Ag5fasc5f1zldZNitS6f6xgEYUO74sleZLgVEV0iZf cxrXdoxQqc6di30dXM0m/ySGQLuf6oTy3t5WTqlIdkqtj/iwWPqsKPlCFZuc4Knw5gf1 u4ubfRBsu3/Ss9+zrSP2KXkoZpwGNsZTkJ9ID/HwIbAi8UG76gmd3BSEGaYb37oL1GlI 4UwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=8t0/JYJ6h8YuK0HpAvUjBMlhor3vuYd/lmEhQ64ciI0=; b=QF0SuOE5rAuDLSV/rp5dsfWI0Lwe2fZu0pqhqjZsEaCRRkTAOaBewykhSNV9DMmyLw I84MKXnp34h2j8sUmQYVOtpIA2946v9GXGGpnBQQpvTKQiQ3tYA3HZmBOZ1lMU/IGZAY R3dEPKEW/7JO1CYWAR9EPApruFuwFPXNnPS3529KKSZFolKKxRLz8PvqkpOMYxB9toSF 2GGV3pvO7HxecdDatkIJEb3CJdD41vz9+sk+umgrmnXA935Lz70CAJ825DCCeZfZ5nFh JuiDE6E5MZ9bI2cPp+b9Ii722JemGK/GPkHuv7U+QYaSV8xB4mwNNzZxiqKPGtdFuS0O fTKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=EPPAbSQ7; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id u7si1490959pfb.216.2018.02.23.00.53.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 00:54:00 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=EPPAbSQ7; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id F034922436958; Fri, 23 Feb 2018 00:47:57 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::244; helo=mail-pl0-x244.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x244.google.com (mail-pl0-x244.google.com [IPv6:2607:f8b0:400e:c01::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 410102243694C for ; Fri, 23 Feb 2018 00:47:56 -0800 (PST) Received: by mail-pl0-x244.google.com with SMTP id w21so4548926plp.11 for ; Fri, 23 Feb 2018 00:53:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yZtA1A2jW8WTfz6GGtR8b/Eimt6mCsZxTmwmmlhp46U=; b=EPPAbSQ74H4+lykyC76reDZaOxU/aLzExXHB5EilITIebYgz++7M3VdQav7ZWELHnU kpaGdK6ufx0ZKR6QjS94EmjezTndhSIeEGYn6WDr4wbj/87ItI4R90s8Sja8j0AQ2G6Q blE3Lq4E+puzlvxOk3TzT1zW+d1GV49WPmRMc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yZtA1A2jW8WTfz6GGtR8b/Eimt6mCsZxTmwmmlhp46U=; b=Yr7HFNQ9XqKI9ihWl6D/nlxXYF4XW7oFluhWHWL0YU+hRIPc/ugerZbtadoybJe5Fz nkshklcJ88t+3+RYCOt9ifrkHFVqgdhR/Z8CIMEYVjnc6fq2pr5KH+VLmvxE4msJy59O 9CTO/TcuZtYa9QEh0gEqcefYsZIVrw1u6Zg0Jq/JR08+vbOxp+91G7X/mguV4oAVXby/ g3RJP3s4/cMfVzwaUMFkHbLTQcf/82Wc5LHF3XzigHlRvIT04jehN1C3DJHVsrpYPE29 W0HjXlwsyMLN2qk+wZZ6+TfYnGk1ak2G04qZg5ykJWmc+6RRYVTEOPJT792WZOzWikie Yyww== X-Gm-Message-State: APf1xPABGKxn0CDcrMH+QJBTryRdUISIvnzPNgnv4t69ZepOFuF5PicD e0B48ek//jrUMS7jOgP5JhI9Y7sKTCo= X-Received: by 2002:a17:902:6e8c:: with SMTP id v12-v6mr1031972plk.424.1519376037336; Fri, 23 Feb 2018 00:53:57 -0800 (PST) Received: from localhost.localdomain ([45.56.152.187]) by smtp.gmail.com with ESMTPSA id j25sm3422694pgn.92.2018.02.23.00.53.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 23 Feb 2018 00:53:56 -0800 (PST) From: Heyi Guo To: edk2-devel@lists.01.org Date: Fri, 23 Feb 2018 16:53:28 +0800 Message-Id: <1519376008-110662-4-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519376008-110662-1-git-send-email-heyi.guo@linaro.org> References: <1519376008-110662-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [RFC v3 3/3] MdeModulePkg/PciBus: return CPU address for GetBarAttributes X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Eric Dong , Ard Biesheuvel , Heyi Guo , Michael D Kinney , Laszlo Ersek , Star Zeng MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" According to UEFI spec 2.7, PciIo->GetBarAttributes should return host address (CPU view ddress) rather than device address (PCI view address), and device address = host address + address translation offset, so we subtract translation from device address before returning. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo Cc: Ruiyu Ni Cc: Ard Biesheuvel Cc: Star Zeng Cc: Eric Dong Cc: Laszlo Ersek Cc: Michael D Kinney --- MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c index fef3ece..62179eb 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c @@ -1972,6 +1972,10 @@ PciIoGetBarAttributes ( return EFI_UNSUPPORTED; } } + + // According to UEFI spec 2.7, we need return host address for + // PciIo->GetBarAttributes, and host address = device address - translation. + Descriptor->AddrRangeMin -= Descriptor->AddrTranslationOffset; } return EFI_SUCCESS;