From patchwork Fri Feb 23 13:28:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 129365 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp606798lja; Fri, 23 Feb 2018 05:29:11 -0800 (PST) X-Google-Smtp-Source: AH8x226UZapL75cTidK2Q1HJZUyXJgUjieFtkjThvrfBwkL9Zo7fQVNvKxHM9cbwKp1tWW2/Iosm X-Received: by 10.99.119.72 with SMTP id s69mr1464562pgc.224.1519392551555; Fri, 23 Feb 2018 05:29:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519392551; cv=none; d=google.com; s=arc-20160816; b=wUlY1ATvmkomxGqWMWv9Re/MT9HHCfb3dmJqhda2GV3VWDIGKyXgYIZ519tiLv2zKR pq8i1Xan4kXAwtmBzv+knAYdnwAFnhlPpULATLwj89E9c5qFL8EcyzFHkEI7FpbrONkW 9MFb+ZWQZcZTIV3wnSUFwxKdfPTG5kECgu7o26AcylYo+G1ekfkzvMO1MX0qyndx8uc/ W18FkxCwwAuKaM/5aN/KHhZZMw8cyqBXbvFhFWldooec2dIMnNKtZk6tDdIr8PzbOB8u wxbG+ZwYhRSDCN1t0kdDWvZoXk4MuB5cw46xQh/DqnRn2eYlBoHiMXYjYdgTlZxjRmwd wxIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:message-id:date:to:from:dkim-signature :delivered-to:arc-authentication-results; bh=Nn2kNNMtMuUlwSIBnNYwveyfsK6rBKaCvzgzK1KXkZk=; b=XDSuvfuCQDCCb0F89y2GlVIclWZrhp+5wYyj5uQBSqOTvAwRr3EaInbE3s/SR03uH/ 6dSRihDVBnkVTLdXyyjdvzXBHvEAWcmjUyGruD+LP2HbpOZSMRrqEqw79VVFhySBMDd2 p0NVMq8shQQ1xg3Ka55HGwKFeI3G+8l1cutCfq3SxjqHBeshu24zo4QTY9kLQtAdJltU z5YNaIE+yfdLlXa+YN89+VhYth7d+olp6I2iYK3xavuggNI5XdN5T+Iga6WW4gBrx4fo DrmeKS1Xk3oc+QaaGf/PXF9qYS6WLJaUQjRfWiU89AqsCzFDa2hivWdc0rCUpzkYqOMU xBfA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=cU2oghPH; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id g1-v6si1803506pld.236.2018.02.23.05.29.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 05:29:11 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=cU2oghPH; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 031D02034D8C0; Fri, 23 Feb 2018 05:23:09 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::235; helo=mail-wm0-x235.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x235.google.com (mail-wm0-x235.google.com [IPv6:2a00:1450:400c:c09::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B78D222436956 for ; Fri, 23 Feb 2018 05:23:06 -0800 (PST) Received: by mail-wm0-x235.google.com with SMTP id q83so4677001wme.5 for ; Fri, 23 Feb 2018 05:29:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=+PGwVVbYp4FU6hWd06Ko5bfyz9SSFXxEwUZR/7nV0p0=; b=cU2oghPHCJCNd8OhtqEsAOw0yT5ysK1hZYfcYtXTdtvX5jTpc3GDSuwzV8AQ7ixuUk dTysTwq/0lwUOVNf0aJI1tTs0zNry2KllwM5vAWb8PP11Cbupb2rd125L10yzl1G2GJ3 U8AnpqfaGfOcA1fwQu1F15hAH2IvWQS7GZOo0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=+PGwVVbYp4FU6hWd06Ko5bfyz9SSFXxEwUZR/7nV0p0=; b=Qzsk1XkcrnjplMlLNttyXpwe+aNwvitvawPBGAs0g2pdm/i4UD/+rBn2+Iwq1u6/68 IWyq3HwrVudubd1JbzWOa3VI2vc3B6K2fiPBYzm1rAURjhPxIl29WfX0XiDudX5qzWj0 6+I0eFxVdbyoVbi0AoDyEVTc1KyUhIJLubnoptIl/x53rtB38uue9B9xayGUcvoJKlAK 3BcdRH1QfzDQ8Ip5Ap389ZWrCnQxhnoxDjAuiMSG8iEefMqxteic0NDZHbHEAe7eMkAw JPo1iCv0LEq9m/djwDHEI5MDeWTDU/sg530krMWvba/KmToL7E8G138jJc8NhFI1CLz7 3m+Q== X-Gm-Message-State: APf1xPBWuojUYbzFsQE6NpWkWZ8ITJ9dojMuVf9wNhmO7V99tMKeAIF3 YQGM7zdIbjwqGLDMmEdKz39xAZB8+FE= X-Received: by 10.28.105.80 with SMTP id e77mr1847401wmc.123.1519392545894; Fri, 23 Feb 2018 05:29:05 -0800 (PST) Received: from localhost.localdomain ([196.90.4.100]) by smtp.gmail.com with ESMTPSA id x17sm3353453wrg.32.2018.02.23.05.29.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 05:29:04 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Fri, 23 Feb 2018 13:28:58 +0000 Message-Id: <20180223132858.26248-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Subject: [edk2] [RFC PATCH edk2-non-osi] Platform/DeveloperBox: add prebuilt binary containing stage 2 page tables X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Now that the secure firmware image BL31 has been moved back into secure memory where it belongs, we can no longer keep the stage2 translation tables in the same image, given that EL2 is non-secure. So instead, let's put those tables in the NOR flash, at the end of the ARM-TF region. This is difficult to integrate into the build sequence of either ARM-TF or UEFI, so let's just generate the binary and put it at the correct offset using the .fdf description of the platform. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- I am not sure where to put this and how to integrate this into the build, hence the RFC. Platform/Socionext/DeveloperBox/README | 2 + Platform/Socionext/DeveloperBox/stage2_tables.S | 95 ++++++++++++++++++++ Platform/Socionext/DeveloperBox/stage2_tables.bin | Bin 0 -> 20480 bytes 3 files changed, 97 insertions(+) diff --git a/Platform/Socionext/DeveloperBox/stage2_tables.bin b/Platform/Socionext/DeveloperBox/stage2_tables.bin new file mode 100644 index 000000000000..48369f00c022 Binary files /dev/null and b/Platform/Socionext/DeveloperBox/stage2_tables.bin differ -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Socionext/DeveloperBox/README b/Platform/Socionext/DeveloperBox/README index 8f079011e153..5728bf0ef88a 100644 --- a/Platform/Socionext/DeveloperBox/README +++ b/Platform/Socionext/DeveloperBox/README @@ -6,3 +6,5 @@ fip_all_arm_tf.bin - prebuilt ARM Trusted Firmware RELEASE binary Repo: https://git.linaro.org/leg/noupstream/arm-trusted-firmware.git Commit: cd3de9253d90f5ab6eed046fb7bb9f4e9f87ae5a +stage2_tables.bin - prebuilt stage 2 translation tables +Built from stage2_tables.S in the same directory diff --git a/Platform/Socionext/DeveloperBox/stage2_tables.S b/Platform/Socionext/DeveloperBox/stage2_tables.S new file mode 100644 index 000000000000..44da21e7e467 --- /dev/null +++ b/Platform/Socionext/DeveloperBox/stage2_tables.S @@ -0,0 +1,95 @@ +/** @file + Copyright (c) 2018, Linaro, Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +/* + * This file contains the assembler code to instantiate a set of stage 2 + * translation tables that make the ECAM space of the Synopsys DesignWare + * PCIe root complexes appear sane to the OS. + * - ECAM 'shadows' caused by non TLP filtering root ports are eliminated + * - MMIO region are mapped with device attributes that supersede write combine + attributes that the OS may attempt to use, and which is not supported by + the SoC. + * + * Build using: + * + * gcc -o stage2_tables.elf stage2_tables.S \ + * -Wl,-e,0x81f8000 -Wl,--section-start=.rodata=0x81f8000 -nostdlib + * + * objcopy -O binary -j .rodata stage2_tables.elf stage2_tables.bin + */ + +#define TT_S2_CONT_SHIFT 52 +#define TT_S2_AF (0x1 << 10) +#define TT_S2_SH_NON_SHAREABLE (0x0 << 8) +#define TT_S2_AP_RW (0x3 << 6) +#define TT_S2_MEMATTR_DEVICE_nGRE (0x2 << 2) +#define TT_S2_MEMATTR_MEMORY_WB (0xf << 2) +#define TT_S2_TABLE (0x3 << 0) +#define TT_S2_L3_PAGE (0x1 << 1) +#define TT_S2_VALID (0x1 << 0) + + .altmacro + .macro for, start, count, do, arg2, arg3, arg4 + .if \count == 1 + \do \start, \arg2, \arg3, \arg4 + .elseif \count > 1 + for \start, %(\count / 2), \do, \arg2, \arg3, \arg4 + for %(\start + \count / 2), %((\count + 1) / 2), \do, \arg2, \arg3, \arg4 + .endif + .endm + + .macro s2_dev_entry, base, shift=30, offset=0, cont=0 + .quad ((\base << \shift) + \offset) | TT_S2_AF | TT_S2_AP_RW | \ + TT_S2_SH_NON_SHAREABLE | TT_S2_MEMATTR_DEVICE_nGRE | \ + TT_S2_VALID | (\cont << TT_S2_CONT_SHIFT) + .endm + + .macro s2_mem_entry, base, shift=30, offset=0, cont=0 + .quad ((\base << \shift) + \offset) | TT_S2_AF | TT_S2_AP_RW | \ + TT_S2_SH_NON_SHAREABLE | TT_S2_MEMATTR_MEMORY_WB | \ + TT_S2_VALID | (\cont << TT_S2_CONT_SHIFT) + .endm + + .macro s2_l3_entry, base, offset=0, cont=0 + .quad ((\base << 12) + \offset) | TT_S2_AF | TT_S2_AP_RW | \ + TT_S2_SH_NON_SHAREABLE | TT_S2_MEMATTR_MEMORY_WB | \ + TT_S2_L3_PAGE | TT_S2_VALID | (\cont << TT_S2_CONT_SHIFT) + .endm + + .section ".rodata", "a", %progbits + /* level 1 */ + s2_mem_entry 0 /* 0x0000_0000 - 0x3fff_ffff */ + .quad 1f + TT_S2_TABLE /* 0x4000_0000 - 0x7fff_ffff */ + for 2, 246, s2_mem_entry /* 0x8000_0000 - 0x3d_ffff_ffff */ + for 248, 8, s2_dev_entry /* PCIe MMIO64 */ + for 256, 768, s2_mem_entry /* 0x40_0000_0000 - 0xff_ffff_ffff */ + + /* level 2 */ +1: for 0, 256, s2_mem_entry, 21, 0x40000000, 1 + + .quad 2f + TT_S2_TABLE /* 0x6000_0000 -> RC #0 bus 0 */ + for 1, 15, s2_mem_entry, 21, 0x60000000 + for 0, 48, s2_mem_entry, 21, 0x62000000, 1 + for 0, 64, s2_dev_entry, 21, 0x68000000, 1 /* PCIe MMIO32 */ + + .quad 3f + TT_S2_TABLE /* 0x7000_0000 -> RC #1 bus 0 */ + for 1, 15, s2_mem_entry, 21, 0x70000000 + for 0, 48, s2_mem_entry, 21, 0x72000000, 1 + for 0, 64, s2_dev_entry, 21, 0x78000000, 1 /* PCIe MMIO32 */ + + /* level 3 */ +2: for 0, 8, s2_l3_entry, 0x60000000 + for 0, 8, s2_l3_entry, 0x60010000 /* hide device #1 */ + for 0, 496, s2_l3_entry, 0x60010000, 1 +3: for 0, 8, s2_l3_entry, 0x70000000 + for 0, 8, s2_l3_entry, 0x70010000 /* hide device #1 */ + for 0, 496, s2_l3_entry, 0x70010000, 1