From patchwork Fri Feb 23 18:57:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129482 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp984633edc; Fri, 23 Feb 2018 10:59:47 -0800 (PST) X-Google-Smtp-Source: AH8x225b6VtIZ/Rb3aCSiTvFH6TvC6iUDAwzmbzbGnKEIFFPriDVKZZhwrEwF/y6CVJcXkM/0qv+ X-Received: by 10.36.222.2 with SMTP id d2mr3426588itg.1.1519412386939; Fri, 23 Feb 2018 10:59:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519412386; cv=none; d=google.com; s=arc-20160816; b=rrKrPzdW3ZcTOGO+cqoDQsCQUgWvlpWfCYQ8tYJ0/Mm3ZC1SR7x9ADoW4W5MFB1Xzd GzXzFAAV3TVPiObVBmG8MQIANFp30RfP0Ro99tCVQtQNJZsf9ovD/Q9joWB43lSZ/S9H LohH/mcLZe3OF5gx5sqrlZPkqhJVrnHl5nCRYxdhRwSg2XtSpUd8F9gfVyZQprCFJRn+ cmPUBEfEVsbhV6QwwyAhRK3HbpuIa05TXD5hRbUhUTDWE9PwL7lUoM0Uce358NNk4+S8 x7QIuzvxPghK5qFjHj+0DeqDPhMyweYLUal086rP/aXLbvhnbqbKG45xaKEkiJHhxnEf qCLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=0T8rsxLbZfXxgT34et37/h24MSV4npBV4MViKwTuUrg=; b=oG4YycjZ5UcxXBHagmSy7z9KHqWkIpfaV7iGeOZTPObDPcDl12A3Hp9BBqjJ2CTLf4 mNV6FAPYPuro/NQXWNpSseAWvLtvvLSi/j5Syw7IpSst/vno2Hggt5XY48ZvS3+kHoBd 2ykkiKI3EYt/kPvXRvrd0ib3Kf+fActOoe2wx/TaqcrRt2ofNcK/B/pfuz0RdVB4SmFl q6uIWs9mhWleT+DO+womTSfEbDVqBTeeazVUK+Jd6Y7wpv6h9lqCYzevBH+3fphfVtiS MtzfB9i5cpzZPzq+uMAVcO8nZOHpLpyQgF0Ch0sQzPh9NcgHPcPCfYwhXtJtyFyueVfk jWlA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id p193si1567838itg.172.2018.02.23.10.59.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 10:59:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXM-0002pb-9K; Fri, 23 Feb 2018 18:57:40 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXK-0002oY-QF for xen-devel@lists.xen.org; Fri, 23 Feb 2018 18:57:38 +0000 X-Inumbo-ID: 4c7e0600-18cb-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 4c7e0600-18cb-11e8-ba59-bc764e045a96; Fri, 23 Feb 2018 19:56:47 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B2E4115AD; Fri, 23 Feb 2018 10:57:37 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7FE4E3F25C; Fri, 23 Feb 2018 10:57:36 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 18:57:12 +0000 Message-Id: <20180223185729.8780-2-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223185729.8780-1-julien.grall@arm.com> References: <20180223185729.8780-1-julien.grall@arm.com> Cc: Volodymyr Babchuk , Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v5 01/18] xen/arm: psci: Rework the PSCI definitions X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Some PSCI functions are only available in the 32-bit version. After recent changes, Xen always needs to know whether the call was made using 32-bit id or 64-bit id. So we don't emulate reserved one. With the current naming scheme, it is not easy to know which call supports 32-bit and 64-bit id. So rework the definitions to encode the version in the name. From now the functions will be named PSCI_0_2_FNxx where xx is 32 or 64. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini --- Changes in v2: - Add Volodymyr's reviewed-by --- xen/arch/arm/platforms/seattle.c | 4 ++-- xen/arch/arm/psci.c | 10 +++++----- xen/arch/arm/vpsci.c | 22 +++++++++++----------- xen/include/asm-arm/psci.h | 37 +++++++++++++++++++++---------------- 4 files changed, 39 insertions(+), 34 deletions(-) diff --git a/xen/arch/arm/platforms/seattle.c b/xen/arch/arm/platforms/seattle.c index 22c062293f..893cc17972 100644 --- a/xen/arch/arm/platforms/seattle.c +++ b/xen/arch/arm/platforms/seattle.c @@ -33,12 +33,12 @@ static const char * const seattle_dt_compat[] __initconst = */ static void seattle_system_reset(void) { - call_smc(PSCI_0_2_FN32(SYSTEM_RESET), 0, 0, 0); + call_smc(PSCI_0_2_FN32_SYSTEM_RESET, 0, 0, 0); } static void seattle_system_off(void) { - call_smc(PSCI_0_2_FN32(SYSTEM_OFF), 0, 0, 0); + call_smc(PSCI_0_2_FN32_SYSTEM_OFF, 0, 0, 0); } PLATFORM_START(seattle, "SEATTLE") diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c index 1508a3be3a..5dda35cd7c 100644 --- a/xen/arch/arm/psci.c +++ b/xen/arch/arm/psci.c @@ -31,9 +31,9 @@ * (native-width) function ID. */ #ifdef CONFIG_ARM_64 -#define PSCI_0_2_FN_NATIVE(name) PSCI_0_2_FN64(name) +#define PSCI_0_2_FN_NATIVE(name) PSCI_0_2_FN64_##name #else -#define PSCI_0_2_FN_NATIVE(name) PSCI_0_2_FN32(name) +#define PSCI_0_2_FN_NATIVE(name) PSCI_0_2_FN32_##name #endif uint32_t psci_ver; @@ -48,13 +48,13 @@ int call_psci_cpu_on(int cpu) void call_psci_system_off(void) { if ( psci_ver > PSCI_VERSION(0, 1) ) - call_smc(PSCI_0_2_FN32(SYSTEM_OFF), 0, 0, 0); + call_smc(PSCI_0_2_FN32_SYSTEM_OFF, 0, 0, 0); } void call_psci_system_reset(void) { if ( psci_ver > PSCI_VERSION(0, 1) ) - call_smc(PSCI_0_2_FN32(SYSTEM_RESET), 0, 0, 0); + call_smc(PSCI_0_2_FN32_SYSTEM_RESET, 0, 0, 0); } int __init psci_is_smc_method(const struct dt_device_node *psci) @@ -144,7 +144,7 @@ int __init psci_init_0_2(void) } } - psci_ver = call_smc(PSCI_0_2_FN32(PSCI_VERSION), 0, 0, 0); + psci_ver = call_smc(PSCI_0_2_FN32_PSCI_VERSION, 0, 0, 0); /* For the moment, we only support PSCI 0.2 and PSCI 1.x */ if ( psci_ver != PSCI_VERSION(0, 2) && PSCI_VERSION_MAJOR(psci_ver) != 1 ) diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 03fd4eb5b5..6ab8ab64d0 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -243,35 +243,35 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid) */ switch ( fid ) { - case PSCI_0_2_FN32(PSCI_VERSION): + case PSCI_0_2_FN32_PSCI_VERSION: perfc_incr(vpsci_version); PSCI_SET_RESULT(regs, do_psci_0_2_version()); return true; - case PSCI_0_2_FN32(CPU_OFF): + case PSCI_0_2_FN32_CPU_OFF: perfc_incr(vpsci_cpu_off); PSCI_SET_RESULT(regs, do_psci_0_2_cpu_off()); return true; - case PSCI_0_2_FN32(MIGRATE_INFO_TYPE): + case PSCI_0_2_FN32_MIGRATE_INFO_TYPE: perfc_incr(vpsci_migrate_info_type); PSCI_SET_RESULT(regs, do_psci_0_2_migrate_info_type()); return true; - case PSCI_0_2_FN32(SYSTEM_OFF): + case PSCI_0_2_FN32_SYSTEM_OFF: perfc_incr(vpsci_system_off); do_psci_0_2_system_off(); PSCI_SET_RESULT(regs, PSCI_INTERNAL_FAILURE); return true; - case PSCI_0_2_FN32(SYSTEM_RESET): + case PSCI_0_2_FN32_SYSTEM_RESET: perfc_incr(vpsci_system_reset); do_psci_0_2_system_reset(); PSCI_SET_RESULT(regs, PSCI_INTERNAL_FAILURE); return true; - case PSCI_0_2_FN32(CPU_ON): - case PSCI_0_2_FN64(CPU_ON): + case PSCI_0_2_FN32_CPU_ON: + case PSCI_0_2_FN64_CPU_ON: { register_t vcpuid = PSCI_ARG(regs, 1); register_t epoint = PSCI_ARG(regs, 2); @@ -282,8 +282,8 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid) return true; } - case PSCI_0_2_FN32(CPU_SUSPEND): - case PSCI_0_2_FN64(CPU_SUSPEND): + case PSCI_0_2_FN32_CPU_SUSPEND: + case PSCI_0_2_FN64_CPU_SUSPEND: { uint32_t pstate = PSCI_ARG32(regs, 1); register_t epoint = PSCI_ARG(regs, 2); @@ -294,8 +294,8 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid) return true; } - case PSCI_0_2_FN32(AFFINITY_INFO): - case PSCI_0_2_FN64(AFFINITY_INFO): + case PSCI_0_2_FN32_AFFINITY_INFO: + case PSCI_0_2_FN64_AFFINITY_INFO: { register_t taff = PSCI_ARG(regs, 1); uint32_t laff = PSCI_ARG32(regs, 2); diff --git a/xen/include/asm-arm/psci.h b/xen/include/asm-arm/psci.h index 3c44468e72..becc9f9ded 100644 --- a/xen/include/asm-arm/psci.h +++ b/xen/include/asm-arm/psci.h @@ -23,22 +23,27 @@ void call_psci_system_off(void); void call_psci_system_reset(void); /* PSCI v0.2 interface */ -#define PSCI_0_2_FN32(name) ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ - ARM_SMCCC_CONV_32, \ - ARM_SMCCC_OWNER_STANDARD, \ - PSCI_0_2_FN_##name) -#define PSCI_0_2_FN64(name) ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ - ARM_SMCCC_CONV_64, \ - ARM_SMCCC_OWNER_STANDARD, \ - PSCI_0_2_FN_##name) -#define PSCI_0_2_FN_PSCI_VERSION 0 -#define PSCI_0_2_FN_CPU_SUSPEND 1 -#define PSCI_0_2_FN_CPU_OFF 2 -#define PSCI_0_2_FN_CPU_ON 3 -#define PSCI_0_2_FN_AFFINITY_INFO 4 -#define PSCI_0_2_FN_MIGRATE_INFO_TYPE 6 -#define PSCI_0_2_FN_SYSTEM_OFF 8 -#define PSCI_0_2_FN_SYSTEM_RESET 9 +#define PSCI_0_2_FN32(nr) ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_32, \ + ARM_SMCCC_OWNER_STANDARD, \ + nr) +#define PSCI_0_2_FN64(nr) ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_64, \ + ARM_SMCCC_OWNER_STANDARD, \ + nr) + +#define PSCI_0_2_FN32_PSCI_VERSION PSCI_0_2_FN32(0) +#define PSCI_0_2_FN32_CPU_SUSPEND PSCI_0_2_FN32(1) +#define PSCI_0_2_FN32_CPU_OFF PSCI_0_2_FN32(2) +#define PSCI_0_2_FN32_CPU_ON PSCI_0_2_FN32(3) +#define PSCI_0_2_FN32_AFFINITY_INFO PSCI_0_2_FN32(4) +#define PSCI_0_2_FN32_MIGRATE_INFO_TYPE PSCI_0_2_FN32(6) +#define PSCI_0_2_FN32_SYSTEM_OFF PSCI_0_2_FN32(8) +#define PSCI_0_2_FN32_SYSTEM_RESET PSCI_0_2_FN32(9) + +#define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1) +#define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3) +#define PSCI_0_2_FN64_AFFINITY_INFO PSCI_0_2_FN64(4) /* PSCI v0.2 affinity level state returned by AFFINITY_INFO */ #define PSCI_0_2_AFFINITY_LEVEL_ON 0 From patchwork Fri Feb 23 18:57:13 2018 Content-Type: text/plain; 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[192.237.175.120]) by mx.google.com with ESMTPS id l191si1620825ith.138.2018.02.23.10.59.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 10:59:56 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXT-0002rS-G5; Fri, 23 Feb 2018 18:57:47 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXS-0002pr-9d for xen-devel@lists.xen.org; Fri, 23 Feb 2018 18:57:46 +0000 X-Inumbo-ID: a9182e3b-18cb-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id a9182e3b-18cb-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 18:59:23 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7844A80D; Fri, 23 Feb 2018 10:57:39 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F28C03F25C; Fri, 23 Feb 2018 10:57:37 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 18:57:13 +0000 Message-Id: <20180223185729.8780-3-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223185729.8780-1-julien.grall@arm.com> References: <20180223185729.8780-1-julien.grall@arm.com> Cc: sstabellini@kernel.org, Wei Liu , Ian Jackson , andre.przywara@linaro.org, Julien Grall , volodymyr_babchuk@epam.com, mirela.simonovic@aggios.com Subject: [Xen-devel] [PATCH v5 02/18] xen/arm: vpsci: Add support for PSCI 1.1 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment, Xen provides virtual PSCI interface compliant with 0.1 and 0.2. Since them, the specification has been updated and the latest version is 1.1 (see ARM DEN 0022D). >From an implementation point of view, only PSCI_FEATURES is mandatory. The rest is optional and can be left unimplemented for now. At the same time, the compatible for PSCI node have been updated to expose "arm,psci-1.0". Signed-off-by: Julien Grall Acked-by: Wei Liu Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini Cc: Ian Jackson Cc: mirela.simonovic@aggios.com --- We may want to provide a way for the toolstack to specify a PSCI version. This could be useful if a guest is expecting a given version. Changes in v4: - Add Stefano's acked-by Changes in v3: - Add Wei's acked-by - Add Volodymyr's reviewed-by Changes in v2: - Return v1.1 on GET_VERSION call as claimed by this patch - Order by function ID the calls in FEATURES call --- tools/libxl/libxl_arm.c | 3 ++- xen/arch/arm/domain_build.c | 1 + xen/arch/arm/vpsci.c | 39 ++++++++++++++++++++++++++++++++++++++- xen/include/asm-arm/perfc_defn.h | 1 + xen/include/asm-arm/psci.h | 1 + xen/include/asm-arm/vpsci.h | 2 +- 6 files changed, 44 insertions(+), 3 deletions(-) diff --git a/tools/libxl/libxl_arm.c b/tools/libxl/libxl_arm.c index 3e46554301..86f59c0d80 100644 --- a/tools/libxl/libxl_arm.c +++ b/tools/libxl/libxl_arm.c @@ -410,7 +410,8 @@ static int make_psci_node(libxl__gc *gc, void *fdt) res = fdt_begin_node(fdt, "psci"); if (res) return res; - res = fdt_property_compat(gc, fdt, 2, "arm,psci-0.2","arm,psci"); + res = fdt_property_compat(gc, fdt, 3, "arm,psci-1.0", + "arm,psci-0.2", "arm,psci"); if (res) return res; res = fdt_property_string(fdt, "method", "hvc"); diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 155c952349..941688a2ce 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -637,6 +637,7 @@ static int make_psci_node(void *fdt, const struct dt_device_node *parent) { int res; const char compat[] = + "arm,psci-1.0""\0" "arm,psci-0.2""\0" "arm,psci"; diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 6ab8ab64d0..e82b62db1a 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -106,7 +106,11 @@ static int32_t do_psci_cpu_off(uint32_t power_state) static uint32_t do_psci_0_2_version(void) { - return PSCI_VERSION(0, 2); + /* + * PSCI is backward compatible from 0.2. So we can bump the version + * without any issue. + */ + return PSCI_VERSION(1, 1); } static register_t do_psci_0_2_cpu_suspend(uint32_t power_state, @@ -191,6 +195,29 @@ static void do_psci_0_2_system_reset(void) domain_shutdown(d,SHUTDOWN_reboot); } +static int32_t do_psci_1_0_features(uint32_t psci_func_id) +{ + /* /!\ Ordered by function ID and not name */ + switch ( psci_func_id ) + { + case PSCI_0_2_FN32_PSCI_VERSION: + case PSCI_0_2_FN32_CPU_SUSPEND: + case PSCI_0_2_FN64_CPU_SUSPEND: + case PSCI_0_2_FN32_CPU_OFF: + case PSCI_0_2_FN32_CPU_ON: + case PSCI_0_2_FN64_CPU_ON: + case PSCI_0_2_FN32_AFFINITY_INFO: + case PSCI_0_2_FN64_AFFINITY_INFO: + case PSCI_0_2_FN32_MIGRATE_INFO_TYPE: + case PSCI_0_2_FN32_SYSTEM_OFF: + case PSCI_0_2_FN32_SYSTEM_RESET: + case PSCI_1_0_FN32_PSCI_FEATURES: + return 0; + default: + return PSCI_NOT_SUPPORTED; + } +} + #define PSCI_SET_RESULT(reg, val) set_user_reg(reg, 0, val) #define PSCI_ARG(reg, n) get_user_reg(reg, n) @@ -304,6 +331,16 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid) PSCI_SET_RESULT(regs, do_psci_0_2_affinity_info(taff, laff)); return true; } + + case PSCI_1_0_FN32_PSCI_FEATURES: + { + uint32_t psci_func_id = PSCI_ARG32(regs, 1); + + perfc_incr(vpsci_features); + PSCI_SET_RESULT(regs, do_psci_1_0_features(psci_func_id)); + return true; + } + default: return false; } diff --git a/xen/include/asm-arm/perfc_defn.h b/xen/include/asm-arm/perfc_defn.h index a7acb7d21c..87866264ca 100644 --- a/xen/include/asm-arm/perfc_defn.h +++ b/xen/include/asm-arm/perfc_defn.h @@ -31,6 +31,7 @@ PERFCOUNTER(vpsci_system_off, "vpsci: system_off") PERFCOUNTER(vpsci_system_reset, "vpsci: system_reset") PERFCOUNTER(vpsci_cpu_suspend, "vpsci: cpu_suspend") PERFCOUNTER(vpsci_cpu_affinity_info, "vpsci: cpu_affinity_info") +PERFCOUNTER(vpsci_features, "vpsci: features") PERFCOUNTER(vgicd_reads, "vgicd: read") PERFCOUNTER(vgicd_writes, "vgicd: write") diff --git a/xen/include/asm-arm/psci.h b/xen/include/asm-arm/psci.h index becc9f9ded..e2629eed01 100644 --- a/xen/include/asm-arm/psci.h +++ b/xen/include/asm-arm/psci.h @@ -40,6 +40,7 @@ void call_psci_system_reset(void); #define PSCI_0_2_FN32_MIGRATE_INFO_TYPE PSCI_0_2_FN32(6) #define PSCI_0_2_FN32_SYSTEM_OFF PSCI_0_2_FN32(8) #define PSCI_0_2_FN32_SYSTEM_RESET PSCI_0_2_FN32(9) +#define PSCI_1_0_FN32_PSCI_FEATURES PSCI_0_2_FN32(10) #define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1) #define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3) diff --git a/xen/include/asm-arm/vpsci.h b/xen/include/asm-arm/vpsci.h index 035a41e812..0cca5e6830 100644 --- a/xen/include/asm-arm/vpsci.h +++ b/xen/include/asm-arm/vpsci.h @@ -23,7 +23,7 @@ #include /* Number of function implemented by virtual PSCI (only 0.2 or later) */ -#define VPSCI_NR_FUNCS 11 +#define VPSCI_NR_FUNCS 12 /* Functions handle PSCI calls from the guests */ bool do_vpsci_0_1_call(struct cpu_user_regs *regs, uint32_t fid); From patchwork Fri Feb 23 18:57:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129481 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp984595edc; Fri, 23 Feb 2018 10:59:43 -0800 (PST) X-Google-Smtp-Source: AG47ELvNxi3Ouks7+E5eIiR3J8iolk7aPaS4pdTZQh6sttyCUPykBIYpJR1dnpMR9o/nNjuivKNS X-Received: by 10.107.43.7 with SMTP id r7mr2835224ior.302.1519412383681; Fri, 23 Feb 2018 10:59:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519412383; cv=none; d=google.com; s=arc-20160816; b=zH8yx8gjRtePJBt3KRTxLdJgb4KdaX0lkRXLW4LyXLqK1yJA1lZ6mrR06W8uewJzvV xzo0h4o00OuuiU6In7NXwjn/utVU55FV1NwWTxlm+JoAQWjBh+eXIB1t0yIpcMUP4fHL VkVqROoyKx2PJxfZxIPvGUJq20Ck7M59HzNXFcW1ziulXo2LNIdT3abmcjwrU0I/k4cX BiOZh0+r60r8YANQtlv5zDVdEjmDXbABna36o5rzMaEYrjvBRBlSqNGTuGMMzWRV2rfF TcJi/E7ptqV3rvtsdWKy2FTyv9dXlNViVjJE5TnhH4+aC50g3bOJcZy7EkgHuuPoTExC LSOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=zr/c9WoQdsMIjrG5E2R0VY9hIoZooIANEfaHS7aXUH0=; b=WAgJ6JUm5vX4BVPITACqW8VrUvqBIZWSG8yXS5aryonNFdBq0zmhCkc/79wXsCu6t3 BMDorn7EfS3pEjotOApmNK0IDg69YNulDUzDBPjjAcFY2JqtYlOahO3p9TmC22Y/eveg doDCuXzM4P012O/PIxIqF/E8ZrFbdUVgg1ry/YhuKEhs/H8Dl15II9PtzdlcMxrf2A70 98BUrGrfplWo2mSkyrDbVzWBdBl7/HPdD2wtFQXEs0u+7k/X4dvnOeee6JxbhHJOClme L2n1r6PE8SmmMLFi/qRgPlRfx0lbUaYxOsCYV+nBPEqufbuMIqZctvqleFe5yelbXLTn CmTw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id c126si2020288ioc.311.2018.02.23.10.59.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 10:59:43 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXT-0002sP-U0; Fri, 23 Feb 2018 18:57:47 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXT-0002py-81 for xen-devel@lists.xen.org; Fri, 23 Feb 2018 18:57:47 +0000 X-Inumbo-ID: a9f6e8d9-18cb-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id a9f6e8d9-18cb-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 18:59:24 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EA52115BE; Fri, 23 Feb 2018 10:57:40 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B74143F25C; Fri, 23 Feb 2018 10:57:39 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 18:57:14 +0000 Message-Id: <20180223185729.8780-4-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223185729.8780-1-julien.grall@arm.com> References: <20180223185729.8780-1-julien.grall@arm.com> Cc: Volodymyr Babchuk , Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v5 03/18] xen/arm: vsmc: Implement SMCCC 1.1 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The new SMC Calling Convention (v1.1) allows for a reduced overhead when calling into the firmware, and provides a new feature discovery mechanism. See "Firmware interfaces for mitigating CVE-2017-5715" ARM DEN 00070A. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini --- Changes in v4: - Add Volodymyr's reviewed-by - Add Stefano's acked-by Changes in v3: - Use ARM_SMCCC_NOT_SUPPORTED rather than hardcoded return Changes in v2: - Add a humand readable name for the specification --- xen/arch/arm/vpsci.c | 1 + xen/arch/arm/vsmc.c | 23 +++++++++++++++++++++++ xen/include/asm-arm/smccc.h | 18 +++++++++++++++++- 3 files changed, 41 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index e82b62db1a..19ee7caeb4 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -212,6 +212,7 @@ static int32_t do_psci_1_0_features(uint32_t psci_func_id) case PSCI_0_2_FN32_SYSTEM_OFF: case PSCI_0_2_FN32_SYSTEM_RESET: case PSCI_1_0_FN32_PSCI_FEATURES: + case ARM_SMCCC_VERSION_FID: return 0; default: return PSCI_NOT_SUPPORTED; diff --git a/xen/arch/arm/vsmc.c b/xen/arch/arm/vsmc.c index 3d3bd95fee..7ec492741b 100644 --- a/xen/arch/arm/vsmc.c +++ b/xen/arch/arm/vsmc.c @@ -81,6 +81,26 @@ static bool fill_function_call_count(struct cpu_user_regs *regs, uint32_t cnt) return true; } +/* SMCCC interface for ARM Architecture */ +static bool handle_arch(struct cpu_user_regs *regs) +{ + uint32_t fid = (uint32_t)get_user_reg(regs, 0); + + switch ( fid ) + { + case ARM_SMCCC_VERSION_FID: + set_user_reg(regs, 0, ARM_SMCCC_VERSION_1_1); + return true; + + case ARM_SMCCC_ARCH_FEATURES_FID: + /* Nothing supported yet */ + set_user_reg(regs, 0, ARM_SMCCC_NOT_SUPPORTED); + return true; + } + + return false; +} + /* SMCCC interface for hypervisor. Tell about itself. */ static bool handle_hypervisor(struct cpu_user_regs *regs) { @@ -188,6 +208,9 @@ static bool vsmccc_handle_call(struct cpu_user_regs *regs) { switch ( smccc_get_owner(funcid) ) { + case ARM_SMCCC_OWNER_ARCH: + handled = handle_arch(regs); + break; case ARM_SMCCC_OWNER_HYPERVISOR: handled = handle_hypervisor(regs); break; diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 62b3a8cdf5..629cc5150b 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -16,6 +16,9 @@ #ifndef __ASM_ARM_SMCCC_H__ #define __ASM_ARM_SMCCC_H__ +#define ARM_SMCCC_VERSION_1_0 0x10000 +#define ARM_SMCCC_VERSION_1_1 0x10001 + /* * This file provides common defines for ARM SMC Calling Convention as * specified in @@ -100,8 +103,21 @@ static inline uint32_t smccc_get_owner(register_t funcid) ARM_SMCCC_OWNER_##owner, \ 0xFF03) -/* Only one error code defined in SMCCC */ +#define ARM_SMCCC_VERSION_FID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_32, \ + ARM_SMCCC_OWNER_ARCH, \ + 0x0) \ + +#define ARM_SMCCC_ARCH_FEATURES_FID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_32, \ + ARM_SMCCC_OWNER_ARCH, \ + 0x1) + +/* SMCCC error codes */ #define ARM_SMCCC_ERR_UNKNOWN_FUNCTION (-1) +#define ARM_SMCCC_NOT_SUPPORTED (-1) /* SMCCC function identifier range which is reserved for existing APIs */ #define ARM_SMCCC_RESERVED_RANGE_START 0x0 From patchwork Fri Feb 23 18:57:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129486 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp984761edc; Fri, 23 Feb 2018 10:59:55 -0800 (PST) X-Google-Smtp-Source: AH8x2250dj2Mxlj+0hKG8TuYDy1j8msGwKvcmnTPZe3i5N5iY2F3nXy0SiaB0i6zNVVdV/6hrLCG X-Received: by 10.36.221.65 with SMTP id t62mr3502182itf.14.1519412395087; Fri, 23 Feb 2018 10:59:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519412395; cv=none; d=google.com; s=arc-20160816; b=e9f20XC3GDkSpvFacItQ90oiZdBqJgicurUmlzbonWn7xJ5VrEL6CawkUpu59OSsFV 8aOzKnedaPqtkiO1rN1a5D3W6s74zswZhjgAJTLTam7Xk9VsCh0FcgUZpz4zIVB9Lflf GWwYOqo8oD0dyPXCVPBUndUf7BDZxJwRwVcKzG5/VMnlfQ0cF/akc0bS3Bjd3H6s0Pjf fo7Y9Dq2j6mpBoWja2vuWuu8fxOwxrZgpuSdBWITYyIRSOW1zRUlWzTN8LGTJG6q4TBI kbaUzF4p3N6pZd8Q1GZ+EEH6Xhnc+sQZBmVUrurdRrzntknAtuMN3+HecsDN9VM2f7Od riYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=EGcMWK361zSDhdPwgGeE37gSSqTQA+Oii0sObGVatDA=; b=zCT4R1W1u44I6o4iGRTj9P0SiV6pntozTWSq8MNaSbKKnxCEdgFrc/1i+HBCAg6tdT wOL22KLeJEEdcBsmb07+SwBtLSJ4FjVN5XgU4pet6sTWjPRJMuNJ57oNn+2c7tCOxOJr c8lpOa8AonEhbuek226iRPcZLZcjMP2H9ZZUgPdUxm+aJMWKEo6XYb8uuNsVxfIQYd+C gbFQPcnl8bzfNG3c0FWBYpjdoWrd5e7xoicg0fvLE90/ZO4i2wlwDmWAjpdCpDJVqbhN 6KtKfoUIp2wfRQXyMXoKyf4IKqnHkHUvbQe/EUhR6HcaAQfGzJVlolsWKfktuACkfyNY Lpeg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 94si2001835iom.270.2018.02.23.10.59.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 10:59:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXW-0002up-7b; Fri, 23 Feb 2018 18:57:50 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXV-0002qC-2U for xen-devel@lists.xen.org; Fri, 23 Feb 2018 18:57:49 +0000 X-Inumbo-ID: aaec30e1-18cb-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id aaec30e1-18cb-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 18:59:26 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8C17315BF; Fri, 23 Feb 2018 10:57:42 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 358B03F25C; Fri, 23 Feb 2018 10:57:41 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 18:57:15 +0000 Message-Id: <20180223185729.8780-5-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223185729.8780-1-julien.grall@arm.com> References: <20180223185729.8780-1-julien.grall@arm.com> Cc: sstabellini@kernel.org, Andre Przywara , andre.przywara@linaro.org, Volodymyr Babchuk , Julien Grall , volodymyr_babchuk@epam.com Subject: [Xen-devel] [PATCH v5 04/18] xen/arm: vsmc: Implement SMCCC_ARCH_WORKAROUND_1 BP hardening support X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" SMCCC 1.1 offers firmware-based CPU workarounds. In particular, SMCCC_ARCH_WORKAROUND_1 provides BP hardening for variant 2 of XSA-254 (CVE-2017-5715). If the hypervisor has some mitigation for this issue, report that we deal with it using SMCCC_ARCH_WORKAROUND_1, as we apply the hypervisor workaround on every guest exit. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini Reviewed-by: Andre Przywara --- Changes in v4: - Add Stefano's acked-by - Add Andre's reviewed-by Changes in v3: - Fix minor conflict during rebase Changes in v2: - Add Volodymyr's reviewed-by --- xen/arch/arm/vsmc.c | 22 ++++++++++++++++++++-- xen/include/asm-arm/smccc.h | 6 ++++++ 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vsmc.c b/xen/arch/arm/vsmc.c index 7ec492741b..40a80d5760 100644 --- a/xen/arch/arm/vsmc.c +++ b/xen/arch/arm/vsmc.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -93,8 +94,25 @@ static bool handle_arch(struct cpu_user_regs *regs) return true; case ARM_SMCCC_ARCH_FEATURES_FID: - /* Nothing supported yet */ - set_user_reg(regs, 0, ARM_SMCCC_NOT_SUPPORTED); + { + uint32_t arch_func_id = get_user_reg(regs, 1); + int ret = ARM_SMCCC_NOT_SUPPORTED; + + switch ( arch_func_id ) + { + case ARM_SMCCC_ARCH_WORKAROUND_1_FID: + if ( cpus_have_cap(ARM_HARDEN_BRANCH_PREDICTOR) ) + ret = 0; + break; + } + + set_user_reg(regs, 0, ret); + + return true; + } + + case ARM_SMCCC_ARCH_WORKAROUND_1_FID: + /* No return value */ return true; } diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 629cc5150b..2951caa49d 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -115,6 +115,12 @@ static inline uint32_t smccc_get_owner(register_t funcid) ARM_SMCCC_OWNER_ARCH, \ 0x1) +#define ARM_SMCCC_ARCH_WORKAROUND_1_FID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_32, \ + ARM_SMCCC_OWNER_ARCH, \ + 0x8000) + /* SMCCC error codes */ #define ARM_SMCCC_ERR_UNKNOWN_FUNCTION (-1) #define ARM_SMCCC_NOT_SUPPORTED (-1) From patchwork Fri Feb 23 18:57:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129496 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp989858edc; Fri, 23 Feb 2018 11:03:49 -0800 (PST) X-Google-Smtp-Source: AH8x227sfAid5Ld3HcdPdz98xccAOiKClNREAXX5tMWmyjM3iuZxbKA0wCjMKWBbXicjFubExLlQ X-Received: by 10.36.60.82 with SMTP id m79mr3493301ita.152.1519412629513; Fri, 23 Feb 2018 11:03:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519412629; cv=none; d=google.com; s=arc-20160816; b=0OPAr6io40x8AmhXN6QEKCct8ylsqmcCxozW3uF6VICcE4Doekcc1KrIQKv10KOClA fHmIrjFzDtRVfJlmnom8Xa00FWYreE/2TBYqrKCWRL0qjbNJOqFGxnKHYB207nJ8wupV e1wC68mTWnjZBx+whGF8PV08z7PFWJYsDP9fi1u7VTlWzxuRqkKC5rZND4DpVJH8d0q0 ETtd2mdTBTOw2/Ok+q601DudxRS/axylwPFpEp92Rc/Y16198/BE7wM4R6U7LFWFrciI 98a+Bu6k3Qii9eVU16i+GkLfNcuG27u4H9XHa4zKWDUzqQOcgs/VKBpqc+Pb478H7+c3 HHcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=iXMIlbb5R7i958r5o8tW/gx+oFtHbmJfyI4VuVKvGac=; b=GKiQ5bf7eXQBzBcn/eWX3e4DARtfdiNRgXD2d9I0GKxYi2qu09/c3C6cr4AooNGY2e lDC4R6U2dX/2ErBZ5W2khbiU9R0K1hDjeJQK7G1jShSbvQJ3BFd+gLB0ffu+y7xk1oa7 RmmEKcpOy/BTReAEHqqOFdPY7bKAgefEMdXGw1JwRj9FPevXTud/4UpzOyROFS+hbRoo OwrnvgVgqu58bxh4vWksDIj3u2w+XC/jUwySHrYxr5QMBVr308rapbkVtOxtozxS2qVM d3xCrELYZ/icxprz9xNLi/3LS9LLum2hWxv/qR5eGGLsSw4qn9BW9L8rpiLjC88H609u CBow== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id m27si2376231ioo.216.2018.02.23.11.03.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 11:03:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIbj-0005TR-Ml; Fri, 23 Feb 2018 19:02:11 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIbi-0005T7-7p for xen-devel@lists.xen.org; Fri, 23 Feb 2018 19:02:10 +0000 X-Inumbo-ID: abcc582b-18cb-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id abcc582b-18cb-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 18:59:27 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 09FE180D; Fri, 23 Feb 2018 10:57:44 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CB1463F25C; Fri, 23 Feb 2018 10:57:42 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 18:57:16 +0000 Message-Id: <20180223185729.8780-6-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223185729.8780-1-julien.grall@arm.com> References: <20180223185729.8780-1-julien.grall@arm.com> Cc: Volodymyr Babchuk , Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v5 05/18] xen/arm: Adapt smccc.h to be able to use it in assembly code X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini --- Changes in v4: - Add Stefano's acked-by Changes in v2: - Add Volodymyr's reviewed-by --- xen/include/asm-arm/smccc.h | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 2951caa49d..30208d12ca 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -25,18 +25,20 @@ * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html */ -#define ARM_SMCCC_STD_CALL 0U -#define ARM_SMCCC_FAST_CALL 1U +#define ARM_SMCCC_STD_CALL _AC(0,U) +#define ARM_SMCCC_FAST_CALL _AC(1,U) #define ARM_SMCCC_TYPE_SHIFT 31 -#define ARM_SMCCC_CONV_32 0U -#define ARM_SMCCC_CONV_64 1U +#define ARM_SMCCC_CONV_32 _AC(0,U) +#define ARM_SMCCC_CONV_64 _AC(1,U) #define ARM_SMCCC_CONV_SHIFT 30 -#define ARM_SMCCC_OWNER_MASK 0x3FU +#define ARM_SMCCC_OWNER_MASK _AC(0x3F,U) #define ARM_SMCCC_OWNER_SHIFT 24 -#define ARM_SMCCC_FUNC_MASK 0xFFFFU +#define ARM_SMCCC_FUNC_MASK _AC(0xFFFF,U) + +#ifndef __ASSEMBLY__ /* Check if this is fast call. */ static inline bool smccc_is_fast_call(register_t funcid) @@ -62,6 +64,8 @@ static inline uint32_t smccc_get_owner(register_t funcid) return (funcid >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK; } +#endif + /* * Construct function identifier from call type (fast or standard), * calling convention (32 or 64 bit), service owner and function number. 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[192.237.175.120]) by mx.google.com with ESMTPS id a9si615787ioe.183.2018.02.23.10.59.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 10:59:48 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXT-0002rr-Ms; Fri, 23 Feb 2018 18:57:47 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXT-0002r9-66 for xen-devel@lists.xen.org; Fri, 23 Feb 2018 18:57:47 +0000 X-Inumbo-ID: 511eaa7d-18cb-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 511eaa7d-18cb-11e8-ba59-bc764e045a96; Fri, 23 Feb 2018 19:56:55 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7B97C15AD; Fri, 23 Feb 2018 10:57:45 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 48F953F25C; Fri, 23 Feb 2018 10:57:44 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 18:57:17 +0000 Message-Id: <20180223185729.8780-7-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223185729.8780-1-julien.grall@arm.com> References: <20180223185729.8780-1-julien.grall@arm.com> Cc: Volodymyr Babchuk , Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v5 06/18] xen/arm64: Implement a fast path for handling SMCCC_ARCH_WORKAROUND_1 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The function SMCCC_ARCH_WORKAROUND_1 will be called by the guest for hardening the branch predictor. So we want the handling to be as fast as possible. As the mitigation is applied on every guest exit, we can check for the call before saving all the context and return very early. For now, only provide a fast path for HVC64 call. Because the code rely on 2 registers, x0 and x1 are saved in advance. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Reviewed-by: Stefano Stabellini Reviewed-by: Andre Przywara --- guest_sync only handle 64-bit guest, so I have only implemented the 64-bit side for now. We can discuss whether it is useful to implement it for 32-bit guests. We could also consider to implement the fast path for SMC64, althought a guest should always use HVC. I decided to keep the reviewed-by as mostly the documentation was updated to make it clearer. Changes in v4: - Add Stefano's reviewed-by - Use xzr to clobber x1 instead of x0 - Update comments in the code Changes in v2: - Add Volodymyr's reviewed-by --- xen/arch/arm/arm64/entry.S | 59 +++++++++++++++++++++++++++++++++++++++-- xen/include/asm-arm/processor.h | 2 ++ 2 files changed, 59 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/arm64/entry.S b/xen/arch/arm/arm64/entry.S index 6d99e46f0f..ffa9a1c492 100644 --- a/xen/arch/arm/arm64/entry.S +++ b/xen/arch/arm/arm64/entry.S @@ -1,6 +1,7 @@ #include #include #include +#include #include /* @@ -90,8 +91,12 @@ lr .req x30 /* link register */ .endm /* * Save state on entry to hypervisor, restore on exit + * + * save_x0_x1: Does the macro needs to save x0/x1? Defaults to 1 + * If 0, we rely on the on x0/x1 to have been saved at the correct + * position on the stack before. */ - .macro entry, hyp, compat + .macro entry, hyp, compat, save_x0_x1=1 sub sp, sp, #(UREGS_SPSR_el1 - UREGS_LR) /* CPSR, PC, SP, LR */ push x28, x29 push x26, x27 @@ -107,7 +112,16 @@ lr .req x30 /* link register */ push x6, x7 push x4, x5 push x2, x3 + /* + * The caller may already have saved x0/x1 on the stack at the + * correct address and corrupt them with another value. Only + * save them if save_x0_x1 == 1. + */ + .if \save_x0_x1 == 1 push x0, x1 + .else + sub sp, sp, #16 + .endif .if \hyp == 1 /* Hypervisor mode */ @@ -200,7 +214,48 @@ hyp_irq: exit hyp=1 guest_sync: - entry hyp=0, compat=0 + /* + * Save x0, x1 in advance + */ + stp x0, x1, [sp, #-(UREGS_kernel_sizeof - UREGS_X0)] + + /* + * x1 is used because x0 may contain the function identifier. + * This avoids to restore x0 from the stack. + */ + mrs x1, esr_el2 + lsr x1, x1, #HSR_EC_SHIFT /* x1 = ESR_EL2.EC */ + cmp x1, #HSR_EC_HVC64 + b.ne 1f /* Not a HVC skip fastpath. */ + + mrs x1, esr_el2 + and x1, x1, #0xffff /* Check the immediate [0:16] */ + cbnz x1, 1f /* should be 0 for HVC #0 */ + + /* + * Fastest path possible for ARM_SMCCC_ARCH_WORKAROUND_1. + * The workaround has already been applied on the exception + * entry from the guest, so let's quickly get back to the guest. + * + * Note that eor is used because the function identifier cannot + * be encoded as an immediate for cmp. + */ + eor w0, w0, #ARM_SMCCC_ARCH_WORKAROUND_1_FID + cbnz w0, 1f + + /* + * Clobber both x0 and x1 to prevent leakage. Note that thanks + * the eor, x0 = 0. + */ + mov x1, xzr + eret + +1: + /* + * x0/x1 may have been scratch by the fast path above, so avoid + * to save them. + */ + entry hyp=0, compat=0, save_x0_x1=0 /* * The vSError will be checked while SKIP_SYNCHRONIZE_SERROR_ENTRY_EXIT * is not set. If a vSError took place, the initial exception will be diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index c0f79d0093..222a02dd99 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -306,6 +306,8 @@ #define HDCR_TPM (_AC(1,U)<<6) /* Trap Performance Monitors accesses */ #define HDCR_TPMCR (_AC(1,U)<<5) /* Trap PMCR accesses */ +#define HSR_EC_SHIFT 26 + #define HSR_EC_UNKNOWN 0x00 #define HSR_EC_WFI_WFE 0x01 #define HSR_EC_CP15_32 0x03 From patchwork Fri Feb 23 18:57:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129484 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp984716edc; Fri, 23 Feb 2018 10:59:53 -0800 (PST) X-Google-Smtp-Source: AH8x225fgGW8h0HbIiL2RFx6WFzAav7aeEesbRHuSknPRE2s4Vmda28ZyOGDVG4mJubYeAxvZAwe X-Received: by 10.107.174.14 with SMTP id x14mr2937794ioe.67.1519412393094; Fri, 23 Feb 2018 10:59:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519412393; cv=none; d=google.com; s=arc-20160816; b=DQkxMEbiHfekExn9X2jIqFZ/b48L0w88L3WwJBB/2smdpdvK9knNDPE19/yOkJq27V ngbzFUmuQn/AhLGd8NLBEZR8LwYXesKBsMiI588KYw8Al76QfMNaDzwgsAosafD/cJae FYLbgb5J2zbHrJ+4ZYR0ZUM4MnwppQKFWc/QtKdVeDHMKfGYnRrvGfN7LlBQ/1ETjSyU iuhmckiXO2+uqzQKYcFOXeKMW8fUEgUVkcjIl0IlQDLp42qsP0AIu0hYDTjcFnuVeNFp so3CZOl7OtlnwC2gXzEBOhR+/QHxwCn1DF/4x9Iheo5FomkWynCc3OQaaJyZaoONq8pw sUWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=uPwbeDSBnqpBAC1UWK41FRLJiu+G5+8+KUUtGjn1vmI=; b=PolP0fhHMoiY0T0Xaa9pBrNUY8b6/UK6hRRYujpaL8Lr9QvGfY1iwSy+NBjTqGCyBi E4V0+avLD/vqndrKTcxdfz4fa3e2UFkkRQmwKpUXSvQb05RI0CkuTq1kxWh5u9G1kx0e nmx5sCdYtmGuFsVFSQ6FSUVaGvpDb6bKmk1fSvCKv2McViMn4kz7zYIFTXP4np2fAtDk UyeHvaxb2V0m8Q6Dgik6jgp4iUkSaevSVYGfeF2t4PqGZ8+iJgqSs2Usu/9CuFvM/yEO 8LyfzGMmx+73+MEX262YWt8qVtGieiNNTByVNkDMzfRVC1rhthIBXsug3r6aCCCD4IxQ UqFg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id n15si1927170iob.258.2018.02.23.10.59.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 10:59:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXZ-0002yE-TA; Fri, 23 Feb 2018 18:57:53 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXZ-0002t5-Cy for xen-devel@lists.xen.org; Fri, 23 Feb 2018 18:57:53 +0000 X-Inumbo-ID: ad75ebd4-18cb-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id ad75ebd4-18cb-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 18:59:30 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CB06180D; Fri, 23 Feb 2018 10:57:46 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BBC4E3F25C; Fri, 23 Feb 2018 10:57:45 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 18:57:18 +0000 Message-Id: <20180223185729.8780-8-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223185729.8780-1-julien.grall@arm.com> References: <20180223185729.8780-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v5 07/18] xen/arm64: Print a per-CPU message with the BP hardening method used X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" This will make easier to know whether BP hardening has been enabled for a CPU and which method is used. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babcuk Acked-by: Stefano Stabellini --- Changes in v4: - Add Stefano's acked-by Changes in v3: - Add Volodymyr's reviewed-by Changes in v2: - Patch added --- xen/arch/arm/cpuerrata.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index c243521ed4..8d5f8d372a 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -79,7 +79,8 @@ static bool copy_hyp_vect_bpi(unsigned int slot, const char *hyp_vec_start, static bool __maybe_unused install_bp_hardening_vec(const struct arm_cpu_capabilities *entry, const char *hyp_vec_start, - const char *hyp_vec_end) + const char *hyp_vec_end, + const char *desc) { static int last_slot = -1; static DEFINE_SPINLOCK(bp_lock); @@ -94,6 +95,9 @@ install_bp_hardening_vec(const struct arm_cpu_capabilities *entry, if ( !entry->matches(entry) ) return true; + printk(XENLOG_INFO "CPU%u will %s on exception entry\n", + smp_processor_id(), desc); + /* * No need to install hardened vector when the processor has * ID_AA64PRF0_EL1.CSV2 set. @@ -157,7 +161,8 @@ static int enable_psci_bp_hardening(void *data) */ if ( psci_ver >= PSCI_VERSION(0, 2) ) ret = install_bp_hardening_vec(data, __psci_hyp_bp_inval_start, - __psci_hyp_bp_inval_end); + __psci_hyp_bp_inval_end, + "call PSCI get version"); else if ( !warned ) { ASSERT(system_state < SYS_STATE_active); From patchwork Fri Feb 23 18:57:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129490 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp984801edc; Fri, 23 Feb 2018 10:59:57 -0800 (PST) X-Google-Smtp-Source: AG47ELuWPYFaheIEnmLw/PugI8qL2GXPAf+3PJLnOqu6L+3svL0cYSaFU5H8NdI7330lEerMEchx X-Received: by 10.107.35.7 with SMTP id j7mr2780732ioj.226.1519412397693; Fri, 23 Feb 2018 10:59:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519412397; cv=none; d=google.com; s=arc-20160816; b=NF9SrqDAN2HSDCISTG31H6voPWg/0wR8KxTnb4/by83l84mlV0FKUo0HjL8Jz89hKq c0eb8d5a61c53DAC9PbNDUOztNqaFVUaJmBvRJ+COsSDSg+oQFcthv2TX7BaZn+mYULg 792j8amOTtvjR0AiCTAgUxMGOxOVfZAhTsBqqZo1oAVVp2ys7B6iIKPPHSuZpxnB6ycy 5h28ywFcvbFE7Se4JAODM4/yEomtcSc5un0wrJxisPM18eGZm8YhHqqGH3+zRkQjzt8W Hph78MQJKmDBASOSnRBDShRfZnQVRGHitZZqj4eB+UKUed1FHz+yahESXSS6FtarTDIG 2XGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=s+1udkVf3pJCOsgGEF4cgOdrtCju8yo6x5hGdOYKPIU=; b=LUp+R+qSUXERHmUCLa6wWzC0IKFWNlytnk75RFWtpoGEjXCv251nNurufLcFnF6YBW L4Evg8ntJGVxA/69w/OU4FtBSok2KZcFWqsl7Qq5DpuOF+8l5yPe8bjbi0KtlL+zARG+ la//Ta68EPr63LKjaBYeuCrnSqPxopZwjZzKzE4zLCjUNp/RwipR7MwQ+or3WabwESgj WAAkiOoap+un9A00sLIyRP+Q/DZjBoKX8FywaTMOEzOI61FW1R9KyufUsncP4NyyoBD4 qGhpfjhdVudSUVp5nUwE/mRHF9JRXe0CV0gGcPosCBdek5omPfET41qVVr2F35WymjNA 0EHA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id v13si1707577itv.7.2018.02.23.10.59.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 10:59:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXX-0002vy-Et; Fri, 23 Feb 2018 18:57:51 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXV-0002tq-G6 for xen-devel@lists.xen.org; Fri, 23 Feb 2018 18:57:49 +0000 X-Inumbo-ID: 52b18d44-18cb-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 52b18d44-18cb-11e8-ba59-bc764e045a96; Fri, 23 Feb 2018 19:56:58 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2518715AD; Fri, 23 Feb 2018 10:57:48 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 15E6E3F25C; Fri, 23 Feb 2018 10:57:46 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 18:57:19 +0000 Message-Id: <20180223185729.8780-9-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223185729.8780-1-julien.grall@arm.com> References: <20180223185729.8780-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v5 08/18] xen/arm: smccc: Add macros SMCCC_VERSION, SMCCC_VERSION_{MINOR, MAJOR} X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Add macros SMCCC_VERSION, SMCCC_VERSION_{MINOR, MAJOR} to easily convert between a 32-bit value and a version number. The encoding is based on 2.2.2 in "Firmware interfaces for mitigation CVE-2017-5715" (ARM DEN 0070A). Also re-use them to define ARM_SMCCC_VERSION_1_0 and ARM_SMCCC_VERSION_1_1. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini --- Changes in v4: - Add Stefano's acked-by Changes in v3: - Add Volodymyr's reviewed-by Changes in v2: - Patch added --- xen/include/asm-arm/smccc.h | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 30208d12ca..d0240d64bf 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -16,8 +16,20 @@ #ifndef __ASM_ARM_SMCCC_H__ #define __ASM_ARM_SMCCC_H__ -#define ARM_SMCCC_VERSION_1_0 0x10000 -#define ARM_SMCCC_VERSION_1_1 0x10001 +#define SMCCC_VERSION_MAJOR_SHIFT 16 +#define SMCCC_VERSION_MINOR_MASK \ + ((1U << SMCCC_VERSION_MAJOR_SHIFT) - 1) +#define SMCCC_VERSION_MAJOR_MASK ~SMCCC_VERSION_MINOR_MASK +#define SMCCC_VERSION_MAJOR(ver) \ + (((ver) & SMCCC_VERSION_MAJOR_MASK) >> SMCCC_VERSION_MAJOR_SHIFT) +#define SMCCC_VERSION_MINOR(ver) \ + ((ver) & SMCCC_VERSION_MINOR_MASK) + +#define SMCCC_VERSION(major, minor) \ + (((major) << SMCCC_VERSION_MAJOR_SHIFT) | (minor)) + +#define ARM_SMCCC_VERSION_1_0 SMCCC_VERSION(1, 0) +#define ARM_SMCCC_VERSION_1_1 SMCCC_VERSION(1, 1) /* * This file provides common defines for ARM SMC Calling Convention as From patchwork Fri Feb 23 18:57:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129495 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp985085edc; Fri, 23 Feb 2018 11:00:12 -0800 (PST) X-Google-Smtp-Source: AH8x225btWFj1fhDYEiDy3zf/6p8LLhjh7//+a+dmLlsrRCgzmCPESTh/Dg1hi4u5rKo29vkb/s+ X-Received: by 10.36.73.18 with SMTP id z18mr3610210ita.132.1519412412196; Fri, 23 Feb 2018 11:00:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519412412; cv=none; d=google.com; s=arc-20160816; b=PAyxeIAtXM9Hz8NWvH/FykKzdmoLCsjbqTVg3uyONL2etCSB+qW3iU/CBOH6Pp8BYV hPykTuowhVxKiVEvAmH75b0Q2gI32iwMe1dVJ8Mjrs1gekD6QqnuZ4ajkwaM+qVI/UNd 9a3bbbLKrm4dlpx6d3eO6ap6RW9lWTc5ap1a+GpBeYEj6IVEhype4qdkjq0tXRF9Oqvu EDTxN5AM5NnbuGBG9lgMSeHXTKq3Gb/KusfQbWGeMIL2Csms+rzDYeCBTbSiTbbit8Q2 3W4+agDbsFg9kcdyxs310V+SC1Hfv9jMH8Aq9lbVAQVQhIF+V5O1q0r/xdkOgRvzweZO r/sw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=WGbMsGuqZDtZmGK0UfDctps0gL2rcTPHPjWrum80ep8=; b=w9gaRT12fPkJu2PbBBC+UB/SPwIFa1tPTeq4dKm5UbI0iFbLjo4vNZ9mRvpulEliv6 bxmMp6bRB/giy6GPMZZytW9SpTSDeZHt0JgoBAQP9MGvzkUHX4OMxql/9UZ9VLgrQmga LOjgU/9sbFQtNzibJeT9V543Shzm9lhPQcWrl2m8KAh7QKt8oPgNIHUJGOt8LKVSZ34H etIcjTiAeSSVhiE9MEgwWPoOwFcSeA5pBvCPi+kmjIGBl2Ow3XOISSxcBf6H5SPujqwf RXfmsCzSMe47E9YHYbmUSBMSuJwk/k0ZFOUpIsPaAYTVOsJURcSe3537YWv02O84DAwz XiFA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id e2si1614636itc.63.2018.02.23.11.00.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 11:00:12 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXd-00032g-BF; Fri, 23 Feb 2018 18:57:57 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXc-0002vn-7l for xen-devel@lists.xen.org; Fri, 23 Feb 2018 18:57:56 +0000 X-Inumbo-ID: af1f3516-18cb-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id af1f3516-18cb-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 18:59:33 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9729D80D; Fri, 23 Feb 2018 10:57:49 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 642043F25C; Fri, 23 Feb 2018 10:57:48 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 18:57:20 +0000 Message-Id: <20180223185729.8780-10-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223185729.8780-1-julien.grall@arm.com> References: <20180223185729.8780-1-julien.grall@arm.com> Cc: Andre Przywara , Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v5 09/18] xen/arm: psci: Detect SMCCC version X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" PSCI 1.0 and later allows the SMCCC version to be (indirectly) probed via PSCI_FEATURES. If the PSCI_FEATURES does not exist (PSCI 0.2 or earlier) and the function returns an error, then we assume SMCCC 1.0 is implemented. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini Reviewed-by: Andre Przywara --- Changes in v4: - Add Stefano's reviewed-by - Add Andre's reviewed-by - Fix typoes Changes in v2: - Patch added --- xen/arch/arm/psci.c | 34 +++++++++++++++++++++++++++++++++- xen/include/asm-arm/smccc.h | 2 ++ 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c index 5dda35cd7c..909d1c176f 100644 --- a/xen/arch/arm/psci.c +++ b/xen/arch/arm/psci.c @@ -37,6 +37,7 @@ #endif uint32_t psci_ver; +uint32_t smccc_ver; static uint32_t psci_cpu_on_nr; @@ -57,6 +58,14 @@ void call_psci_system_reset(void) call_smc(PSCI_0_2_FN32_SYSTEM_RESET, 0, 0, 0); } +static int __init psci_features(uint32_t psci_func_id) +{ + if ( psci_ver < PSCI_VERSION(1, 0) ) + return PSCI_NOT_SUPPORTED; + + return call_smc(PSCI_1_0_FN32_PSCI_FEATURES, psci_func_id, 0, 0); +} + int __init psci_is_smc_method(const struct dt_device_node *psci) { int ret; @@ -82,6 +91,24 @@ int __init psci_is_smc_method(const struct dt_device_node *psci) return 0; } +static void __init psci_init_smccc(void) +{ + /* PSCI is using at least SMCCC 1.0 calling convention. */ + smccc_ver = ARM_SMCCC_VERSION_1_0; + + if ( psci_features(ARM_SMCCC_VERSION_FID) != PSCI_NOT_SUPPORTED ) + { + uint32_t ret; + + ret = call_smc(ARM_SMCCC_VERSION_FID, 0, 0, 0); + if ( ret != ARM_SMCCC_NOT_SUPPORTED ) + smccc_ver = ret; + } + + printk(XENLOG_INFO "Using SMC Calling Convention v%u.%u\n", + SMCCC_VERSION_MAJOR(smccc_ver), SMCCC_VERSION_MINOR(smccc_ver)); +} + int __init psci_init_0_1(void) { int ret; @@ -173,7 +200,12 @@ int __init psci_init(void) if ( ret ) ret = psci_init_0_1(); - return ret; + if ( ret ) + return ret; + + psci_init_smccc(); + + return 0; } /* diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index d0240d64bf..bc067892c7 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -52,6 +52,8 @@ #ifndef __ASSEMBLY__ +extern uint32_t smccc_ver; + /* Check if this is fast call. */ static inline bool smccc_is_fast_call(register_t funcid) { From patchwork Fri Feb 23 18:57:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129494 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp984873edc; Fri, 23 Feb 2018 11:00:02 -0800 (PST) X-Google-Smtp-Source: AG47ELuc6Ajh7R31nRaZEnpPKB85nI54OAmYKdPVd4HHB6TyxeGgA4dkkDYWYubK6xqH+Qhf8HDb X-Received: by 10.107.50.17 with SMTP id y17mr2745945ioy.223.1519412402673; Fri, 23 Feb 2018 11:00:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519412402; cv=none; d=google.com; s=arc-20160816; b=FE3QzlRNvAd9k6unwFT8TWd4kHcaozkVV0cuGXVKgi7H13dpR8q0JeBxWsoXRW6vmT q/Mq3N+oq6pfvrBiclFwdBLpp4UUn3iVWTQYWaq+axAMcT7ii1xZohjvy/n6cV7fvMiG F3VKq5q9BLjoSuAHfkEO60vxvDtoS60Ux1gUm//rPRIdjgwXlGq2oahtWzZrF6enU+Tj EOsldtq4Mg+afhg4+Z7rBc42lGvtW8ocboHDmdeVMEy1HoC2V2UxsdaMnrB/3gTXmL+M KkHNc47h/WLa+6zx/BobOMSaW6PH3wweh46Lz/iq89Deh4nJtFpE44lIWHYHPGi5VEb/ RdNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=5sxnmRq8/GThNSl5hzSCzAKQsjskVPttkG4L6+SCYu8=; b=ZZfqtbO11zZPSlz3/BQi6MWZQpiohGRvvcEYyA0DYcy6Y99+fXe2UFtigp2TrDgJrg 3/eu1zqpF5+pEBXINg03+xl2tQ+ZMgv6g8E7fX1QJlBctzefXbee3mPOJ7W/wHwVXofv yofxz5IJmAyfQnL6fAYIk+l0Gc4JRSfcA68MYJDRVS5gVeXzgkug+jNvcmk8n1EDahpc DSLV271uOS6G/x0TDDYUEzqbPShqb/HF0kwpub3/ZZ1blj8Iq29mJ9C7zX/MJBnUKZMz MOG1Lq/ObSIio5vn8l/gxCm1bQfjALXiLRdQwoWJ+8+di0Kmvdij/rC+W7xpz8BVklTk 4u2g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id x4si1620853iti.124.2018.02.23.11.00.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 11:00:02 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXe-00035E-MQ; Fri, 23 Feb 2018 18:57:58 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXd-0002wn-7i for xen-devel@lists.xen.org; Fri, 23 Feb 2018 18:57:57 +0000 X-Inumbo-ID: afe9c2f9-18cb-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id afe9c2f9-18cb-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 18:59:34 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E50E915AD; Fri, 23 Feb 2018 10:57:50 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D60B53F25C; Fri, 23 Feb 2018 10:57:49 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 18:57:21 +0000 Message-Id: <20180223185729.8780-11-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223185729.8780-1-julien.grall@arm.com> References: <20180223185729.8780-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v5 10/18] xen/arm: smccc: Implement SMCCC v1.1 inline primitive X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" One of the major improvement of SMCCC v1.1 is that it only clobbers the first 4 registers, both on 32 and 64bit. This means that it becomes very easy to provide an inline version of the SMC call primitive, and avoid performing a function call to stash the registers that woudl otherwise be clobbered by SMCCC v1.0. This patch has been adapted to Xen from Linux commit f2d3b2e8759a. The changes mades are: - Using Xen coding style - Remove HVC as not used by Xen - Add arm_smccc_res structure Reviewed-by: Robin Murphy Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Julien Grall Acked-by: Stefano Stabellini --- Note that the patch is in arm64/for-next/core and should be merged in master soon. Changes in v4: - Add Stefano's acked-by Changes in v2: - Patch added --- xen/include/asm-arm/smccc.h | 119 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index bc067892c7..154772b728 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -78,6 +78,125 @@ static inline uint32_t smccc_get_owner(register_t funcid) return (funcid >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK; } +/* + * struct arm_smccc_res - Result from SMC call + * @a0 - @a3 result values from registers 0 to 3 + */ +struct arm_smccc_res { + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; +}; + +/* SMCCC v1.1 implementation madness follows */ +#define ___count_args(_0, _1, _2, _3, _4, _5, _6, _7, _8, x, ...) x + +#define __count_args(...) \ + ___count_args(__VA_ARGS__, 7, 6, 5, 4, 3, 2, 1, 0) + +#define __constraint_write_0 \ + "+r" (r0), "=&r" (r1), "=&r" (r2), "=&r" (r3) +#define __constraint_write_1 \ + "+r" (r0), "+r" (r1), "=&r" (r2), "=&r" (r3) +#define __constraint_write_2 \ + "+r" (r0), "+r" (r1), "+r" (r2), "=&r" (r3) +#define __constraint_write_3 \ + "+r" (r0), "+r" (r1), "+r" (r2), "+r" (r3) +#define __constraint_write_4 __constraint_write_3 +#define __constraint_write_5 __constraint_write_4 +#define __constraint_write_6 __constraint_write_5 +#define __constraint_write_7 __constraint_write_6 + +#define __constraint_read_0 +#define __constraint_read_1 +#define __constraint_read_2 +#define __constraint_read_3 +#define __constraint_read_4 "r" (r4) +#define __constraint_read_5 __constraint_read_4, "r" (r5) +#define __constraint_read_6 __constraint_read_5, "r" (r6) +#define __constraint_read_7 __constraint_read_6, "r" (r7) + +#define __declare_arg_0(a0, res) \ + struct arm_smccc_res *___res = res; \ + register uin32_t r0 asm("r0") = a0; \ + register unsigned long r1 asm("r1"); \ + register unsigned long r2 asm("r2"); \ + register unsigned long r3 asm("r3") + +#define __declare_arg_1(a0, a1, res) \ + struct arm_smccc_res *___res = res; \ + register uint32_t r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register unsigned long r2 asm("r2"); \ + register unsigned long r3 asm("r3") + +#define __declare_arg_2(a0, a1, a2, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register typeof(a2) r2 asm("r2") = a2; \ + register unsigned long r3 asm("r3") + +#define __declare_arg_3(a0, a1, a2, a3, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register typeof(a2) r2 asm("r2") = a2; \ + register typeof(a3) r3 asm("r3") = a3 + +#define __declare_arg_4(a0, a1, a2, a3, a4, res) \ + __declare_arg_3(a0, a1, a2, a3, res); \ + register typeof(a4) r4 asm("r4") = a4 + +#define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \ + __declare_arg_4(a0, a1, a2, a3, a4, res); \ + register typeof(a5) r5 asm("r5") = a5 + +#define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \ + __declare_arg_5(a0, a1, a2, a3, a4, a5, res); \ + register typeof(a6) r6 asm("r6") = a6 + +#define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \ + __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \ + register typeof(a7) r7 asm("r7") = a7 + +#define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) +#define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__) + +#define ___constraints(count) \ + : __constraint_write_ ## count \ + : __constraint_read_ ## count \ + : "memory" +#define __constraints(count) ___constraints(count) + +/* + * arm_smccc_1_1_smc() - make an SMCCC v1.1 compliant SMC call + * + * This is a variadic macro taking one to eight source arguments, and + * an optional return structure. + * + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * + * This macro is used to make SMC calls following SMC Calling Convention v1.1. + * The content of the supplied param are copied to registers 0 to 7 prior + * to the SMC instruction. The return values are updated with the content + * from register 0 to 3 on return from the SMC instruction if not NULL. + * + * We have an output list that is not necessarily used, and GCC feels + * entitled to optimise the whole sequence away. "volatile" is what + * makes it stick. + */ +#define arm_smccc_1_1_smc(...) \ + do { \ + __declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \ + asm volatile("smc #0\n" \ + __constraints(__count_args(__VA_ARGS__))); \ + if ( ___res ) \ + *___res = (typeof(*___res)){r0, r1, r2, r3}; \ + } while ( 0 ) + #endif /* From patchwork Fri Feb 23 18:57:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129487 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp984769edc; Fri, 23 Feb 2018 10:59:55 -0800 (PST) X-Google-Smtp-Source: AH8x226qzsefTh4+QLv10/D1wmEBtXN7iP66n53S1ACwIcOofB7L24AUGebdC13KrRVm8PTpADyG X-Received: by 10.36.98.21 with SMTP id d21mr3671157itc.1.1519412395523; Fri, 23 Feb 2018 10:59:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519412395; cv=none; d=google.com; s=arc-20160816; b=QBj9/hhK8o0jizTfj21kYFAn2r8QGrKfIPo5SaiJ67TLCCupQNKow4EVMyAJNK9zFk WAslbV7rdADqgRsi6rs4apk9YzbMi0Jn2Akocq6jZL0ujoJsRQ034kKyFMmlwAuMmV1X nIi+nDvsoSqPrWzPglORdi0PGK345mLVUbNKyIkYmNZEPi8ziGgUBE8EHAv0j1k5qGWj yPYdKiG/twVcjUusmVIQiM33yDd+eZziVSlxYmhFHHk6EqkMYL6rE18WQhz7jVD8M66Q scy9zQ0IEwXrhYG6UjkopwFHcxr5JzfjuX7AkgXRAZh6JVAKGIHQk1KBY48XxVIADR+D nO7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=kHIGbvUqqQfQdT5YVdBMW1BNLshPRpKP4hpZs111u6g=; b=yX1ImcVjSIlHm26tC6HL82a6EY/SRoHUYk4cKTSqohjRgj2XvPhApsGoTSZFl1P/Po AYfyO4dB3+bTA7FDgYetVAxa2eljeq4vZNHggrT6xnpe1Ri05cCp8FWIXe+j2kh662vR j+F/IQJI8/DFadJioA1MmoVBMDWmxxQXLiaDzd9V10LWifB3QZiqj2916M01mSeBFYXn EX4H+Ng3qXIXoB3Vu78V994rKvRVFiHhy6/9sjCol/4UF6fZz+EYoLEn6qeIdaXbmy8g k/Vv87cSH9cI2YzzDTo1444/NmhufplCkY/vY3NtdbOAKcX0oBppS0X7OrHPVm9HOS/Q SisQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id o66si1624116ith.86.2018.02.23.10.59.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 10:59:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXZ-0002xs-MI; Fri, 23 Feb 2018 18:57:53 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXZ-0002xS-5c for xen-devel@lists.xen.org; Fri, 23 Feb 2018 18:57:53 +0000 X-Inumbo-ID: 552997d6-18cb-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 552997d6-18cb-11e8-ba59-bc764e045a96; Fri, 23 Feb 2018 19:57:02 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3EBE780D; Fri, 23 Feb 2018 10:57:52 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2FB2B3F25C; Fri, 23 Feb 2018 10:57:51 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 18:57:22 +0000 Message-Id: <20180223185729.8780-12-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223185729.8780-1-julien.grall@arm.com> References: <20180223185729.8780-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v5 11/18] xen/arm64: Add ARM_SMCCC_ARCH_WORKAROUND_1 BP hardening support X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Add the detection and runtime code for ARM_SMCCC_ARCH_WORKAROUND_1. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Reviewed-by: Stefano Stabellini Reviewed-by: Andre Przywara --- Changes in v5: - Fold the fixup! patch which re-order registers into it. Changes in v4: - Re-order saving/restoring registers in __smccc_workaround_1_smc_start Changes in v3: - Add the missing call to smc #0. Changes in v2: - Patch added --- xen/arch/arm/arm64/bpi.S | 13 +++++++++++++ xen/arch/arm/cpuerrata.c | 32 +++++++++++++++++++++++++++++++- xen/include/asm-arm/smccc.h | 1 + 3 files changed, 45 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/arm64/bpi.S b/xen/arch/arm/arm64/bpi.S index 4b7f1dc21f..b59e307b0f 100644 --- a/xen/arch/arm/arm64/bpi.S +++ b/xen/arch/arm/arm64/bpi.S @@ -16,6 +16,8 @@ * along with this program. If not, see . */ +#include + .macro ventry target .rept 31 nop @@ -81,6 +83,17 @@ ENTRY(__psci_hyp_bp_inval_start) add sp, sp, #(8 * 18) ENTRY(__psci_hyp_bp_inval_end) +ENTRY(__smccc_workaround_1_smc_start) + sub sp, sp, #(8 * 4) + stp x0, x1, [sp, #(8 * 2)] + stp x2, x3, [sp, #(8 * 0)] + mov w0, #ARM_SMCCC_ARCH_WORKAROUND_1_FID + smc #0 + ldp x2, x3, [sp, #(8 * 0)] + ldp x0, x1, [sp, #(8 * 2)] + add sp, sp, #(8 * 4) +ENTRY(__smccc_workaround_1_smc_end) + /* * Local variables: * mode: ASM diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index 8d5f8d372a..dec9074422 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -147,6 +147,34 @@ install_bp_hardening_vec(const struct arm_cpu_capabilities *entry, return ret; } +extern char __smccc_workaround_1_smc_start[], __smccc_workaround_1_smc_end[]; + +static bool +check_smccc_arch_workaround_1(const struct arm_cpu_capabilities *entry) +{ + struct arm_smccc_res res; + + /* + * Enable callbacks are called on every CPU based on the + * capabilities. So double-check whether the CPU matches the + * entry. + */ + if ( !entry->matches(entry) ) + return false; + + if ( smccc_ver < SMCCC_VERSION(1, 1) ) + return false; + + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FID, + ARM_SMCCC_ARCH_WORKAROUND_1_FID, &res); + if ( res.a0 != ARM_SMCCC_SUCCESS ) + return false; + + return install_bp_hardening_vec(entry,__smccc_workaround_1_smc_start, + __smccc_workaround_1_smc_end, + "call ARM_SMCCC_ARCH_WORKAROUND_1"); +} + extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[]; static int enable_psci_bp_hardening(void *data) @@ -154,12 +182,14 @@ static int enable_psci_bp_hardening(void *data) bool ret = true; static bool warned = false; + if ( check_smccc_arch_workaround_1(data) ) + return 0; /* * The mitigation is using PSCI version function to invalidate the * branch predictor. This function is only available with PSCI 0.2 * and later. */ - if ( psci_ver >= PSCI_VERSION(0, 2) ) + else if ( psci_ver >= PSCI_VERSION(0, 2) ) ret = install_bp_hardening_vec(data, __psci_hyp_bp_inval_start, __psci_hyp_bp_inval_end, "call PSCI get version"); diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 154772b728..8342cc33fe 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -261,6 +261,7 @@ struct arm_smccc_res { /* SMCCC error codes */ #define ARM_SMCCC_ERR_UNKNOWN_FUNCTION (-1) #define ARM_SMCCC_NOT_SUPPORTED (-1) +#define ARM_SMCCC_SUCCESS (0) /* SMCCC function identifier range which is reserved for existing APIs */ #define ARM_SMCCC_RESERVED_RANGE_START 0x0 From patchwork Fri Feb 23 18:57:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129492 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp984848edc; Fri, 23 Feb 2018 11:00:00 -0800 (PST) X-Google-Smtp-Source: AG47ELvi+Qloqwlod2Z8lzChEiGsDol6FzVO12AP1birLiFTb/KZc1gdcRoczDWS8ypTonyRrGIl X-Received: by 10.36.53.146 with SMTP id k140mr3400469ita.17.1519412400836; Fri, 23 Feb 2018 11:00:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519412400; cv=none; d=google.com; s=arc-20160816; b=rHa/46Hc5kyFrvhrwj5SjNpa2scHIBaF+yVHotfVYt8U9xo6hN7ObzpvIUhnOt2CCN KYimeDLAwUuRgJidcecqLEWJC/f7c2aggYN+aSO3hO6NvORjKSWi1/5LmdSWUa8RrS8A xJTvN0iwFSlp5XmqKOW1OttHgUtgxlOy9RkTAZd7beyyo98RThZfzfVRs4FD1fIRTjLk cj6N71edaZgn+wJqvLbSix7HKISHHUKjPA7k23PSB+KkbF2wWcFRQnio2fpjs1yWZ9NF wVbh7hOtiyMIRjgZs1IkGkxeA1czQ7KCAcxOIgyA1II0fH3Y7X1gG9UYoqUxf2vSgOs0 fH0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=niodD7ufXW+Ybz4/blTZLtdngzg608mz5Zb43DUSgOE=; b=frnsnIw4bKbaaL07N+cLuEvGTuPicu+8IUVikjfUxnxO2DJr7VBJpn4zNNkNPE/jh0 Hfx97zSXshH79QYXweug+RmKVVmfzZCMlADxZnTZO1sPmYbCLVHiowGrDsp3ppd5O+EJ bVajpmH76H343xj4zvKyZFK+aYCNWnxISQ9hGpZpem2TdQ70psSaCeIMzjBNyG7UCVME +YFqDzxvxXFT7e4rePIywZ2OgkzjYCfjtRBMEEgoiL+pzg7M8k5nofTZblWbDG9ZC17I Q7qF6B7Zv25YMu+mBpZffjXn6HxTvNNn5bJPfDKdtSZL83Vnen8d/sFLzVpWo4hWR91I WuDw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id h65si1960872ioh.54.2018.02.23.11.00.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 11:00:00 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXb-000307-44; Fri, 23 Feb 2018 18:57:55 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXa-0002z4-Gg for xen-devel@lists.xen.org; Fri, 23 Feb 2018 18:57:54 +0000 X-Inumbo-ID: 55ed03a7-18cb-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 55ed03a7-18cb-11e8-ba59-bc764e045a96; Fri, 23 Feb 2018 19:57:03 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8CD5C15BE; Fri, 23 Feb 2018 10:57:53 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7DC963F25C; Fri, 23 Feb 2018 10:57:52 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 18:57:23 +0000 Message-Id: <20180223185729.8780-13-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223185729.8780-1-julien.grall@arm.com> References: <20180223185729.8780-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v5 12/18] xen/arm64: Kill PSCI_GET_VERSION as a variant-2 workaround X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Now that we've standardised on SMCCC v1.1 to perform the branch prediction invalidation, let's drop the previous band-aid. If vendors haven't updated their firmware to do SMCCC 1.1, they haven't updated PSCI either, so we don't loose anything. This is aligned with the Linux commit 3a0a397ff5ff. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Reviewed-by: Stefano Stabellini --- Note that the patch is in arm64/for-next/core and should be merged in master soon. Changes in v4: - Add Stefano's reviewed-by Changes in v3: - Add Volodymyr's reviewed-by Changes in v2: - Patch added --- xen/arch/arm/arm64/bpi.S | 25 ---------------------- xen/arch/arm/cpuerrata.c | 54 +++++++++++++++++------------------------------- 2 files changed, 19 insertions(+), 60 deletions(-) diff --git a/xen/arch/arm/arm64/bpi.S b/xen/arch/arm/arm64/bpi.S index b59e307b0f..d8743d955c 100644 --- a/xen/arch/arm/arm64/bpi.S +++ b/xen/arch/arm/arm64/bpi.S @@ -58,31 +58,6 @@ ENTRY(__bp_harden_hyp_vecs_start) .endr ENTRY(__bp_harden_hyp_vecs_end) -ENTRY(__psci_hyp_bp_inval_start) - sub sp, sp, #(8 * 18) - stp x16, x17, [sp, #(16 * 0)] - stp x14, x15, [sp, #(16 * 1)] - stp x12, x13, [sp, #(16 * 2)] - stp x10, x11, [sp, #(16 * 3)] - stp x8, x9, [sp, #(16 * 4)] - stp x6, x7, [sp, #(16 * 5)] - stp x4, x5, [sp, #(16 * 6)] - stp x2, x3, [sp, #(16 * 7)] - stp x0, x1, [sp, #(16 * 8)] - mov x0, #0x84000000 - smc #0 - ldp x16, x17, [sp, #(16 * 0)] - ldp x14, x15, [sp, #(16 * 1)] - ldp x12, x13, [sp, #(16 * 2)] - ldp x10, x11, [sp, #(16 * 3)] - ldp x8, x9, [sp, #(16 * 4)] - ldp x6, x7, [sp, #(16 * 5)] - ldp x4, x5, [sp, #(16 * 6)] - ldp x2, x3, [sp, #(16 * 7)] - ldp x0, x1, [sp, #(16 * 8)] - add sp, sp, #(8 * 18) -ENTRY(__psci_hyp_bp_inval_end) - ENTRY(__smccc_workaround_1_smc_start) sub sp, sp, #(8 * 4) stp x0, x1, [sp, #(8 * 2)] diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index dec9074422..4eb1567589 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -149,10 +149,11 @@ install_bp_hardening_vec(const struct arm_cpu_capabilities *entry, extern char __smccc_workaround_1_smc_start[], __smccc_workaround_1_smc_end[]; -static bool -check_smccc_arch_workaround_1(const struct arm_cpu_capabilities *entry) +static int enable_smccc_arch_workaround_1(void *data) { struct arm_smccc_res res; + static bool warned = false; + const struct arm_cpu_capabilities *entry = data; /* * Enable callbacks are called on every CPU based on the @@ -160,47 +161,30 @@ check_smccc_arch_workaround_1(const struct arm_cpu_capabilities *entry) * entry. */ if ( !entry->matches(entry) ) - return false; + return 0; if ( smccc_ver < SMCCC_VERSION(1, 1) ) - return false; + goto warn; arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FID, ARM_SMCCC_ARCH_WORKAROUND_1_FID, &res); if ( res.a0 != ARM_SMCCC_SUCCESS ) - return false; - - return install_bp_hardening_vec(entry,__smccc_workaround_1_smc_start, - __smccc_workaround_1_smc_end, - "call ARM_SMCCC_ARCH_WORKAROUND_1"); -} + goto warn; -extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[]; + return !install_bp_hardening_vec(entry,__smccc_workaround_1_smc_start, + __smccc_workaround_1_smc_end, + "call ARM_SMCCC_ARCH_WORKAROUND_1"); -static int enable_psci_bp_hardening(void *data) -{ - bool ret = true; - static bool warned = false; - - if ( check_smccc_arch_workaround_1(data) ) - return 0; - /* - * The mitigation is using PSCI version function to invalidate the - * branch predictor. This function is only available with PSCI 0.2 - * and later. - */ - else if ( psci_ver >= PSCI_VERSION(0, 2) ) - ret = install_bp_hardening_vec(data, __psci_hyp_bp_inval_start, - __psci_hyp_bp_inval_end, - "call PSCI get version"); - else if ( !warned ) +warn: + if ( !warned ) { ASSERT(system_state < SYS_STATE_active); - warning_add("PSCI 0.2 or later is required for the branch predictor hardening.\n"); - warned = true; + warning_add("No support for ARM_SMCCC_ARCH_WORKAROUND_1.\n" + "Please update your firmware.\n"); + warned = false; } - return !ret; + return 0; } #endif /* CONFIG_ARM64_HARDEN_BRANCH_PREDICTOR */ @@ -316,22 +300,22 @@ static const struct arm_cpu_capabilities arm_errata[] = { { .capability = ARM_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, #endif #ifdef CONFIG_ARM32_HARDEN_BRANCH_PREDICTOR From patchwork Fri Feb 23 18:57:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129485 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp984756edc; Fri, 23 Feb 2018 10:59:54 -0800 (PST) X-Google-Smtp-Source: AG47ELuyykZ7wMo8PDeqFv7eiIgPfWCXKq9AxOeZvoZhq5CJm/obPMewMjh0Qms3xgvVRkxG0Alx X-Received: by 10.36.64.140 with SMTP id n134mr370032ita.84.1519412394538; Fri, 23 Feb 2018 10:59:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519412394; cv=none; d=google.com; s=arc-20160816; b=K4irF19qOKSu+hul+yLn8d0IzXNpAqrXLfAaB+lpw1oaUAf1QIEgL6ugPQCOQ0uMfE 0k87jWXGVdu9atVK8AFfnemx053Dye3CgZpq9CyZxweS4TRRoFcS1FwmEtpAr4KCvB6e fNo9hagwIvxNTgqz4S9F1+ytUDp4g33Ap2JVbUIA7j8z3ysbD99+S1hyA6wOUCZPQCM2 Rup41xG3tWAgzAP1zcwNSfRXXp9SQcTcjO0sjPTsqUM4guI0014uAT+4+qnXI0Fc1bDZ vIXf/Jt7V75tRYS+OCbCegeN9sPxwgHmXdx6sVmRYk53NLhN5Y7x2WyP1jKc0QZyHYRF mjSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=dYH1kiPlSLD32lQlMWqHofYy0VCarCPdqgxw0DwyyA0=; b=XSggX8kxFUVp2SoowW7Il7Y0uaW7jicic9gnSOUnpQirlTEN+Px6pjTerxUnpzJZDY JoR3R3TYigmC5vRbsScIdHpngtUqU6bpAa0d9KkGkN+YXSv9pHaypLrbp0XzIMNhxos9 2X9A6VMvAbnScIpincPt4PZ4hSzfNENm0QSpaF9x/Y/0BXErc0Q9My5uVOkCA8W3Eq67 NMv8+nIY59hYkdSdPGX/goefvDi2eSBS0hWuVmtPlR816N9qA5/oAgCA1j8hNnZ2hyc/ 9zXnVYAySRey1e4ALQhPMVF/xo1oZ6mhdYAVM5XoVDTjDwF03ARPP7tJgJRhNwxMyNaz DqfA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 3si1063844itj.126.2018.02.23.10.59.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 10:59:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXi-0003B4-4G; Fri, 23 Feb 2018 18:58:02 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXh-00031k-Cl for xen-devel@lists.xen.org; Fri, 23 Feb 2018 18:58:01 +0000 X-Inumbo-ID: b277161d-18cb-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id b277161d-18cb-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 18:59:38 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2E32180D; Fri, 23 Feb 2018 10:57:55 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CC28A3F25C; Fri, 23 Feb 2018 10:57:53 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 18:57:24 +0000 Message-Id: <20180223185729.8780-14-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223185729.8780-1-julien.grall@arm.com> References: <20180223185729.8780-1-julien.grall@arm.com> Cc: sstabellini@kernel.org, Andre Przywara , andre.przywara@linaro.org, Volodymyr Babchuk , Julien Grall , volodymyr_babchuk@epam.com Subject: [Xen-devel] [PATCH v5 13/18] xen/arm: vpsci: Remove parameter 'ver' from do_common_cpu X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Currently, the behavior of do_common_cpu will slightly change depending on the PSCI version passed in parameter. Looking at the code, more the specific 0.2 behavior could move out of the function or adapted for 0.1: - x0/r0 can be updated on PSCI 0.1 because general purpose registers are undefined upon CPU on. This was deduced from the spec not mentioning the state of general purpose registers on CPU on. - PSCI 0.1 does not defined PSCI_ALREADY_ON. However, it would be safer to bail out if the CPU is already on. Based on this, the parameter 'ver' is removed and do_psci_cpu_on (implementation for PSCI 0.1) is adapted to avoid returning PSCI_ALREADY_ON. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini Reviewed-by: Andre Przywara --- The reviewed-by was kept despite move this patch towards the end of the series because there was no clash with the rest of the series. Changes in v4: - Slightly update the comment to mention the spec - Add Stefano's acked-by - Add Andre's reviewed-by Changes in v2: - Move the patch towards the end of the series as not strictly necessary for SP2. - Add Volodymyr's reviewed-by --- xen/arch/arm/vpsci.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 19ee7caeb4..7ea3ea58e3 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -22,7 +22,7 @@ #include static int do_common_cpu_on(register_t target_cpu, register_t entry_point, - register_t context_id,int ver) + register_t context_id) { struct vcpu *v; struct domain *d = current->domain; @@ -40,8 +40,7 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, if ( is_64bit_domain(d) && is_thumb ) return PSCI_INVALID_PARAMETERS; - if ( (ver == PSCI_VERSION(0, 2)) && - !test_bit(_VPF_down, &v->pause_flags) ) + if ( !test_bit(_VPF_down, &v->pause_flags) ) return PSCI_ALREADY_ON; if ( (ctxt = alloc_vcpu_guest_context()) == NULL ) @@ -55,18 +54,21 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, ctxt->ttbr0 = 0; ctxt->ttbr1 = 0; ctxt->ttbcr = 0; /* Defined Reset Value */ + + /* + * x0/r0_usr are always updated because for PSCI 0.1 the general + * purpose registers are undefined upon CPU_on. + */ if ( is_32bit_domain(d) ) { ctxt->user_regs.cpsr = PSR_GUEST32_INIT; - if ( ver == PSCI_VERSION(0, 2) ) - ctxt->user_regs.r0_usr = context_id; + ctxt->user_regs.r0_usr = context_id; } #ifdef CONFIG_ARM_64 else { ctxt->user_regs.cpsr = PSR_GUEST64_INIT; - if ( ver == PSCI_VERSION(0, 2) ) - ctxt->user_regs.x0 = context_id; + ctxt->user_regs.x0 = context_id; } #endif @@ -93,7 +95,14 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, static int32_t do_psci_cpu_on(uint32_t vcpuid, register_t entry_point) { - return do_common_cpu_on(vcpuid, entry_point, 0 , PSCI_VERSION(0, 1)); + int32_t ret; + + ret = do_common_cpu_on(vcpuid, entry_point, 0); + /* + * PSCI 0.1 does not define the return code PSCI_ALREADY_ON. + * Instead, return PSCI_INVALID_PARAMETERS. + */ + return (ret == PSCI_ALREADY_ON) ? PSCI_INVALID_PARAMETERS : ret; } static int32_t do_psci_cpu_off(uint32_t power_state) @@ -137,8 +146,7 @@ static int32_t do_psci_0_2_cpu_on(register_t target_cpu, register_t entry_point, register_t context_id) { - return do_common_cpu_on(target_cpu, entry_point, context_id, - PSCI_VERSION(0, 2)); + return do_common_cpu_on(target_cpu, entry_point, context_id); } static const unsigned long target_affinity_mask[] = { From patchwork Fri Feb 23 18:57:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129491 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp984816edc; Fri, 23 Feb 2018 10:59:58 -0800 (PST) X-Google-Smtp-Source: AG47ELvzWZ8V1eIZkA68HH4bbnaxNXVRK0nt6w4A7ozVXl4Ods4HLl0ZovY1Qfr3iud8kgvJ5tGg X-Received: by 10.107.16.210 with SMTP id 79mr3064465ioq.290.1519412398539; Fri, 23 Feb 2018 10:59:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519412398; cv=none; d=google.com; s=arc-20160816; b=D65/AlTl8RTF7WfmEvUZKT6nXvuwdt+0IILXP8K2KWvWKya9Kq8V0TFzlhVsBKMQMW wYHHGAO+U1Ar+59fOB4PxnLw48OJb4UVcAV6kXAh3GyBnFdBPu/I7GCHB1y0u3l4c6oz pc6TIoOZWbOGQWYPzMD0pClI1sVzHO2AneIOJ72VyTgqcMBKZdxsJeAbPsGD+gxhPAN8 gRGsWFAfXBYAeUMm2IhMj5peijI89L/PFs+bzARPDraIzjW5k1XuaKbyDDNAYBcOJr7Z xv67hvYX0Q1wiRsLXxhy3jAel6w+b0H2HKdgKotcJIfbg898apsSaPINcbFQndZ1r6Gs 0ghw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=vEVHcj/oKj8VbuLNbfFv5dyowfno4E85f/7gWlSdo0w=; b=w1IypcsU+UcUamwoixxZirs3b681XsQq9U5zgKIurE9c5wxZSVoS02pT0Zz2YKusqB qpe1Dq++yhp945xVkH2QkWD6CHs812pekkyrpEh6oJgs3veYOnxUrOX02Mn1BmqTQdrI CDwuQUdBDMcKxLPCTNLegsXDquxA/0o3sza7oVK4LIAnhs8lox8V+v6heYd5x5tzRL6d yJFCxTGOwE3gW0NpxYWdgbwpftayB+UrVOgGPfbDDcyxbwMnm5r56IpKww8yvo0cQGWu oV8dF+0HPbXnyQs0bml9zo4yQYT4dXAeeEIvcX2a3EyBARAYeMajc/TfHGZGRD6sBP1T 0lvw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id x25si204841ioi.92.2018.02.23.10.59.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 10:59:58 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXe-00035i-T9; Fri, 23 Feb 2018 18:57:58 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXd-000331-JB for xen-devel@lists.xen.org; Fri, 23 Feb 2018 18:57:57 +0000 X-Inumbo-ID: 57ac857b-18cb-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 57ac857b-18cb-11e8-ba59-bc764e045a96; Fri, 23 Feb 2018 19:57:06 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7C7C415AD; Fri, 23 Feb 2018 10:57:56 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6D3423F25C; Fri, 23 Feb 2018 10:57:55 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 18:57:25 +0000 Message-Id: <20180223185729.8780-15-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223185729.8780-1-julien.grall@arm.com> References: <20180223185729.8780-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v5 14/18] xen/arm: psci: Consolidate PSCI version print X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Xen is printing the same way the PSCI version for 0.1, 0.2 and later. The only different is the former is hardcoded. Furthermore PSCI is now used for other things than SMP bring up. So only print the PSCI version in psci_init. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini --- Changes in v4: - Add Stefano's acked-by Changes in v3: - Add Volodymyr's reviewed-by Changes in v2: - Patch added --- xen/arch/arm/psci.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c index 909d1c176f..6e6980bfe2 100644 --- a/xen/arch/arm/psci.c +++ b/xen/arch/arm/psci.c @@ -136,8 +136,6 @@ int __init psci_init_0_1(void) psci_ver = PSCI_VERSION(0, 1); - printk(XENLOG_INFO "Using PSCI-0.1 for SMP bringup\n"); - return 0; } @@ -183,9 +181,6 @@ int __init psci_init_0_2(void) psci_cpu_on_nr = PSCI_0_2_FN_NATIVE(CPU_ON); - printk(XENLOG_INFO "Using PSCI-%u.%u for SMP bringup\n", - PSCI_VERSION_MAJOR(psci_ver), PSCI_VERSION_MINOR(psci_ver)); - return 0; } @@ -205,6 +200,9 @@ int __init psci_init(void) psci_init_smccc(); + printk(XENLOG_INFO "Using PSCI v%u.%u\n", + PSCI_VERSION_MAJOR(psci_ver), PSCI_VERSION_MINOR(psci_ver)); + return 0; } From patchwork Fri Feb 23 18:57:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129479 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp984485edc; Fri, 23 Feb 2018 10:59:35 -0800 (PST) X-Google-Smtp-Source: AG47ELs6czOcWPqgfD5S+FLskqmPZcRvDCA1qrEYtI10qyYlMtUV30VbK3Tr5M8vIG0Rny11QlHt X-Received: by 10.36.46.23 with SMTP id i23mr3599282ita.55.1519412374911; Fri, 23 Feb 2018 10:59:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519412374; cv=none; d=google.com; s=arc-20160816; b=XWDR+og95Qlf0B0dmBpRRXZnSH3RsnwdltcOXfZz2GS6TgHWoaLZwMGZNCCtO0B2Ts zuSiRfVMARtroNfhjwMMKvn49l7qH9d9rdaJW2VXZ4K9tiy9Co0cna5C7pKVFjICAA0D QKu0Olw+9bb/ihwfI3RYTV8EBBUVIO37IwXwaTixV0xImnEIKBqhnYowERiT/QMb3hP0 AuhxVxLg1aAk4tClL0LAkx+9n2n2+qzJQ1L3PGkph0E8rIGxOlZZ5zD1lnPyDcaisPY7 64J853dijtIQXF52iwKo6mm4XpLe0CMq+acTBEjpR10QSt9WfUfpKEqNwmh/F4jEP513 RVtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=ZsbEhlhant75qlby0uTebfG3IW9pTKqfMcrD0lxixYQ=; b=xUHK3ESTtCIR7vSHDHJVre1kXnLCG0uAUknbB3NpKFeh0g9Adup4ktHK+yezNd62qV EwePMonqTfZqtejp9smUg9pYK2bqblFcSuaTcF/NJeSYeeRcjYjvCIiDnrwsYuPYn/bh jahltMrxqjrrPYcwyW776UDyKA2knu6cRf4li3lNc8XHnvc2wRRrU8sAAnRuu89BHoDx cxIGt/g8lHLTZKqWYiJ8vdV41i0nZreTSNCEH2Zp4nwlyLLL5qUsJ1mx36k4d/orM5FA ASN/ZxkZv5VXbHhgAhoc29G7uYvESxbo/a++CSFwHMd6USMttyPx+Cmjctrz7iUfPO9K FxYg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id z190si2012916ioz.133.2018.02.23.10.59.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 10:59:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXl-0003Gw-JN; Fri, 23 Feb 2018 18:58:05 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXk-000376-Da for xen-devel@lists.xen.org; Fri, 23 Feb 2018 18:58:04 +0000 X-Inumbo-ID: b4042ee4-18cb-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id b4042ee4-18cb-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 18:59:41 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CAAF715BE; Fri, 23 Feb 2018 10:57:57 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BB7DA3F25C; Fri, 23 Feb 2018 10:57:56 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 18:57:26 +0000 Message-Id: <20180223185729.8780-16-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223185729.8780-1-julien.grall@arm.com> References: <20180223185729.8780-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v5 15/18] xen/arm: psci: Prefix with static any functions not exported X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" A bunch of PSCI functions are not prefixed with static despite no one is using them outside the file and the prototype is not available in psci.h. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini --- Changes in v4: - Add Stefano's acked-by Changes in v2: - Patch added --- xen/arch/arm/psci.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c index 6e6980bfe2..94b616df9b 100644 --- a/xen/arch/arm/psci.c +++ b/xen/arch/arm/psci.c @@ -66,7 +66,7 @@ static int __init psci_features(uint32_t psci_func_id) return call_smc(PSCI_1_0_FN32_PSCI_FEATURES, psci_func_id, 0, 0); } -int __init psci_is_smc_method(const struct dt_device_node *psci) +static int __init psci_is_smc_method(const struct dt_device_node *psci) { int ret; const char *prop_str; @@ -109,7 +109,7 @@ static void __init psci_init_smccc(void) SMCCC_VERSION_MAJOR(smccc_ver), SMCCC_VERSION_MINOR(smccc_ver)); } -int __init psci_init_0_1(void) +static int __init psci_init_0_1(void) { int ret; const struct dt_device_node *psci; @@ -139,7 +139,7 @@ int __init psci_init_0_1(void) return 0; } -int __init psci_init_0_2(void) +static int __init psci_init_0_2(void) { static const struct dt_device_match psci_ids[] __initconst = { From patchwork Fri Feb 23 18:57:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129478 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp984433edc; Fri, 23 Feb 2018 10:59:31 -0800 (PST) X-Google-Smtp-Source: AG47ELvgbnPFNT/vU/o92Q3uKQadnE30C9umnYwLiV2ko62oQU2343IBSQeV2R0lsk/9Qtx9aC4K X-Received: by 10.107.173.144 with SMTP id m16mr3057910ioo.32.1519412371614; Fri, 23 Feb 2018 10:59:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519412371; cv=none; d=google.com; s=arc-20160816; b=m4O6DRLriW0aDoq4HYl2igIx9eFDFcdtUVccLto11tcB4+wokTWpVkOWa/aKeO3DGQ UP7+U5AgeDHTxRlupjOGBuQAJbgytZvDAEV4e9ujrlinGKGLk9vZQu5EHHiucXvw9Cw2 HiJ8Tf9YpZP69UvC0YPFMVlErrY0S5l51/7+RayccTbMi6ZWtYyGZirGQGJnej0c+1Qo kyH1ihnaFI9WAPDQNk8iMGTU6kGq0o69GZgK5/kz2zQr4iHUTdDh+keZPwG1H8kdgwII WXqEM1xgLLhiZ2GSW1piW1kL5mxHMO6dU50vOj/PO+7bOuUyrdjA4BUQZFbG4jZxpsNf xQ8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=/8cUjQBSqO2GBfXzEn8HJlfpvG8hnKMJYS7fILlA8Dw=; b=NmnZE1YUDjZ/+w14RD/5GcqQHu+M0HsPtuTuzIdYrmto6ywegX5chuVI8Yp+f4AdUW sID7zG27HOyYRUSUT0iHvNXquIAod9rsHOq8h75cD8V0CAgeqLfniMzet/Ra5AubF3Sg e3tYGLEj2OCImZfvIf31Clc5/Rv72c4h8NlqHWvDiTLjrOqoIQKDwqB4BBSuvNJU73gv O+25crpuRHlLPqKzQC8hqjOd2JFjveKg1qHrCEAqUXflt7fdmPsD5/HoMysv3A+khFzL lBM7zzkJjaXY+GtY94Vb5kucQZdgWSxZsWxIfOzYVa9/hAnRo8NCUW93jn4t+m7yiyPF QYbg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id f142si1499866itd.132.2018.02.23.10.59.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 10:59:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXn-0003KT-Qy; Fri, 23 Feb 2018 18:58:07 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXl-00039P-Tt for xen-devel@lists.xen.org; Fri, 23 Feb 2018 18:58:05 +0000 X-Inumbo-ID: b4e41f88-18cb-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id b4e41f88-18cb-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 18:59:42 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4876D15AD; Fri, 23 Feb 2018 10:57:59 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 15A983F25C; Fri, 23 Feb 2018 10:57:57 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 18:57:27 +0000 Message-Id: <20180223185729.8780-17-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223185729.8780-1-julien.grall@arm.com> References: <20180223185729.8780-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, mirela.simonovic@aggios.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v5 16/18] xen/arm: vpsci: Update the return type for MIGRATE_INFO_TYPE X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" >From the specification, the PSCI call MIGRATE_INFO_TYPE will return an int32_t. Update the function return type to match it. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini Cc: mirela.simonovic@aggios.com --- Changes in v4: - Add Stefano's reviewed-by Changes in v3: - Patch added --- xen/arch/arm/vpsci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 7ea3ea58e3..9a082aa6ee 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -186,7 +186,7 @@ static int32_t do_psci_0_2_affinity_info(register_t target_affinity, return PSCI_0_2_AFFINITY_LEVEL_OFF; } -static uint32_t do_psci_0_2_migrate_info_type(void) +static int32_t do_psci_0_2_migrate_info_type(void) { return PSCI_0_2_TOS_MP_OR_NOT_PRESENT; } From patchwork Fri Feb 23 18:57:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129480 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp984493edc; Fri, 23 Feb 2018 10:59:35 -0800 (PST) X-Google-Smtp-Source: AG47ELsdiHf8xyqhbmGP7W1QmzmESYeRIIRG1YytE18L+bujPljoLB7i8JDlafuZZwFHS2YyBKvQ X-Received: by 10.36.67.1 with SMTP id s1mr3715491itb.145.1519412375315; Fri, 23 Feb 2018 10:59:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519412375; cv=none; d=google.com; s=arc-20160816; b=F61zWb8xJXYykgm795AO3tqRmjlOmwpEox6tOHN8iXfQttd03/zfbAQAye79Q8tVUZ 6Gwt/IEVYubwq4BIaSHwvIEdD3qmVppd2B8vjnTgJ8XuE0xXHpYfkX/7JG5DTL7iqt42 hFTmTSAxbdO6Kr1zmFVII7jiMbFPLT/fM93N0gqlugmLs9rMaPcKdU2OlEE78cpf6zvy RODTOAOFhDLtJdEnNc3l6wOGWw7jaCUm3yqTPyGMjpHL9YVkRgbJVGy6auCqpXxrOQVA bCwHuolYAGmZec/xhZmedm5qwMtm1y4OlYUK4LRNYWjvNvQvP4JRGw8MbwsFOATKka78 mcHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=/0rIio5QeCp+glGttn2kDs0K0F87RArvWiZ4b3I3FXU=; b=qhqHsg56NQpAFhCdGQUTXZTa24gl2H32RXQPVMz6wjwmXSgjCOcjPFNYoa2Mb5p8C7 6sujM0xDawkchGGmq3j8jg+1d+t1oH3lwDO9/vVlDBih6Ygmc3NGz7jE2L2saBYQzBhm 7zRAbE3mtv/SACtQaQASBbmMWeulPKBfOuVKpu3KyXj5fE1lq1hG88d4R7iIVYfSZWH/ M/QqWwsDOx5ieIEP+2TQD3STpRx0pr7F+2/k6cS4brhUrmmsQPe8QLgxeRAw9LQwj+Oy u4Od8mlSMRhbaeHV8g7+GTjhG7hzEUjHikyTHm5EAPVXSwwTmmRPqH8AyGzuhgyeBlzM sbVg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id f27si2000837ioi.102.2018.02.23.10.59.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 10:59:35 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXo-0003L4-1H; Fri, 23 Feb 2018 18:58:08 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXm-0003AJ-Hg for xen-devel@lists.xen.org; Fri, 23 Feb 2018 18:58:06 +0000 X-Inumbo-ID: b5c4229c-18cb-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id b5c4229c-18cb-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 18:59:44 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BA85A15BE; Fri, 23 Feb 2018 10:58:00 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 87A233F25C; Fri, 23 Feb 2018 10:57:59 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 18:57:28 +0000 Message-Id: <20180223185729.8780-18-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223185729.8780-1-julien.grall@arm.com> References: <20180223185729.8780-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, mirela.simonovic@aggios.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v5 17/18] xen/arm: vpsci: Introduce and use PSCI_INVALID_ADDRESS X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" PSCI 1.0 added the error return PSCI_INVALID_ADDRESS. It is used to indicate the entry point address is known to be invalid. In Xen case, this error could be returned when a 64-bit vCPU is using a Thumb entry address. For PSCI 0.1 implementation, return PSCI_INVALID_PARAMETERS instead. Suggested-by: mirela.simonovic@aggios.com Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini Cc: mirela.simonovic@aggios.com --- Changes in v4: - Add Stefano's reviewed-by Changes in v3: - Patch added --- xen/arch/arm/vpsci.c | 10 +++++++--- xen/include/asm-arm/psci.h | 1 + 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 9a082aa6ee..1729f7071e 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -38,7 +38,7 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, /* THUMB set is not allowed with 64-bit domain */ if ( is_64bit_domain(d) && is_thumb ) - return PSCI_INVALID_PARAMETERS; + return PSCI_INVALID_ADDRESS; if ( !test_bit(_VPF_down, &v->pause_flags) ) return PSCI_ALREADY_ON; @@ -99,10 +99,14 @@ static int32_t do_psci_cpu_on(uint32_t vcpuid, register_t entry_point) ret = do_common_cpu_on(vcpuid, entry_point, 0); /* - * PSCI 0.1 does not define the return code PSCI_ALREADY_ON. + * PSCI 0.1 does not define the return codes PSCI_ALREADY_ON and + * PSCI_INVALID_ADDRESS. * Instead, return PSCI_INVALID_PARAMETERS. */ - return (ret == PSCI_ALREADY_ON) ? PSCI_INVALID_PARAMETERS : ret; + if ( ret == PSCI_ALREADY_ON || ret == PSCI_INVALID_ADDRESS ) + ret = PSCI_INVALID_PARAMETERS; + + return ret; } static int32_t do_psci_cpu_off(uint32_t power_state) diff --git a/xen/include/asm-arm/psci.h b/xen/include/asm-arm/psci.h index e2629eed01..9ac820e94a 100644 --- a/xen/include/asm-arm/psci.h +++ b/xen/include/asm-arm/psci.h @@ -13,6 +13,7 @@ #define PSCI_INTERNAL_FAILURE -6 #define PSCI_NOT_PRESENT -7 #define PSCI_DISABLED -8 +#define PSCI_INVALID_ADDRESS -9 /* availability of PSCI on the host for SMP bringup */ extern uint32_t psci_ver; From patchwork Fri Feb 23 18:57:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129488 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp984771edc; Fri, 23 Feb 2018 10:59:55 -0800 (PST) X-Google-Smtp-Source: AH8x227ygc4Z3CxEo6wqVZRQ/U/eaBN8GlYUVvEeSF3v+8BZeYvhMYhzXw7RpBC5Rx6P5L24CCho X-Received: by 10.36.68.214 with SMTP id o205mr3399604ita.49.1519412395556; Fri, 23 Feb 2018 10:59:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519412395; cv=none; d=google.com; s=arc-20160816; b=fJGmeOw7/ofsuXJ/SFkf7AW2cK9DCEt33a4AhMoYnxChhmvcn5TmBA+z1TByPJy2JU /Qr4c9RGYerbvAl7UMr1dDpTKIX8jWPW41Bfw34p36K1wpfIwA4nZdT6/H1ujlAp9BHH JoaOK1WEa2t9DFJ2AtWKmF80CSgUFNBWeSqC/usJYnbiNoPJfvOm7kH3S6f+kIZFkhjE QQWeFNCs6Ash+DBETq/L2sygj17yZR7+lzFQjX07G0aeO0rw9XmmZgSgDTJD/ER2cgow ZLhytI2qwZ9CsbKSaAPrPsqACUyRSkUslA+CXEvTflEAsHoFlxbp1QdIfaPuqKr1j88q 0Fsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=ZgGCIv4UMySKAXi0fQJavGU/hzH+RKJWEdEIyP1zofY=; b=BSJe7PVb9OP2zrcnkMUFJaZCZD5Dw4UAit1XPiEZgdtCcd3mvIjRbFhbA1hJBGPuo4 DlkbMcdBh7nzYO1rYwToT2LxT+WaWF08Mm1m3+gZItVUm1Y/KIxg7w4VjE35+dYh+nWX zLcUgRK0LyLrYMyCsPkD6aqJWNZpahupqes2DJQc0muUhE2NEDFQl6qY1TDgN5TNgdZP u75wWt65d4zv0iInuK2/FgDtVb1asfj+jdbgIU1abihrZ2kZ1IAH/WrlMgLk7gyQ8De0 1PdqZRmbiRE0uQSZlhgFSvtyVtbidHo5IoLDNOmNdzW27nQ/0hwCP82aGU00HdpSTwPT JJIw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id x196si1581058itb.101.2018.02.23.10.59.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 10:59:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXk-0003Ej-Bn; Fri, 23 Feb 2018 18:58:04 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXi-0003Ca-SS for xen-devel@lists.xen.org; Fri, 23 Feb 2018 18:58:02 +0000 X-Inumbo-ID: 5b1739c6-18cb-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 5b1739c6-18cb-11e8-ba59-bc764e045a96; Fri, 23 Feb 2018 19:57:12 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3AFBA80D; Fri, 23 Feb 2018 10:58:02 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0567E3F25C; Fri, 23 Feb 2018 10:58:00 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 18:57:29 +0000 Message-Id: <20180223185729.8780-19-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223185729.8780-1-julien.grall@arm.com> References: <20180223185729.8780-1-julien.grall@arm.com> Cc: Andre Przywara , Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v5 18/18] xen/arm: vpsci: Rework the logic to start AArch32 vCPU in Thumb mode X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" 32-bit domain is able to select the instruction (ARM vs Thumb) to use when boot a new vCPU via CPU_ON. This is indicated via bit[0] of the entry point address (see "T32 support" in PSCI v1.1 DEN0022D). bit[0] must be cleared when setting the PC. At the moment, Xen is setting the CPSR.T but never clear bit[0]. Clear it to match the specification. At the same time, slighlty rework the code to make clear thumb is only for 32-bit domain. Lastly, take the opportunity to switch is_thumb from int to bool. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini Reviewed-by: Andre Przywara --- Changes in v4: - Add Stefano's reviewed-by - Add Andre's reviewed-by Changes in v3: - Patch added --- xen/arch/arm/vpsci.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index 1729f7071e..9f4e5b8844 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -28,7 +28,7 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, struct domain *d = current->domain; struct vcpu_guest_context *ctxt; int rc; - int is_thumb = entry_point & 1; + bool is_thumb = entry_point & 1; register_t vcpuid; vcpuid = vaffinity_to_vcpuid(target_cpu); @@ -62,6 +62,13 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, if ( is_32bit_domain(d) ) { ctxt->user_regs.cpsr = PSR_GUEST32_INIT; + /* Start the VCPU with THUMB set if it's requested by the kernel */ + if ( is_thumb ) + { + ctxt->user_regs.cpsr |= PSR_THUMB; + ctxt->user_regs.pc64 &= ~(u64)1; + } + ctxt->user_regs.r0_usr = context_id; } #ifdef CONFIG_ARM_64 @@ -71,10 +78,6 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point, ctxt->user_regs.x0 = context_id; } #endif - - /* Start the VCPU with THUMB set if it's requested by the kernel */ - if ( is_thumb ) - ctxt->user_regs.cpsr |= PSR_THUMB; ctxt->flags = VGCF_online; domain_lock(d);