From patchwork Thu Jan 14 15:26:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zulkifli, Muhammad Husaini" X-Patchwork-Id: 363219 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FA2DC433E9 for ; Thu, 14 Jan 2021 15:29:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5514423B7B for ; Thu, 14 Jan 2021 15:29:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729084AbhANP3P (ORCPT ); Thu, 14 Jan 2021 10:29:15 -0500 Received: from mga14.intel.com ([192.55.52.115]:7044 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726259AbhANP3O (ORCPT ); Thu, 14 Jan 2021 10:29:14 -0500 IronPort-SDR: BaNT3Bb6qOTjPIL5bXyO99UOwGWu71gmzpLGUUEGjMud6/bpJaOC6QPA+VG0ZZKqd6EOPpcA/0 gW0dQ7AC51ig== X-IronPort-AV: E=McAfee;i="6000,8403,9864"; a="177604650" X-IronPort-AV: E=Sophos;i="5.79,347,1602572400"; d="scan'208";a="177604650" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jan 2021 07:28:34 -0800 IronPort-SDR: dILQRkIpTGFKwwYtWjr0dNTrkFx0YCtigf5SjsCMPo5ZKO2KeyZCWXdfJPICI7i5St/VQiFC6r C/JucOne765w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,347,1602572400"; d="scan'208";a="568193576" Received: from zulkifl3-ilbpg0.png.intel.com ([10.88.229.114]) by orsmga005.jf.intel.com with ESMTP; 14 Jan 2021 07:28:31 -0800 From: Muhammad Husaini Zulkifli To: ulf.hansson@linaro.org, broonie@kernel.org, lgirdwood@gmail.com, robh+dt@kernel.org, devicetree@vger.kernel.org, adrian.hunter@intel.com, michal.simek@xilinx.com, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: andriy.shevchenko@intel.com, Rashmi.A@intel.com, mahesh.r.vaidya@intel.com, muhammad.husaini.zulkifli@intel.com Subject: [PATCH v1 2/9] mmc: sdhci-of-arasan: Convert to use np instead of pdev->dev.of_node Date: Thu, 14 Jan 2021 23:26:53 +0800 Message-Id: <20210114152700.21916-3-muhammad.husaini.zulkifli@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210114152700.21916-1-muhammad.husaini.zulkifli@intel.com> References: <20210114152700.21916-1-muhammad.husaini.zulkifli@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Use np pointer to simplify code and improve readability. Signed-off-by: Muhammad Husaini Zulkifli Suggested-by: Andy Shevchenko Acked-by: Adrian Hunter Acked-by: Andy Shevchenko --- drivers/mmc/host/sdhci-of-arasan.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index 07479019caf9..ecaea4b45367 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -1529,7 +1529,7 @@ static int sdhci_arasan_probe(struct platform_device *pdev) sdhci_arasan->soc_ctl_map = data->soc_ctl_map; sdhci_arasan->clk_ops = data->clk_ops; - node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0); + node = of_parse_phandle(np, "arasan,soc-ctl-syscon", 0); if (node) { sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node); of_node_put(node); @@ -1578,8 +1578,7 @@ static int sdhci_arasan_probe(struct platform_device *pdev) pltfm_host->clk = clk_xin; - if (of_device_is_compatible(pdev->dev.of_node, - "rockchip,rk3399-sdhci-5.1")) + if (of_device_is_compatible(np, "rockchip,rk3399-sdhci-5.1")) sdhci_arasan_update_clockmultiplier(host, 0x0); if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") || @@ -1612,8 +1611,7 @@ static int sdhci_arasan_probe(struct platform_device *pdev) } sdhci_arasan->phy = ERR_PTR(-ENODEV); - if (of_device_is_compatible(pdev->dev.of_node, - "arasan,sdhci-5.1")) { + if (of_device_is_compatible(np, "arasan,sdhci-5.1")) { sdhci_arasan->phy = devm_phy_get(&pdev->dev, "phy_arasan"); if (IS_ERR(sdhci_arasan->phy)) { From patchwork Thu Jan 14 15:26:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zulkifli, Muhammad Husaini" X-Patchwork-Id: 363217 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4983C4332E for ; Thu, 14 Jan 2021 15:29:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 844532311F for ; Thu, 14 Jan 2021 15:29:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728468AbhANP3X (ORCPT ); Thu, 14 Jan 2021 10:29:23 -0500 Received: from mga14.intel.com ([192.55.52.115]:7040 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726259AbhANP3X (ORCPT ); Thu, 14 Jan 2021 10:29:23 -0500 IronPort-SDR: XBuGuQw1kUP8iq7g9PWPEqJsNRVbR7o7+Suy8gmn9uXF4dX4LZYYhzWw1pZ0UGbBP1zXbam3UZ aYvmUn/9lp4g== X-IronPort-AV: E=McAfee;i="6000,8403,9864"; a="177604656" X-IronPort-AV: E=Sophos;i="5.79,347,1602572400"; d="scan'208";a="177604656" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jan 2021 07:28:37 -0800 IronPort-SDR: ZG4P16/Othm9qt5oxgjNakxTNBxKdYBmyvn6xMOivb3rCecCBHStIXOxMVzqOpbBxuX951Vopm uSAkRl839bNg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,347,1602572400"; d="scan'208";a="568193590" Received: from zulkifl3-ilbpg0.png.intel.com ([10.88.229.114]) by orsmga005.jf.intel.com with ESMTP; 14 Jan 2021 07:28:34 -0800 From: Muhammad Husaini Zulkifli To: ulf.hansson@linaro.org, broonie@kernel.org, lgirdwood@gmail.com, robh+dt@kernel.org, devicetree@vger.kernel.org, adrian.hunter@intel.com, michal.simek@xilinx.com, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: andriy.shevchenko@intel.com, Rashmi.A@intel.com, mahesh.r.vaidya@intel.com, muhammad.husaini.zulkifli@intel.com Subject: [PATCH v1 3/9] mmc: sdhci-of-arasan: Add structure device pointer in probe function Date: Thu, 14 Jan 2021 23:26:54 +0800 Message-Id: <20210114152700.21916-4-muhammad.husaini.zulkifli@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210114152700.21916-1-muhammad.husaini.zulkifli@intel.com> References: <20210114152700.21916-1-muhammad.husaini.zulkifli@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add struct device *dev in probe func() so that it can widely use in probe to make code more readable. Signed-off-by: Muhammad Husaini Zulkifli Acked-by: Adrian Hunter Acked-by: Andy Shevchenko --- drivers/mmc/host/sdhci-of-arasan.c | 34 +++++++++++++++--------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index ecaea4b45367..4e6ee9e69a1b 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -1512,11 +1512,12 @@ static int sdhci_arasan_probe(struct platform_device *pdev) struct clk *clk_xin; struct sdhci_host *host; struct sdhci_pltfm_host *pltfm_host; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; struct sdhci_arasan_data *sdhci_arasan; - struct device_node *np = pdev->dev.of_node; const struct sdhci_arasan_of_data *data; - data = of_device_get_match_data(&pdev->dev); + data = of_device_get_match_data(dev); host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan)); if (IS_ERR(host)) @@ -1535,36 +1536,36 @@ static int sdhci_arasan_probe(struct platform_device *pdev) of_node_put(node); if (IS_ERR(sdhci_arasan->soc_ctl_base)) { - ret = dev_err_probe(&pdev->dev, + ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->soc_ctl_base), "Can't get syscon\n"); goto err_pltfm_free; } } - sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb"); + sdhci_arasan->clk_ahb = devm_clk_get(dev, "clk_ahb"); if (IS_ERR(sdhci_arasan->clk_ahb)) { - dev_err(&pdev->dev, "clk_ahb clock not found.\n"); + dev_err(dev, "clk_ahb clock not found.\n"); ret = PTR_ERR(sdhci_arasan->clk_ahb); goto err_pltfm_free; } - clk_xin = devm_clk_get(&pdev->dev, "clk_xin"); + clk_xin = devm_clk_get(dev, "clk_xin"); if (IS_ERR(clk_xin)) { - dev_err(&pdev->dev, "clk_xin clock not found.\n"); + dev_err(dev, "clk_xin clock not found.\n"); ret = PTR_ERR(clk_xin); goto err_pltfm_free; } ret = clk_prepare_enable(sdhci_arasan->clk_ahb); if (ret) { - dev_err(&pdev->dev, "Unable to enable AHB clock.\n"); + dev_err(dev, "Unable to enable AHB clock.\n"); goto err_pltfm_free; } ret = clk_prepare_enable(clk_xin); if (ret) { - dev_err(&pdev->dev, "Unable to enable SD clock.\n"); + dev_err(dev, "Unable to enable SD clock.\n"); goto clk_dis_ahb; } @@ -1592,7 +1593,7 @@ static int sdhci_arasan_probe(struct platform_device *pdev) sdhci_arasan_update_baseclkfreq(host); - ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev); + ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, dev); if (ret) goto clk_disable_all; @@ -1601,28 +1602,27 @@ static int sdhci_arasan_probe(struct platform_device *pdev) arasan_zynqmp_execute_tuning; } - arasan_dt_parse_clk_phases(&pdev->dev, &sdhci_arasan->clk_data); + arasan_dt_parse_clk_phases(dev, &sdhci_arasan->clk_data); ret = mmc_of_parse(host->mmc); if (ret) { if (ret != -EPROBE_DEFER) - dev_err(&pdev->dev, "parsing dt failed (%d)\n", ret); + dev_err(dev, "parsing dt failed (%d)\n", ret); goto unreg_clk; } sdhci_arasan->phy = ERR_PTR(-ENODEV); if (of_device_is_compatible(np, "arasan,sdhci-5.1")) { - sdhci_arasan->phy = devm_phy_get(&pdev->dev, - "phy_arasan"); + sdhci_arasan->phy = devm_phy_get(dev, "phy_arasan"); if (IS_ERR(sdhci_arasan->phy)) { ret = PTR_ERR(sdhci_arasan->phy); - dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n"); + dev_err(dev, "No phy for arasan,sdhci-5.1.\n"); goto unreg_clk; } ret = phy_init(sdhci_arasan->phy); if (ret < 0) { - dev_err(&pdev->dev, "phy_init err.\n"); + dev_err(dev, "phy_init err.\n"); goto unreg_clk; } @@ -1647,7 +1647,7 @@ static int sdhci_arasan_probe(struct platform_device *pdev) if (!IS_ERR(sdhci_arasan->phy)) phy_exit(sdhci_arasan->phy); unreg_clk: - sdhci_arasan_unregister_sdclk(&pdev->dev); + sdhci_arasan_unregister_sdclk(dev); clk_disable_all: clk_disable_unprepare(clk_xin); clk_dis_ahb: From patchwork Thu Jan 14 15:26:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zulkifli, Muhammad Husaini" X-Patchwork-Id: 363218 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D559C433E6 for ; Thu, 14 Jan 2021 15:29:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0B36F23A24 for ; Thu, 14 Jan 2021 15:29:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729326AbhANP3a (ORCPT ); Thu, 14 Jan 2021 10:29:30 -0500 Received: from mga14.intel.com ([192.55.52.115]:7044 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726259AbhANP3a (ORCPT ); Thu, 14 Jan 2021 10:29:30 -0500 IronPort-SDR: /biz+3lnOHLOpJ4URRA8JMMHPSrlCC5lcxktsKDv7tfJ2VSvCqrFp/F5kvXeuWYgpXIbS63TkX c6/iCXRx96GA== X-IronPort-AV: E=McAfee;i="6000,8403,9864"; a="177604671" X-IronPort-AV: E=Sophos;i="5.79,347,1602572400"; d="scan'208";a="177604671" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jan 2021 07:28:43 -0800 IronPort-SDR: t3gUSsbPz4eDs4XJpMxRkNzkvPA3g4Cay+7UOr6avSj8H+sFzbFlU6QOv5GOq1tqGA7EBwKFxH 6Stg8Dmhsclw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,347,1602572400"; d="scan'208";a="568193613" Received: from zulkifl3-ilbpg0.png.intel.com ([10.88.229.114]) by orsmga005.jf.intel.com with ESMTP; 14 Jan 2021 07:28:40 -0800 From: Muhammad Husaini Zulkifli To: ulf.hansson@linaro.org, broonie@kernel.org, lgirdwood@gmail.com, robh+dt@kernel.org, devicetree@vger.kernel.org, adrian.hunter@intel.com, michal.simek@xilinx.com, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: andriy.shevchenko@intel.com, Rashmi.A@intel.com, mahesh.r.vaidya@intel.com, muhammad.husaini.zulkifli@intel.com Subject: [PATCH v1 5/9] firmware: keembay: Add support for Trusted Firmware Service call Date: Thu, 14 Jan 2021 23:26:56 +0800 Message-Id: <20210114152700.21916-6-muhammad.husaini.zulkifli@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210114152700.21916-1-muhammad.husaini.zulkifli@intel.com> References: <20210114152700.21916-1-muhammad.husaini.zulkifli@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Export inline function to encapsulate AON_CFG1 for controling the I/O Rail supplied voltage levels which communicate with Trusted Firmware. Signed-off-by: Muhammad Husaini Zulkifli Acked-by: Andy Shevchenko --- include/linux/firmware/intel/keembay.h | 82 ++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 include/linux/firmware/intel/keembay.h diff --git a/include/linux/firmware/intel/keembay.h b/include/linux/firmware/intel/keembay.h new file mode 100644 index 000000000000..f5a8dbfdb63b --- /dev/null +++ b/include/linux/firmware/intel/keembay.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Intel Keembay SOC Firmware API Layer + * + * Copyright (C) 2020, Intel Corporation + * + * Author: Muhammad Husaini Zulkifli + */ + +#ifndef __FIRMWARE_KEEMBAY_SMC_H__ +#define __FIRMWARE_KEEMBAY_SMC_H__ + +#include + +/* + * This file defines an API function that can be called by a device driver in order to + * communicate with Trusted Firmware - A profile(TF-A) or Trusted Firmware - M profile (TF-M). + */ + +#define KEEMBAY_SET_1V8_IO_RAIL 1 +#define KEEMBAY_SET_3V3_IO_RAIL 0 + +#define KEEMBAY_IOV_1_8V_uV 1800000 +#define KEEMBAY_IOV_3_3V_uV 3300000 + +#define KEEMBAY_SET_SD_VOLTAGE_ID 0xFF26 +#define KEEMBAY_GET_SD_VOLTAGE_ID 0xFF2A + +#define ARM_SMCCC_SIP_KEEMBAY_SET_SD_VOLTAGE \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_SIP, \ + KEEMBAY_SET_SD_VOLTAGE_ID) + +#define ARM_SMCCC_SIP_KEEMBAY_GET_SD_VOLTAGE \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_SIP, \ + KEEMBAY_GET_SD_VOLTAGE_ID) + +#define KEEMBAY_REG_NUM_CONSUMERS 2 + +struct keembay_reg_supply { + struct regulator *consumer; +}; + +#if IS_ENABLED(CONFIG_HAVE_ARM_SMCCC_DISCOVERY) +/* + * Voltage applied on the IO Rail is controlled from the Always On Register using specific + * bits in AON_CGF1 register. This is a secure register. Keem Bay SOC cannot exposed this + * register address to the outside world. + */ +static inline int keembay_set_io_rail_supplied_voltage(int volt) +{ + struct arm_smccc_res res; + + arm_smccc_1_1_invoke(ARM_SMCCC_SIP_KEEMBAY_SET_SD_VOLTAGE, volt, &res); + + return res.a0; +} + +static inline int keembay_get_io_rail_supplied_voltage(void) +{ + struct arm_smccc_res res; + + arm_smccc_1_1_invoke(ARM_SMCCC_SIP_KEEMBAY_GET_SD_VOLTAGE, &res); + + return res.a1; +} +#else +static inline int keembay_set_io_rail_supplied_voltage(int volt) +{ + return -ENODEV; +} + +static inline int keembay_get_io_rail_supplied_voltage(void) +{ + return -ENODEV; +} +#endif + +#endif /* __FIRMWARE_KEEMBAY_SMC_H__ */ From patchwork Thu Jan 14 15:26:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zulkifli, Muhammad Husaini" X-Patchwork-Id: 363216 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B510C433E0 for ; Thu, 14 Jan 2021 15:30:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 24CD02311F for ; Thu, 14 Jan 2021 15:30:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726459AbhANP3j (ORCPT ); Thu, 14 Jan 2021 10:29:39 -0500 Received: from mga14.intel.com ([192.55.52.115]:7040 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726259AbhANP3j (ORCPT ); Thu, 14 Jan 2021 10:29:39 -0500 IronPort-SDR: AGhfs9MEFqnXZX9N9IdMX5gmBGtFEkemHapAFSwBWwDzbjNQkkwsLHBhWXkCNCu70S5Sdtvb5u tRSXJUEf1/0A== X-IronPort-AV: E=McAfee;i="6000,8403,9864"; a="177604677" X-IronPort-AV: E=Sophos;i="5.79,347,1602572400"; d="scan'208";a="177604677" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jan 2021 07:28:46 -0800 IronPort-SDR: 5g3V5QAFOVvJOiwuicI7o4ju8thIa/KcAkcpOLGDM8bwESzPiJcm6Ga3vR7B/WSnN3s4gDvl/x BzMZXHhMmxwQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,347,1602572400"; d="scan'208";a="568193622" Received: from zulkifl3-ilbpg0.png.intel.com ([10.88.229.114]) by orsmga005.jf.intel.com with ESMTP; 14 Jan 2021 07:28:43 -0800 From: Muhammad Husaini Zulkifli To: ulf.hansson@linaro.org, broonie@kernel.org, lgirdwood@gmail.com, robh+dt@kernel.org, devicetree@vger.kernel.org, adrian.hunter@intel.com, michal.simek@xilinx.com, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: andriy.shevchenko@intel.com, Rashmi.A@intel.com, mahesh.r.vaidya@intel.com, muhammad.husaini.zulkifli@intel.com Subject: [PATCH v1 6/9] dt-bindings: mmc: Update phy and regulator supply for Keem Bay SOC Date: Thu, 14 Jan 2021 23:26:57 +0800 Message-Id: <20210114152700.21916-7-muhammad.husaini.zulkifli@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210114152700.21916-1-muhammad.husaini.zulkifli@intel.com> References: <20210114152700.21916-1-muhammad.husaini.zulkifli@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add DT bindings of vmmc, vqmmc and sdvrail supplies of regulator and phys for the phandle of sd0_phy which contain additional property for otap delay and sel_clk_buffer. Signed-off-by: Muhammad Husaini Zulkifli Acked-by: Adrian Hunter --- Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml index 37a5fe7b26dc..b77a1ff37afa 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml @@ -83,7 +83,7 @@ properties: - const: intel,keembay-sdhci-5.1-sd # Intel Keem Bay SD controller description: For this device it is strongly suggested to include - arasan,soc-ctl-syscon. + arasan,soc-ctl-syscon, phys, vmmc-supply, vqmmc-supply and sdvrail-supply. - const: intel,keembay-sdhci-5.1-sdio # Intel Keem Bay SDIO controller description: For this device it is strongly suggested to include @@ -299,5 +299,10 @@ examples: clock-names = "clk_xin", "clk_ahb"; clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>, <&scmi_clk KEEM_BAY_PSS_SD0>; + phys = <&sd0_phy>; + phy-names = "phy_arasan"; arasan,soc-ctl-syscon = <&sd0_phy_syscon>; + vmmc-supply = <®_sd0_vcc>; + vqmmc-supply = <®_sd0_vqcc>; + sdvrail-supply = <®ulator_rail>; }; From patchwork Thu Jan 14 15:27:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Zulkifli, Muhammad Husaini" X-Patchwork-Id: 363215 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CC21C433DB for ; Thu, 14 Jan 2021 15:31:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DECA42311F for ; Thu, 14 Jan 2021 15:31:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726465AbhANPby (ORCPT ); Thu, 14 Jan 2021 10:31:54 -0500 Received: from mga14.intel.com ([192.55.52.115]:7040 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729290AbhANP3y (ORCPT ); Thu, 14 Jan 2021 10:29:54 -0500 IronPort-SDR: xM73YUArT37qIhM80LIMC+3qiuQWW170TUbXUCF7LWAsIU8apgR+YbIRqFninkUCQLi0tDH0oN TS4KQlrqwbuw== X-IronPort-AV: E=McAfee;i="6000,8403,9864"; a="177604697" X-IronPort-AV: E=Sophos;i="5.79,347,1602572400"; d="scan'208";a="177604697" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jan 2021 07:28:56 -0800 IronPort-SDR: nP6C3lC+JjiBDX182Y3R3hgQLQY0sRYjpkIQeBwS+WDP3wqXHUVugQ/Vwd6izmiwdpgL6pQZ73 0nyTX1l18bDA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,347,1602572400"; d="scan'208";a="568193663" Received: from zulkifl3-ilbpg0.png.intel.com ([10.88.229.114]) by orsmga005.jf.intel.com with ESMTP; 14 Jan 2021 07:28:53 -0800 From: Muhammad Husaini Zulkifli To: ulf.hansson@linaro.org, broonie@kernel.org, lgirdwood@gmail.com, robh+dt@kernel.org, devicetree@vger.kernel.org, adrian.hunter@intel.com, michal.simek@xilinx.com, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: andriy.shevchenko@intel.com, Rashmi.A@intel.com, mahesh.r.vaidya@intel.com, muhammad.husaini.zulkifli@intel.com Subject: [PATCH v1 9/9] mmc: sdhci-of-arasan: Add UHS-1 support for Keem Bay SOC Date: Thu, 14 Jan 2021 23:27:00 +0800 Message-Id: <20210114152700.21916-10-muhammad.husaini.zulkifli@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210114152700.21916-1-muhammad.husaini.zulkifli@intel.com> References: <20210114152700.21916-1-muhammad.husaini.zulkifli@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Keem Bay SOC can support dual voltage operations for GPIO SD pins to either 1.8V or 3.3V for bus IO line power. In order to operate the GPIOs line for Clk, Cmd and Data on Keem Bay hardware, it is important to configure the supplied voltage applied to their I/O Rail and the output of the I²C expander pin. Final Voltage applied on the GPIOs line are dependent by both supplied voltage rail and expander pin output as it is been set after passing through the voltage sense resistor. Keem Bay hardware is somewhat unique in the way of how IO bus line voltage are been controlled. Expander pin output is controlled by gpio-regulator. Voltage rail output is controlled by Keem Bay SD regulator. Keem Bay SD regulator encapsulated the Secure Monitor Calling Convention (SMCCC) to communicate with Trusted Firmware during set voltage operation. Signed-off-by: Muhammad Husaini Zulkifli Acked-by: Adrian Hunter Acked-by: Andy Shevchenko --- drivers/mmc/host/sdhci-of-arasan.c | 263 +++++++++++++++++++++++++++++ 1 file changed, 263 insertions(+) diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index 585ca32ff330..94253e3b8e52 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include "cqhci.h" @@ -79,6 +80,8 @@ struct sdhci_arasan_soc_ctl_field { * @baseclkfreq: Where to find corecfg_baseclkfreq * @clockmultiplier: Where to find corecfg_clockmultiplier * @support64b: Where to find SUPPORT64B bit + * @otap_delay: Where to find otap_delay + * @sel_clk_buffer: Where to find clock buffer delay * @hiword_update: If true, use HIWORD_UPDATE to access the syscon * * It's up to the licensee of the Arsan IP block to make these available @@ -89,6 +92,8 @@ struct sdhci_arasan_soc_ctl_map { struct sdhci_arasan_soc_ctl_field baseclkfreq; struct sdhci_arasan_soc_ctl_field clockmultiplier; struct sdhci_arasan_soc_ctl_field support64b; + struct sdhci_arasan_soc_ctl_field otap_delay; + struct sdhci_arasan_soc_ctl_field sel_clk_buffer; bool hiword_update; }; @@ -139,6 +144,8 @@ struct sdhci_arasan_clk_data { * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers. * @soc_ctl_map: Map to get offsets into soc_ctl registers. * @quirks: Arasan deviations from spec. + * @aux_regulator: Struct for regulator. + * @aux_regulator_en: True if regulator is on; false if not. */ struct sdhci_arasan_data { struct sdhci_host *host; @@ -153,6 +160,8 @@ struct sdhci_arasan_data { struct regmap *soc_ctl_base; const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; unsigned int quirks; + struct regulator *aux_regulator; + bool aux_regulator_en; /* Controller does not have CD wired and will not function normally without */ #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0) @@ -189,6 +198,8 @@ static const struct sdhci_arasan_soc_ctl_map intel_keembay_soc_ctl_map = { .baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 }, .clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 }, .support64b = { .reg = 0x4, .width = 1, .shift = 24 }, + .otap_delay = { .reg = 0x24, .width = 5, .shift = 23 }, + .sel_clk_buffer = { .reg = 0x2c, .width = 3, .shift = 25 }, .hiword_update = false, }; @@ -364,6 +375,132 @@ static int sdhci_arasan_voltage_switch(struct mmc_host *mmc, return -EINVAL; } +/** + * sdhci_arasan_keembay_voltage_switch - Voltage switch operation + * @mmc: Pointer to mmc_host + * @ios: Pointer to IO bus setting + * + * For Keem Bay hardware, in order to operate the GPIOs line for Clk, Cmd and Data, + * it is important to configure the supplied voltage applied to their I/O Rail + * and the output of the I²C expander Pin. + * + * Note that to configure the voltage rail output setting, specific bits in AON_CFG + * register must be set. This AON_CFG register is a secure register. Keem Bay regulator + * was introduced to encapsulate the Secure Monitor Call Calling Convention (SMCCC) for + * voltage rail output change. While to configure the I²C expander pin output, + * GPIO regulator modelling is been used to control the pin state. + * + * Regulator configuration: + * mmc->supply.vqmmc - expander pin output voltage + * sdhci_arasan->aux_regulator - voltage rail output voltage + * + * Final Voltage applied on the GPIOs Line are dependent by both supplied voltage + * I/O Rail and expander pin output as it is been set after passing through the + * voltage sense resistor. + * + * Return: 0 on success and error value on error + */ +static int sdhci_arasan_keembay_voltage_switch(struct mmc_host *mmc, + struct mmc_ios *ios) +{ + struct sdhci_host *host = mmc_priv(mmc); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); + struct keembay_reg_supply supplies[KEEMBAY_REG_NUM_CONSUMERS]; + u16 ctrl_2, clk; + int i, ret; + + /* If no vqmmc supply then we can't change the expander pin output voltage */ + if (IS_ERR(mmc->supply.vqmmc)) + return PTR_ERR(mmc->supply.vqmmc); + + /* If no sdvrail supply then we can't change the voltage rail output voltage */ + if (IS_ERR(sdhci_arasan->aux_regulator)) + return PTR_ERR(sdhci_arasan->aux_regulator); + + supplies[0].consumer = mmc->supply.vqmmc; + supplies[1].consumer = sdhci_arasan->aux_regulator; + + switch (ios->signal_voltage) { + case MMC_SIGNAL_VOLTAGE_180: + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + clk &= ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + if (clk & SDHCI_CLOCK_CARD_EN) + return -EAGAIN; + + sdhci_writeb(host, SDHCI_POWER_ON | SDHCI_POWER_180, + SDHCI_POWER_CONTROL); + + for (i = 0; i < KEEMBAY_REG_NUM_CONSUMERS; i++) { + ret = regulator_set_voltage(supplies[i].consumer, + KEEMBAY_IOV_1_8V_uV, + KEEMBAY_IOV_1_8V_uV); + if (ret) + return ret; + } + + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + ctrl_2 |= SDHCI_CTRL_VDD_180; + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); + + /* Sleep for 5ms to stabilize 1.8V regulator */ + usleep_range(5000, 5500); + + /* 1.8V regulator output should be stable within 5 ms */ + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + if (!(ctrl_2 & SDHCI_CTRL_VDD_180)) + return -EAGAIN; + + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + clk |= SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + return 0; + case MMC_SIGNAL_VOLTAGE_330: + for (i = 0; i < KEEMBAY_REG_NUM_CONSUMERS; i++) { + ret = regulator_set_voltage(supplies[i].consumer, + KEEMBAY_IOV_3_3V_uV, + KEEMBAY_IOV_3_3V_uV); + if (ret) + return ret; + } + + /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + ctrl_2 &= ~SDHCI_CTRL_VDD_180; + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); + + /* Sleep for 5ms to stabilize 3.3V regulator */ + usleep_range(5000, 5500); + + /* 3.3V regulator output should be stable within 5 ms */ + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + if (ctrl_2 & SDHCI_CTRL_VDD_180) + return -EAGAIN; + return 0; + default: + return -EINVAL; + } +} + +static int sdhci_arasan_keembay_select_drive_strength(struct mmc_card *card, + unsigned int max_dtr, int host_drv, + int card_drv, int *drv_type) +{ + switch (card->host->ios.signal_voltage) { + case MMC_SIGNAL_VOLTAGE_180: + *drv_type = MMC_SET_DRIVER_TYPE_C; + return 0; + case MMC_SIGNAL_VOLTAGE_330: + *drv_type = MMC_SET_DRIVER_TYPE_B; + return 0; + default: + return -EINVAL; + } +} + static const struct sdhci_ops sdhci_arasan_ops = { .set_clock = sdhci_arasan_set_clock, .get_max_clock = sdhci_pltfm_clk_get_max_clock, @@ -968,6 +1105,72 @@ static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host) sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz); } +/** + * sdhci_arasan_update_otap_delay - Set otap delay + * @host: The sdhci_host + * @value: The value to write + * + * Otap delay can be use to control the txclk tap delay for flopping the final stage flops. + * + * NOTE: + * Many existing devices don't seem to do this and work fine. To keep compatibility for + * old hardware where the device tree doesn't provide a register map, this function is a + * noop if a soc_ctl_map hasn't been provided for this platform. + */ +static void sdhci_arasan_update_otap_delay(struct sdhci_host *host, u32 value) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); + const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; + struct device *dev = host->mmc->parent; + + /* Having a map is optional */ + soc_ctl_map = sdhci_arasan->soc_ctl_map; + if (!soc_ctl_map) + return; + + /* If we have a map, we expect to have a syscon */ + if (!sdhci_arasan->soc_ctl_base) { + dev_warn(dev, "Have regmap, but no soc-ctl-syscon.\n"); + return; + } + + sdhci_arasan_syscon_write(host, &soc_ctl_map->otap_delay, value); +} + +/** + * sdhci_arasan_update_sel_clkbuf - Clock buffer select + * @host: The sdhci_host + * @value: The value to write + * + * Clock buffer select is use to delay the clock buffer. + * + * NOTE: + * Many existing devices don't seem to do this and work fine. To keep compatibility for + * old hardware where the device tree doesn't provide a register map, this function is a + * noop if a soc_ctl_map hasn't been provided for this platform. + */ +static void sdhci_arasan_update_sel_clkbuf(struct sdhci_host *host, u32 value) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); + const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; + struct device *dev = host->mmc->parent; + + /* Having a map is optional */ + soc_ctl_map = sdhci_arasan->soc_ctl_map; + if (!soc_ctl_map) + return; + + /* If we have a map, we expect to have a syscon */ + if (!sdhci_arasan->soc_ctl_base) { + dev_warn(dev, "Have regmap, but no soc-ctl-syscon.\n"); + return; + } + + sdhci_arasan_syscon_write(host, &soc_ctl_map->sel_clk_buffer, value); +} + static void sdhci_arasan_set_clk_delays(struct sdhci_host *host) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); @@ -1256,6 +1459,42 @@ static const struct of_device_id sdhci_arasan_of_match[] = { }; MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match); +static int sdhci_arasan_keembay_regulator_setup(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); + struct device *dev = host->mmc->parent; + + sdhci_arasan->aux_regulator = devm_regulator_get_optional(dev, "sdvrail"); + if (IS_ERR(sdhci_arasan->aux_regulator)) + return PTR_ERR(sdhci_arasan->aux_regulator); + + return regulator_enable(sdhci_arasan->aux_regulator); +} + +static int sdhci_arasan_keembay_phy_configuration(struct sdhci_host *host) +{ + struct device *dev = host->mmc->parent; + struct device_node *phys; + u32 otap_delay, sel_clk_buffer; + + phys = of_parse_phandle(dev->of_node, "phys", 0); + if (!phys) { + dev_err(dev, "Can't get phys for sd0\n"); + return -ENODEV; + } + + of_property_read_u32(phys, "intel,keembay-emmc-phy-otap-dly", &otap_delay); + of_property_read_u32(phys, "intel,keembay-emmc-phy-sel-clkbuf", &sel_clk_buffer); + + of_node_put(phys); + + sdhci_arasan_update_otap_delay(host, otap_delay); + sdhci_arasan_update_sel_clkbuf(host, sel_clk_buffer); + + return 0; +} + /** * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use * @@ -1590,6 +1829,24 @@ static int sdhci_arasan_probe(struct platform_device *pdev) host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; } + if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd")) { + ret = sdhci_arasan_keembay_regulator_setup(host); + if (ret) + goto clk_disable_all; + + sdhci_arasan->aux_regulator_en = true; + + ret = sdhci_arasan_keembay_phy_configuration(host); + if (ret) + goto clk_disable_all; + + host->mmc_host_ops.start_signal_voltage_switch = + sdhci_arasan_keembay_voltage_switch; + + host->mmc_host_ops.select_drive_strength = + sdhci_arasan_keembay_select_drive_strength; + } + sdhci_arasan_update_baseclkfreq(host); ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, dev); @@ -1651,6 +1908,9 @@ static int sdhci_arasan_probe(struct platform_device *pdev) clk_dis_ahb: clk_disable_unprepare(sdhci_arasan->clk_ahb); err_pltfm_free: + if (sdhci_arasan->aux_regulator_en) + regulator_disable(sdhci_arasan->aux_regulator); + sdhci_pltfm_free(pdev); return ret; } @@ -1669,6 +1929,9 @@ static int sdhci_arasan_remove(struct platform_device *pdev) phy_exit(sdhci_arasan->phy); } + if (sdhci_arasan->aux_regulator_en) + regulator_disable(sdhci_arasan->aux_regulator); + sdhci_arasan_unregister_sdclk(&pdev->dev); ret = sdhci_pltfm_unregister(pdev);