From patchwork Mon Feb 26 15:04:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 129666 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp300537lja; Mon, 26 Feb 2018 07:06:03 -0800 (PST) X-Google-Smtp-Source: AH8x226ZS1qPsVvEpzfXQzmjonynb1B0zawpaK/XOovYie/Ea2Bdnl3OZSrR9/XA2HUuwDnCPvic X-Received: by 10.99.94.67 with SMTP id s64mr8456801pgb.379.1519657563060; Mon, 26 Feb 2018 07:06:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519657563; cv=none; d=google.com; s=arc-20160816; b=0Y4OIS/5n/r+wTRhvsWddC0AAUYM5wTJ63UBUHGSp30SQts/zcD0ErjIP0SUSAPgRL oPoPnyPZON+pDZrIEQb2iCr/1YRgyw+ub82U4hIKHeGk7WW+tcpLJCraPcb3ytk494T5 KCrVes4Bkgiox9J2PtBTx+UHMY/ZaplrjQvWS7AGIbejiahJ7wV7ofElVjXPmE/5pnG/ Y7nQuL7LSI1rZDUdabEfkDVw4CKERFTJq3OJ2jIino0qCcoOqocQGzRBccrWxzusW+g7 zLHXWc1Zj9qzkLqd7bxGTpDTdjN1Skt7LutDQf1743u5FwoLBWse1zFQF1cF7R5M60uU 9uog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=uYayreNaCexijW8oKgvS7R7gvZQf9Kw/3zESbbf2Yx0=; b=iyZ+QRbruu1P5RwimlJ9zMuX74Lzt+oz2jZeg7i8A3SGTRAsmpvR1KJrSMtsbCNR+q EZWObKRLI406+W56eD3rqvOlkWCMfOMs5BKmXw7F5WbXshFcG4QiIa+4use4U88+mnWk i9kHp518pjuH4iZmBAAcZ18HPDY9XgJnES/6tYw5xvZSUIj+tLQQUT/UnkBbrobu0pqj p4QqcewAXbL43wrvfbAr1EBtS90wMqxQmN/PVUDh0yTvlpYtlyKG/k3omoa1RaEQjzZV DURjSxovdFBq/Rrfxcv+wG24jR1Bk6oSSqqsR/MzxRjug2djWX0XOavzvBHHRzySbx7Z YChw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n13si5669818pgc.528.2018.02.26.07.06.02; Mon, 26 Feb 2018 07:06:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754056AbeBZPFE (ORCPT + 28 others); Mon, 26 Feb 2018 10:05:04 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:51130 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753879AbeBZPFA (ORCPT ); Mon, 26 Feb 2018 10:05:00 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EFE8A15BE; Mon, 26 Feb 2018 07:04:59 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C1EA03F59D; Mon, 26 Feb 2018 07:04:59 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 4F6B31AE53A8; Mon, 26 Feb 2018 15:05:01 +0000 (GMT) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon , Yoshinori Sato Subject: [RFC PATCH v2 01/12] h8300: Don't include linux/kernel.h in asm/atomic.h Date: Mon, 26 Feb 2018 15:04:49 +0000 Message-Id: <1519657500-15094-2-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1519657500-15094-1-git-send-email-will.deacon@arm.com> References: <1519657500-15094-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org linux/kernel.h isn't needed by asm/atomic.h and will result in circular dependencies when the asm-generic atomic bitops are built around the tomic_long_t interface. Remove the broad include and replace it with linux/compiler.h for READ_ONCE etc and asm/irqflags.h for arch_local_irq_save etc. Cc: Yoshinori Sato Signed-off-by: Will Deacon --- arch/h8300/include/asm/atomic.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.1.4 diff --git a/arch/h8300/include/asm/atomic.h b/arch/h8300/include/asm/atomic.h index 941e7554e886..b174dec099bf 100644 --- a/arch/h8300/include/asm/atomic.h +++ b/arch/h8300/include/asm/atomic.h @@ -2,8 +2,10 @@ #ifndef __ARCH_H8300_ATOMIC__ #define __ARCH_H8300_ATOMIC__ +#include #include #include +#include /* * Atomic operations that C can't guarantee us. Useful for @@ -15,8 +17,6 @@ #define atomic_read(v) READ_ONCE((v)->counter) #define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i)) -#include - #define ATOMIC_OP_RETURN(op, c_op) \ static inline int atomic_##op##_return(int i, atomic_t *v) \ { \ From patchwork Mon Feb 26 15:04:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 129664 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp300327lja; Mon, 26 Feb 2018 07:05:52 -0800 (PST) X-Google-Smtp-Source: AH8x225rmZVRbdznOYNbECkWdC5YissVlNit3eP33Lqj15Cku783PiaBjiUS1Wr3maRemqZEpd0w X-Received: by 2002:a17:902:901:: with SMTP id 1-v6mr10995575plm.404.1519657552210; Mon, 26 Feb 2018 07:05:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519657552; cv=none; d=google.com; s=arc-20160816; b=ME9LrTXe8RO8fMxdz2/7TUUs4hN+fP02MC1wnw3LfknZVugqWpWnarEpdZ6DFR2Nhu a43b/83D0NhDmizgyq2m87CwGkqNEFpEEjVaouSSYHg7ZTLQ5KrH3DaS/8BeD8cL/etj 6uQdRDYjr5KvqYV70GJMeuIxTMqtw+HE1pm8x3BOl/prP9TmXxoDhb6RQPpDyTrFBRBN llC0StzGTeBEW8WI5aNy4F5NprCh9WTeJ+gWvGzP5JhqY4pdUHUVPGVZcsMaptJffHFA BXzxl1ik0DZlTbm5ZHv/kBzHv1wXi5OiI5mnmIeqnR38LjlGoejt+RYaJ2Japjb3a2FX 2E7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=KPoO3xkmTJNlaTbhFQlzQWdV0d+0c5MF04CUiFuVFTI=; b=rBWWznJcIes3IEkFcTvfnSrZgkNwLnE/maG84/Al8b5Nca5garioyxc3NghHf0QsA0 Uq4wAf5JrgZd1S2r2u/1N9kddmJyVdko9uxAZqRGZook2FFXrrKHV8hS0lwNriK9EGkR hH+qYsM8xcff5lhDx9v3PMUMYOU9vSzOMtlbrlMy4tYb5C3Y4+6LjbCYgVHg//LxAp4T ugwLU2H1DtVXmyDLfdt7U9Dvnq1pq/tXmKJ/AhRQJv9sfS9xKZGcf32anKifg/9YpDIO HLqtBa7EjtdLXdsr1JBi89teP8QgaDAaYtz4qhDcKX86Y1p4kIFR5PLJd6y7W0cKTs3R tZmQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n13si5669818pgc.528.2018.02.26.07.05.51; Mon, 26 Feb 2018 07:05:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754076AbeBZPFG (ORCPT + 28 others); Mon, 26 Feb 2018 10:05:06 -0500 Received: from foss.arm.com ([217.140.101.70]:51140 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753903AbeBZPFA (ORCPT ); Mon, 26 Feb 2018 10:05:00 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 120041610; Mon, 26 Feb 2018 07:05:00 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D7E583F614; Mon, 26 Feb 2018 07:04:59 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 60CED1AE53AA; Mon, 26 Feb 2018 15:05:01 +0000 (GMT) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [RFC PATCH v2 02/12] m68k: Don't use asm-generic/bitops/lock.h Date: Mon, 26 Feb 2018 15:04:50 +0000 Message-Id: <1519657500-15094-3-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1519657500-15094-1-git-send-email-will.deacon@arm.com> References: <1519657500-15094-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org asm-generic/bitops/lock.h is shortly going to be built on top of the atomic_long_* API, which introduces a nasty circular dependency for m68k where linux/atomic.h pulls in linux/bitops.h via: linux/atomic.h asm/atomic.h linux/irqflags.h asm/irqflags.h linux/preempt.h asm/preempt.h asm-generic/preempt.h linux/thread_info.h asm/thread_info.h asm/page.h asm-generic/getorder.h linux/log2.h linux/bitops.h Since m68k isn't SMP and doesn't support ACQUIRE/RELEASE barriers, we can just define the lock bitops in terms of the atomic bitops in the asm/bitops.h header. Acked-by: Geert Uytterhoeven Signed-off-by: Will Deacon --- arch/m68k/include/asm/bitops.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 2.1.4 diff --git a/arch/m68k/include/asm/bitops.h b/arch/m68k/include/asm/bitops.h index 93b47b1f6fb4..18193419f97d 100644 --- a/arch/m68k/include/asm/bitops.h +++ b/arch/m68k/include/asm/bitops.h @@ -515,12 +515,16 @@ static inline int __fls(int x) #endif +/* Simple test-and-set bit locks */ +#define test_and_set_bit_lock test_and_set_bit +#define clear_bit_unlock clear_bit +#define __clear_bit_unlock clear_bit_unlock + #include #include #include #include #include -#include #endif /* __KERNEL__ */ #endif /* _M68K_BITOPS_H */ From patchwork Mon Feb 26 15:04:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 129663 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp299842lja; Mon, 26 Feb 2018 07:05:26 -0800 (PST) X-Google-Smtp-Source: AH8x227e5QO5ZMigmPMAiQI0pKNRm9SxjWmbMSM6Wbalqu5k1S0gMBYAqMZerBKU9eoioE79/4uT X-Received: by 2002:a17:902:b2c6:: with SMTP id x6-v6mr10812864plw.285.1519657526175; Mon, 26 Feb 2018 07:05:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519657526; cv=none; d=google.com; s=arc-20160816; b=rX7dNmUkFLXQBZT1DpKzNWFjWGGo+7M6SGSU+vbxU/ZMg/SKA6Q8SKBW1HD1C5GDRg yorKjBIoke3DEM8J1RW5T5qaeLzsZbdV4QKtJ4AZj4AdJv67QefjH6+p2KJHVA+UOpg/ td9yFbmXqcBKDOl8kglTKfPTgW7jDV4OdZ0u2ALfXrfZW7fm8981mN7mZT56a1vA6R7q +QCg+uqbpAy8jgyj77U784+ttZrnHcExq5XabDWALeG9HG0vwN9Lik6cLRQ/e3oRwpyi e4cfgui1PWrWyiYa70tYni6zA7iYEUjo7R4ItF2m1HYs9ZAsai+s+DErHDvnr3rftnHi a1EA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=0AQKq1mKVG0qdHu+zvxXwUHAuFLOceouIwgaHLTE/PU=; b=rDELrYHmvYdqj6eT9GGiot7l19UDxatpsGazBZYoaPTUX6STfOb+AnFaigREBuZmvF jphRlvDsIdY/6IC0bs8pDDOSJGAXKWzKrIifJhMIt13NEHCkhgFTOlXuDt98dLXqlIhr Qhv3hA/IlW5DzNF+bLk27nXSSHKRlO86X8k8VeVI13NE6jlsTiA1L8K9uI6bjqoCXWTe 1Hocg//BUyMDPUSiT6Z507KHa7FjUzrm1ByKbMICN6G5BclL9E6g+3TJQRCAnj8+WELV KLCbvhlxKLW0j3rjvUTJ3uR3ZSIO1TGrzu4UQgqYuKf0H8eM1OkweQdyP81jW2lqlPWR fe+Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j5si1634647pgp.193.2018.02.26.07.05.25; Mon, 26 Feb 2018 07:05:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754095AbeBZPFJ (ORCPT + 28 others); Mon, 26 Feb 2018 10:05:09 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:51150 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753944AbeBZPFA (ORCPT ); Mon, 26 Feb 2018 10:05:00 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2EB1E164F; Mon, 26 Feb 2018 07:05:00 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EC17B3F487; Mon, 26 Feb 2018 07:04:59 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 773381AE53AB; Mon, 26 Feb 2018 15:05:01 +0000 (GMT) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [RFC PATCH v2 03/12] asm-generic: Move some macros from linux/bitops.h to a new bits.h file Date: Mon, 26 Feb 2018 15:04:51 +0000 Message-Id: <1519657500-15094-4-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1519657500-15094-1-git-send-email-will.deacon@arm.com> References: <1519657500-15094-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In preparation for implementing the asm-generic atomic bitops in terms of atomic_long_*, we need to prevent asm/atomic.h implementations from pulling in linux/bitops.h. A common reason for this include is for the BITS_PER_BYTE definition, so move this and some other BIT and masking macros into a new header file, asm-generic/bits.h Signed-off-by: Will Deacon --- include/asm-generic/bits.h | 26 ++++++++++++++++++++++++++ include/linux/bitops.h | 22 +--------------------- 2 files changed, 27 insertions(+), 21 deletions(-) create mode 100644 include/asm-generic/bits.h -- 2.1.4 diff --git a/include/asm-generic/bits.h b/include/asm-generic/bits.h new file mode 100644 index 000000000000..738f8038440b --- /dev/null +++ b/include/asm-generic/bits.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_GENERIC_BITS_H +#define __ASM_GENERIC_BITS_H +#include + +#define BIT(nr) (1UL << (nr)) +#define BIT_ULL(nr) (1ULL << (nr)) +#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) +#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) +#define BIT_ULL_MASK(nr) (1ULL << ((nr) % BITS_PER_LONG_LONG)) +#define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG) +#define BITS_PER_BYTE 8 + +/* + * Create a contiguous bitmask starting at bit position @l and ending at + * position @h. For example + * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000. + */ +#define GENMASK(h, l) \ + (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) + +#define GENMASK_ULL(h, l) \ + (((~0ULL) - (1ULL << (l)) + 1) & \ + (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) + +#endif /* __ASM_GENERIC_BITS_H */ diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 4cac4e1a72ff..57ba7f67b360 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -2,29 +2,9 @@ #ifndef _LINUX_BITOPS_H #define _LINUX_BITOPS_H #include +#include -#ifdef __KERNEL__ -#define BIT(nr) (1UL << (nr)) -#define BIT_ULL(nr) (1ULL << (nr)) -#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) -#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) -#define BIT_ULL_MASK(nr) (1ULL << ((nr) % BITS_PER_LONG_LONG)) -#define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG) -#define BITS_PER_BYTE 8 #define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) -#endif - -/* - * Create a contiguous bitmask starting at bit position @l and ending at - * position @h. For example - * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000. - */ -#define GENMASK(h, l) \ - (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) - -#define GENMASK_ULL(h, l) \ - (((~0ULL) - (1ULL << (l)) + 1) & \ - (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) extern unsigned int __sw_hweight8(unsigned int w); extern unsigned int __sw_hweight16(unsigned int w); From patchwork Mon Feb 26 15:04:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 129681 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp304799lja; Mon, 26 Feb 2018 07:09:42 -0800 (PST) X-Google-Smtp-Source: AG47ELv3cj5djxz0I91c3vi/cxwIdjnDbfG9cMb7CBDYu370Ju0+lKdTNWXfnM/nQr2SxtiO3lED X-Received: by 2002:a25:845:: with SMTP id 66-v6mr6953958ybi.433.1519657782476; Mon, 26 Feb 2018 07:09:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519657782; cv=none; d=google.com; s=arc-20160816; b=frOkxH9AG6Rqurfj70a6shE/di3wugqGufN4dy6oj6aWV8JcRgYzt5E+ztb6BV07Q9 F+A3s0n5yOvajsBtGDvC85SwTF5yXcvCeG9lxLmdhvlx7MEn1g0q2GD6Y4g+Zih+Flpl gLjYlce5AelMd3ZPFPTHRr2rKhkqn6d/5Ws5TX3MvSusZA+Vf3iB9xIMSIkON476KeDj GfNtjPAa1JZIZFyc4UkSQClY2AgaRktMEL7/20wVnpwdgRUVI9G4dK4aRTjZn4DIiAQK kUY8yAod7ODqdQcHi76rbG2twgjjglZf+zg4LtGLYkMZ19N94MVU+FZUA6Id0YKcq6vh fM+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=doLSP4mOf6xS/gyiyhtRPbsqcGmgXTwXMVQjWgrInXY=; b=m+XDIBtX74GlpbdplBBU5jN4mq1nsI9AavWCs8OHPK2aKHpkasWDKLcocVs16Xgdvx +tFl3cf0QSYQ0QNMiw5rCpGyip0EwIX89U3Sw5a3HV/M2LOYax0E4MbcZNl89pN+qIJx 3wtWF4BYpVVSicB0X7gf97LAtHnV+4snOGab5r6Q06DAQLlTOpSKb+BmFWwe8QFgl6Q+ g/Ci22lIIgYYkhlCDGQ3v+zUcca7vMYIvXFmmQqUCvQ8eOwFomf4OC/DRIb/BRCVP2uY cjPIDUe/dP9qwgP7DpTAQRr4T+gfhF//U9rh98k68scNzdZ4yBPCBcEnJWtUSG8bTLIJ qYJA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d1-v6si1513397ybl.750.2018.02.26.07.09.42; Mon, 26 Feb 2018 07:09:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754209AbeBZPJd (ORCPT + 28 others); Mon, 26 Feb 2018 10:09:33 -0500 Received: from foss.arm.com ([217.140.101.70]:51170 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753952AbeBZPFA (ORCPT ); Mon, 26 Feb 2018 10:05:00 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 36FD1165C; Mon, 26 Feb 2018 07:05:00 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 086533F59D; Mon, 26 Feb 2018 07:05:00 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 8B86E1AE53AC; Mon, 26 Feb 2018 15:05:01 +0000 (GMT) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [RFC PATCH v2 04/12] openrisc: Don't pull in all of linux/bitops.h in asm/cmpxchg.h Date: Mon, 26 Feb 2018 15:04:52 +0000 Message-Id: <1519657500-15094-5-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1519657500-15094-1-git-send-email-will.deacon@arm.com> References: <1519657500-15094-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The openrisc implementation of asm/cmpxchg.h pulls in linux/bitops.h so that it can refer to BITS_PER_BYTE. It also transitively relies on this pulling in linux/compiler.h for READ_ONCE. Replace the #include with asm-generic/bits.h and linux/compiler.h Signed-off-by: Will Deacon --- arch/openrisc/include/asm/cmpxchg.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.1.4 diff --git a/arch/openrisc/include/asm/cmpxchg.h b/arch/openrisc/include/asm/cmpxchg.h index d29f7db53906..94b578388fe2 100644 --- a/arch/openrisc/include/asm/cmpxchg.h +++ b/arch/openrisc/include/asm/cmpxchg.h @@ -16,8 +16,9 @@ #ifndef __ASM_OPENRISC_CMPXCHG_H #define __ASM_OPENRISC_CMPXCHG_H +#include #include -#include +#include #define __HAVE_ARCH_CMPXCHG 1 From patchwork Mon Feb 26 15:04:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 129674 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp301436lja; Mon, 26 Feb 2018 07:06:50 -0800 (PST) X-Google-Smtp-Source: AH8x2268TdnapkMDCZSghrgWUTq+VAyXCSf1Nl5ZH2va+fh+wlGt+hdEkZHXhV3WeuEFOxGR62ue X-Received: by 10.101.87.132 with SMTP id b4mr8521851pgr.282.1519657610084; Mon, 26 Feb 2018 07:06:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519657610; cv=none; d=google.com; s=arc-20160816; b=v/A7EwoZPJcYRgRBmKRnsCmlUCgCHOBqN0ynN500feUsizncnXa0pF2KPaJ2dEvb5o ABKLp4+z7nxErIA7O/6bjNjpSRxUlk2reLUNM3UNdlagGqgSR7EUptH3LtUCv87+31dg Xkz4a2p0QB06X9nFIhJyYPaeQNZxs19ovtRZSOt4zFkFoc2RDEZFnT6MqNieuliypU1y PsMiDfxbwS9//CiQke2LzNIFuvOB+/DDLeQ3u6gZ7GQjE33jtcdFC1VsKxhM5fg9F7YD uJBOUgH6r37AkxLawmdTa6GvQ9tv8z5o7AiE4ZYYaW8OfCUk42GtsUFGyVsZIIXbblzD oaDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=k/L5L98AWbCTkZoMPBXy+EZ7uHB4y3MQcuL/bWRGZQc=; b=Pd295zaK7HD+4H03wGq0cCNQScV5phMEkgnzvf3JlCrfBwXbfv8TLxbyYgMy1vKqU4 wFOTnypEq9jjgoQ5NlfhbaCTts1RdR1N4+/IWr4WKyxU2WnNK1HYrZoggR3yUxc6AddF JjrJ4lSfYYIMtEp+PZF4QeTyBOF5dFb/mMRpDowNTG441A3V0joHCCFgwtXlWHNUhxav K96mciN6G3uB152eoMJ5ExC+8HAefRoNTPgjnMBGy3ECsfCVjGbDaxMPz+tnVpYUtmci qujtzObwErYYqeVlGaQqKD1Zuyk375aHM9aAopfd90tK0qamUGVOJla+bPz1M4912S0l 4VqQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l14si5597947pgc.615.2018.02.26.07.06.49; Mon, 26 Feb 2018 07:06:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754250AbeBZPGp (ORCPT + 28 others); Mon, 26 Feb 2018 10:06:45 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:51176 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753987AbeBZPFB (ORCPT ); Mon, 26 Feb 2018 10:05:01 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CA0751684; Mon, 26 Feb 2018 07:05:00 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9C36C3F487; Mon, 26 Feb 2018 07:05:00 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 9BD3B1AE53AD; Mon, 26 Feb 2018 15:05:01 +0000 (GMT) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [RFC PATCH v2 05/12] sh: Don't pull in all of linux/bitops.h in asm/cmpxchg-xchg.h Date: Mon, 26 Feb 2018 15:04:53 +0000 Message-Id: <1519657500-15094-6-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1519657500-15094-1-git-send-email-will.deacon@arm.com> References: <1519657500-15094-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The sh implementation of asm/cmpxchg-xchg.h pulls in linux/bitops.h so that it can refer to BITS_PER_BYTE. It also transitively relies on this pulling in linux/compiler.h for READ_ONCE. Replace the #include with asm-generic/bits.h and linux/compiler.h Signed-off-by: Will Deacon --- arch/sh/include/asm/cmpxchg-xchg.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.1.4 diff --git a/arch/sh/include/asm/cmpxchg-xchg.h b/arch/sh/include/asm/cmpxchg-xchg.h index 1e881f5db659..41c290efa3c4 100644 --- a/arch/sh/include/asm/cmpxchg-xchg.h +++ b/arch/sh/include/asm/cmpxchg-xchg.h @@ -8,7 +8,8 @@ * This work is licensed under the terms of the GNU GPL, version 2. See the * file "COPYING" in the main directory of this archive for more details. */ -#include +#include +#include #include /* From patchwork Mon Feb 26 15:04:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 129673 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp301324lja; Mon, 26 Feb 2018 07:06:44 -0800 (PST) X-Google-Smtp-Source: AH8x226O5K2v44YfyWYsoqV/icljkgvAu+lRtsGIUvM4UsLgkuT25TtcwtX985GQPtQYl72zYd7a X-Received: by 10.98.170.13 with SMTP id e13mr10895977pff.113.1519657604501; Mon, 26 Feb 2018 07:06:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519657604; cv=none; d=google.com; s=arc-20160816; b=Xwx8HQm0C9bqdmn0wAYebQGnz3WIL88qurCdueeR323NOOgC50s0v4lE7nB+kqqqo1 sGStFo94jr6rKGx5n7B6Xd7Vw7Zags801j63Ut8yBQhBUMD7i/CcyqAv/fwjqIQzjIJe XqPnkCTHvsOZO7E9Nuwbl1XiACwVrfwgoG2cnj7TrEga+2MhS7oiAIyI1kjmjUU8lMvN GRoTPEysHKNF9frhs+/VPD3tfzcpmsQZBDkts/FZYcJzM5eR3B8flLqVYgckDEQUAmRH /JaYdgm4o68OOLpq5ixsxKZG1UOdp4IGbrYimE2vjhx1y2otgVlIA3ChgHNFRkyVT6wh eH+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=vRafagUfTI2Cp462QPpxphE9QbS0qrGfDszWZgl8ppQ=; b=gJpmnGBV9b8aFHamJ6K7/Sy51HJwsL7OumhIiQ4Q2PIt4Q4Xf5PfCJmc3j7HojpQB3 6TqjNnmxpmGHAeLzqL5oH9kZS4iUqm/2KXR/zn4IWBDGOCaTsHRy09PpJzwbixYdd7II vnHASwHIwim7bW8GcAeVNMHl3wcrsvvwLEJCInpGB7j/LGUYAnM9agd3kifb6SnO3O4l TO6N69oDH/DW8arWNXG1zqyTGOSIsAvQIGsOt1/KHV0ZaZb03qZhWTaXrxnlovihHi9r qXW66uhFyp7UFyghJbAMEid+An2Kg4QrDKBjvE0tea6DAwLciTynRxyf0Gym5W/WwDDi Wtsw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l14si5597947pgc.615.2018.02.26.07.06.44; Mon, 26 Feb 2018 07:06:44 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754228AbeBZPGl (ORCPT + 28 others); Mon, 26 Feb 2018 10:06:41 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:51180 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753995AbeBZPFB (ORCPT ); Mon, 26 Feb 2018 10:05:01 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D2D7A1688; Mon, 26 Feb 2018 07:05:00 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A53903F59D; Mon, 26 Feb 2018 07:05:00 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id B028D1AE53AE; Mon, 26 Feb 2018 15:05:01 +0000 (GMT) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [RFC PATCH v2 06/12] arm64: fpsimd: include in fpsimd.h Date: Mon, 26 Feb 2018 15:04:54 +0000 Message-Id: <1519657500-15094-7-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1519657500-15094-1-git-send-email-will.deacon@arm.com> References: <1519657500-15094-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org fpsimd.h uses the __init annotation, so pull in linux/init.h Signed-off-by: Will Deacon --- arch/arm64/include/asm/fpsimd.h | 1 + 1 file changed, 1 insertion(+) -- 2.1.4 Acked-by: Mark Rutland diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h index 8857a0f0d0f7..fc3527b985ca 100644 --- a/arch/arm64/include/asm/fpsimd.h +++ b/arch/arm64/include/asm/fpsimd.h @@ -22,6 +22,7 @@ #ifndef __ASSEMBLY__ #include +#include #include /* From patchwork Mon Feb 26 15:04:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 129675 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp301808lja; Mon, 26 Feb 2018 07:07:10 -0800 (PST) X-Google-Smtp-Source: AH8x224CD4Vy8PAOZouy6XTAkewyleu+gqzj7kyGF+l2QEmWbharvSmM8EAZBWDEXtPINDG7xb4y X-Received: by 10.98.103.69 with SMTP id b66mr10971075pfc.114.1519657629959; Mon, 26 Feb 2018 07:07:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519657629; cv=none; d=google.com; s=arc-20160816; b=hsv8HLaICo+QL/GUiKoqY5f1pEkREuH8fdhGJQLd8ku3/U4bnFOUremJZkcWbb8ufu 7TrxJmvXXvv2vWBCRHsclXcIOBb8lgftW1cIyTx8xK+Y2rAx7oUU03p6xflTr1YjOr63 59tV8rfSBLZyjaKOadgei4qiB9S4vL+qw5UXJTjP7t1cST0lUxOHM4hSs5Ph4ZyIdZOC HVrGnk8SA/x3vvZ3G2c/ms3+K/8FfsFCRoakU1vT4A3rG3uSjHPEp00Gg25uD7D3Vjoy cirhaffxl/mvrXvZmi03YpLo65uRv/VAomfEZc/VwtvQo0KZVrxGYcpxerttHs4X4+cu jdAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=oPamFDuTPfWvaHSIje/AwDCdUYnXy06RGnF1Yx4WRzo=; b=zYLrKy4r+pIvE+KTwm3vtouIOzTx+FiA/pyQv3rDKkdfP7YwJxfU6sstx3sK+Yc8mj UWKNXVxiq1/yTP8hTt7MDiAEx0Ov5f+GS+HvQqXp/AuxcPOE7cVyFm6Z/Fuk/lNJ2LIi 4Dz9gHZDT8k3n/35ARTZBgtaY+JDs++1KTUW9hU1dEr/YCVE7BSLQfRyFOX89f4SeLMZ PD2CCsaL6D2m4qg2oYmzsLUYCBM2dpSRY2nKAfZw2EU1c7iSkfbLgWSy8PpiEmDSw8X7 LabA5FGrAFz2gHNAvzL7wva3VBWzF3/XSdjt0lGpxdQQiw5oVHcCJkIF3ZhwBO/KSzcJ ygyw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l14si5597947pgc.615.2018.02.26.07.07.09; Mon, 26 Feb 2018 07:07:09 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754082AbeBZPGi (ORCPT + 28 others); Mon, 26 Feb 2018 10:06:38 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:51184 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753996AbeBZPFB (ORCPT ); Mon, 26 Feb 2018 10:05:01 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DCCA8169F; Mon, 26 Feb 2018 07:05:00 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AEB783F614; Mon, 26 Feb 2018 07:05:00 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id C43681AE53AF; Mon, 26 Feb 2018 15:05:01 +0000 (GMT) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [RFC PATCH v2 07/12] arm64: lse: Include compiler_types.h and export.h for out-of-line LL/SC Date: Mon, 26 Feb 2018 15:04:55 +0000 Message-Id: <1519657500-15094-8-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1519657500-15094-1-git-send-email-will.deacon@arm.com> References: <1519657500-15094-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When the LL/SC atomics are moved out-of-line, they are annotated as notrace and exported to modules. Ensure we pull in the relevant include files so that these macros are defined when we need them. Signed-off-by: Will Deacon --- arch/arm64/include/asm/lse.h | 2 ++ 1 file changed, 2 insertions(+) -- 2.1.4 Acked-by: Mark Rutland diff --git a/arch/arm64/include/asm/lse.h b/arch/arm64/include/asm/lse.h index eec95768eaad..e612a6be113f 100644 --- a/arch/arm64/include/asm/lse.h +++ b/arch/arm64/include/asm/lse.h @@ -4,6 +4,8 @@ #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS) +#include +#include #include #include From patchwork Mon Feb 26 15:04:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 129662 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp299593lja; Mon, 26 Feb 2018 07:05:14 -0800 (PST) X-Google-Smtp-Source: AG47ELtLRBm6BvXdXfpx9vMxwRQ50V2Rr7Szd5u+CTY1QmZijJ5Qa0Zb5kJG4PXQgdlFDo8l+QDx X-Received: by 10.98.198.146 with SMTP id x18mr7743936pfk.22.1519657514591; Mon, 26 Feb 2018 07:05:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519657514; cv=none; d=google.com; s=arc-20160816; b=vdWGd0KYsJc4Ej1+E+zLJzm327aUHCvCS6m4ZJL+t4E3NMzslQlxxheEByjZVyNvcQ avzvvn/SBX00jnBz3J2qRkPR0GQbBKdJOssd+vok3spJNriREce0tu4uEd23s5rcw6vZ KN36VjmzNZKFpeahqUXYWykgNJmH5lEnEaYrMlJcyyKujHfQ93yQnKpxm9qZyc+Ul2Nq a9FLvES/tV99O8CAToDB3SQgXfpZkNgW9BUplu6h5NMQS4Z2wUQTlL8tUcUvccyYJxa7 qtEi4EgCM9VjS6P1l0q8vmpUE/G8eY47EhgYyYZV9c82btTb6SOZL3EMLP9GTKNRRJvy v4CA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=AWG6ru/EiZsl0QIEny6D8izP9jhw7W/o2xZA474lXtQ=; b=ic4DgFxIXfJpovzkx5SEE/UPl8MFcQ0QvNaD9CftGAIlva6J7lZB4O/GSEp3Qjc2cM nVguLYNaolxyvGDrLlprIup9lKjP2xQDxwzCtD8nqQTPeXKW1TUPot4772JvrweXrmcp Ghc/ua9EwInEmyOwlLDJcr5vXHPQWHkwLw4IieD7hORH+dr4sAIpCK2kl8AglZdE84Hn CfZBJWN9C4N9vAgHEyYlxupMZdGtkBP3v7AfvkFMpNSL1Q2nw1t8Max2YdyfGPkSbT1e MxZI49f9geu+S8kxBw2OMo1sl/DfwXY393CUMfVRNEIa80/462xM2QyE5V4/dFzWEndT hBVw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j5si1634647pgp.193.2018.02.26.07.05.14; Mon, 26 Feb 2018 07:05:14 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754116AbeBZPFL (ORCPT + 28 others); Mon, 26 Feb 2018 10:05:11 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:51188 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753999AbeBZPFB (ORCPT ); Mon, 26 Feb 2018 10:05:01 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E4E9716EA; Mon, 26 Feb 2018 07:05:00 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B79C33F7BD; Mon, 26 Feb 2018 07:05:00 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id D68A21AE53B0; Mon, 26 Feb 2018 15:05:01 +0000 (GMT) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [RFC PATCH v2 08/12] arm64: cmpxchg: Include build_bug.h instead of bug.h for BUILD_BUG Date: Mon, 26 Feb 2018 15:04:56 +0000 Message-Id: <1519657500-15094-9-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1519657500-15094-1-git-send-email-will.deacon@arm.com> References: <1519657500-15094-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Having asm/cmpxchg.h pull in linux/bug.h is problematic because this ends up pulling in the atomic bitops which themselves may be built on top of atomic.h and cmpxchg.h. Instead, just include build_bug.h for the definition of BUILD_BUG. Signed-off-by: Will Deacon --- arch/arm64/include/asm/cmpxchg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.1.4 diff --git a/arch/arm64/include/asm/cmpxchg.h b/arch/arm64/include/asm/cmpxchg.h index ae852add053d..bc9e07bc6428 100644 --- a/arch/arm64/include/asm/cmpxchg.h +++ b/arch/arm64/include/asm/cmpxchg.h @@ -18,7 +18,7 @@ #ifndef __ASM_CMPXCHG_H #define __ASM_CMPXCHG_H -#include +#include #include #include From patchwork Mon Feb 26 15:04:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 129676 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp302152lja; Mon, 26 Feb 2018 07:07:31 -0800 (PST) X-Google-Smtp-Source: AH8x227AlP2e47FEfS6KR+cZNBSr/Xype4CzqVXlpWJoLeJKANk2uFaQ1L5yWugz5MF+x9ZHI0BS X-Received: by 2002:a17:902:46a:: with SMTP id 97-v6mr10710130ple.96.1519657651327; Mon, 26 Feb 2018 07:07:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519657651; cv=none; d=google.com; s=arc-20160816; b=NjZhJBQFy3Y/8spvLJ33rySMPIlDDPoVbel6mYLXVn1qWpk5ScJLw2CNnA+ekkgDUw 1urFnxeMr2LBE5xCCl7DkQtS9xTI4T+SRrweZXzdSh6ofTtd7HBM7gMEoTtnnPNay6c3 tk/eJKLDHY2nPhRt+xjhBk5wvheiOcT1jNz5VP1pKUv2QU60KOZAwpuV5LFreshp1Z6m IWmZ3fw7hPjRbA0hYkD6LfbDJ+76NSH+Pm6tuFuKWk1s9817n5qxeHr7LKh3BBCmG9ws +vzIzjy5BUgPKLROW48xw1xD3Q9LO86jhcs18DIV60NTR8dQ9n4oxxF9+LkAV0lxX3Hb /Qrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=VU+CpT7H3yMXqUbNbCnOpiD9JYKLiKAtQwnyOdZDVVg=; b=x/A/Y8EsmRITl31UqwYlDibsjxi4QEqMUYVnixE+OvL4YvkoSsbwPp82aLyEI+6N7y i1/W4TnkuS7fz/ZylKN30rN3xgFOyEQiSzz0V7VzXEa4mmxe7W2deN5bdu3KdM9M+/AM YoyiZjwJWOSA63b9bddshPxfYGyUU6osS+bBnQ57waWHpdIcxSa8jDw4aJZIojk0ZNMf Iq+K4KmxvD6eEi6ksgCBHCMFcLlSR34e1RPFrSuROqBOIPduFZbwrA4bs/hXujs91BN7 rQwebEFtYY9TLLv33qmjcoiXeNtjZNGKZGWPNVLH/Bpwc3fVSlYY/KKXGaCuRQh7P8tr Zcog== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s6si5645847pgp.577.2018.02.26.07.07.31; Mon, 26 Feb 2018 07:07:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754204AbeBZPGf (ORCPT + 28 others); Mon, 26 Feb 2018 10:06:35 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:51192 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754000AbeBZPFB (ORCPT ); Mon, 26 Feb 2018 10:05:01 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F09D21713; Mon, 26 Feb 2018 07:05:00 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C2DCF3F7C5; Mon, 26 Feb 2018 07:05:00 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id E8DDD1AE53B1; Mon, 26 Feb 2018 15:05:01 +0000 (GMT) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [RFC PATCH v2 09/12] asm-generic/bitops/atomic.h: Rewrite using atomic_fetch_* Date: Mon, 26 Feb 2018 15:04:57 +0000 Message-Id: <1519657500-15094-10-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1519657500-15094-1-git-send-email-will.deacon@arm.com> References: <1519657500-15094-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The atomic bitops can actually be implemented pretty efficiently using the atomic_fetch_* ops, rather than explicit use of spinlocks. Cc: Peter Zijlstra Cc: Ingo Molnar Signed-off-by: Will Deacon --- include/asm-generic/bitops/atomic.h | 188 +++++++----------------------------- 1 file changed, 33 insertions(+), 155 deletions(-) -- 2.1.4 diff --git a/include/asm-generic/bitops/atomic.h b/include/asm-generic/bitops/atomic.h index 04deffaf5f7d..bca92586c2f6 100644 --- a/include/asm-generic/bitops/atomic.h +++ b/include/asm-generic/bitops/atomic.h @@ -2,189 +2,67 @@ #ifndef _ASM_GENERIC_BITOPS_ATOMIC_H_ #define _ASM_GENERIC_BITOPS_ATOMIC_H_ -#include -#include - -#ifdef CONFIG_SMP -#include -#include /* we use L1_CACHE_BYTES */ - -/* Use an array of spinlocks for our atomic_ts. - * Hash function to index into a different SPINLOCK. - * Since "a" is usually an address, use one spinlock per cacheline. - */ -# define ATOMIC_HASH_SIZE 4 -# define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ])) - -extern arch_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned; - -/* Can't use raw_spin_lock_irq because of #include problems, so - * this is the substitute */ -#define _atomic_spin_lock_irqsave(l,f) do { \ - arch_spinlock_t *s = ATOMIC_HASH(l); \ - local_irq_save(f); \ - arch_spin_lock(s); \ -} while(0) - -#define _atomic_spin_unlock_irqrestore(l,f) do { \ - arch_spinlock_t *s = ATOMIC_HASH(l); \ - arch_spin_unlock(s); \ - local_irq_restore(f); \ -} while(0) - - -#else -# define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0) -# define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0) -#endif +#include +#include +#include /* - * NMI events can occur at any time, including when interrupts have been - * disabled by *_irqsave(). So you can get NMI events occurring while a - * *_bit function is holding a spin lock. If the NMI handler also wants - * to do bit manipulation (and they do) then you can get a deadlock - * between the original caller of *_bit() and the NMI handler. - * - * by Keith Owens + * Implementation of atomic bitops using atomic-fetch ops. + * See Documentation/atomic_bitops.txt for details. */ -/** - * set_bit - Atomically set a bit in memory - * @nr: the bit to set - * @addr: the address to start counting from - * - * This function is atomic and may not be reordered. See __set_bit() - * if you do not require the atomic guarantees. - * - * Note: there are no guarantees that this function will not be reordered - * on non x86 architectures, so if you are writing portable code, - * make sure not to rely on its reordering guarantees. - * - * Note that @nr may be almost arbitrarily large; this function is not - * restricted to acting on a single-word quantity. - */ -static inline void set_bit(int nr, volatile unsigned long *addr) +static inline void set_bit(unsigned int nr, volatile unsigned long *p) { - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long flags; - - _atomic_spin_lock_irqsave(p, flags); - *p |= mask; - _atomic_spin_unlock_irqrestore(p, flags); + p += BIT_WORD(nr); + atomic_long_fetch_or_relaxed(BIT_MASK(nr), (atomic_long_t *)p); } -/** - * clear_bit - Clears a bit in memory - * @nr: Bit to clear - * @addr: Address to start counting from - * - * clear_bit() is atomic and may not be reordered. However, it does - * not contain a memory barrier, so if it is used for locking purposes, - * you should call smp_mb__before_atomic() and/or smp_mb__after_atomic() - * in order to ensure changes are visible on other processors. - */ -static inline void clear_bit(int nr, volatile unsigned long *addr) +static inline void clear_bit(unsigned int nr, volatile unsigned long *p) { - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long flags; - - _atomic_spin_lock_irqsave(p, flags); - *p &= ~mask; - _atomic_spin_unlock_irqrestore(p, flags); + p += BIT_WORD(nr); + atomic_long_fetch_andnot_relaxed(BIT_MASK(nr), (atomic_long_t *)p); } -/** - * change_bit - Toggle a bit in memory - * @nr: Bit to change - * @addr: Address to start counting from - * - * change_bit() is atomic and may not be reordered. It may be - * reordered on other architectures than x86. - * Note that @nr may be almost arbitrarily large; this function is not - * restricted to acting on a single-word quantity. - */ -static inline void change_bit(int nr, volatile unsigned long *addr) +static inline void change_bit(unsigned int nr, volatile unsigned long *p) { - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long flags; - - _atomic_spin_lock_irqsave(p, flags); - *p ^= mask; - _atomic_spin_unlock_irqrestore(p, flags); + p += BIT_WORD(nr); + atomic_long_fetch_xor_relaxed(BIT_MASK(nr), (atomic_long_t *)p); } -/** - * test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It may be reordered on other architectures than x86. - * It also implies a memory barrier. - */ -static inline int test_and_set_bit(int nr, volatile unsigned long *addr) +static inline int test_and_set_bit(unsigned int nr, volatile unsigned long *p) { + long old; unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old; - unsigned long flags; - _atomic_spin_lock_irqsave(p, flags); - old = *p; - *p = old | mask; - _atomic_spin_unlock_irqrestore(p, flags); + p += BIT_WORD(nr); + if (READ_ONCE(*p) & mask) + return 1; - return (old & mask) != 0; + old = atomic_long_fetch_or(mask, (atomic_long_t *)p); + return !!(old & mask); } -/** - * test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to clear - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It can be reorderdered on other architectures other than x86. - * It also implies a memory barrier. - */ -static inline int test_and_clear_bit(int nr, volatile unsigned long *addr) +static inline int test_and_clear_bit(unsigned int nr, volatile unsigned long *p) { + long old; unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old; - unsigned long flags; - _atomic_spin_lock_irqsave(p, flags); - old = *p; - *p = old & ~mask; - _atomic_spin_unlock_irqrestore(p, flags); + p += BIT_WORD(nr); + if (!(READ_ONCE(*p) & mask)) + return 0; - return (old & mask) != 0; + old = atomic_long_fetch_andnot(mask, (atomic_long_t *)p); + return !!(old & mask); } -/** - * test_and_change_bit - Change a bit and return its old value - * @nr: Bit to change - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. - */ -static inline int test_and_change_bit(int nr, volatile unsigned long *addr) +static inline int test_and_change_bit(unsigned int nr, volatile unsigned long *p) { + long old; unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old; - unsigned long flags; - - _atomic_spin_lock_irqsave(p, flags); - old = *p; - *p = old ^ mask; - _atomic_spin_unlock_irqrestore(p, flags); - return (old & mask) != 0; + p += BIT_WORD(nr); + old = atomic_long_fetch_xor(mask, (atomic_long_t *)p); + return !!(old & mask); } #endif /* _ASM_GENERIC_BITOPS_ATOMIC_H */ From patchwork Mon Feb 26 15:04:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 129671 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp301139lja; Mon, 26 Feb 2018 07:06:35 -0800 (PST) X-Google-Smtp-Source: AH8x224ljnCjGzkVsNGGUho9Y+nHv1Mc0yQnwitE4OIYd6GC3fz+WbcSfq2ZFC+rFCwCC//BTAbM X-Received: by 10.99.154.73 with SMTP id e9mr8474106pgo.26.1519657595197; Mon, 26 Feb 2018 07:06:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519657595; cv=none; d=google.com; s=arc-20160816; b=mO0ZcJjg4ZqeBjX/tnOdWoKJU2OPECypBewboLlUPWZ0xfbnQWNur7kSziLSncEHzw +SLK9Sw6AjTiz4U5FPhA3mZfanEdMja4kV6wh5nC76UzdlfVhHRgoA3bfMFSVHwrJhHM l2Tuf3YKC5bZ0LslhcSD3LAU1yM65ZCD3OsGkEc4eel9DHsFIz26w3y+9Z6CLjDjfnPc 2dSgXZhzhqYtOAOWFlEIyzUJ0BYGOMmfd2dJVdOvS5k0agumkVyx0aCgePi5OMh9qIjH 1pabD6TzC2ILAUjvZF/WXE6/E5JkZWNwiU3AtRAF3seyDXMsbTFfpBtFyoSr/DLZ3Rkr Zfig== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id l14si5597947pgc.615.2018.02.26.07.06.34; Mon, 26 Feb 2018 07:06:35 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754190AbeBZPGb (ORCPT + 28 others); Mon, 26 Feb 2018 10:06:31 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:51196 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754003AbeBZPFB (ORCPT ); Mon, 26 Feb 2018 10:05:01 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 058FE1715; Mon, 26 Feb 2018 07:05:01 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id CBE973F487; Mon, 26 Feb 2018 07:05:00 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 04FC31AE53B2; Mon, 26 Feb 2018 15:05:01 +0000 (GMT) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [RFC PATCH v2 10/12] asm-generic/bitops/lock.h: Rewrite using atomic_fetch_* Date: Mon, 26 Feb 2018 15:04:58 +0000 Message-Id: <1519657500-15094-11-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1519657500-15094-1-git-send-email-will.deacon@arm.com> References: <1519657500-15094-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The lock bitops can be implemented more efficiently using the atomic_fetch_* ops, which provide finer-grained control over the memory ordering semantics than the bitops. Cc: Peter Zijlstra Cc: Ingo Molnar Signed-off-by: Will Deacon --- include/asm-generic/bitops/lock.h | 68 ++++++++++++++++++++++++++++++++------- 1 file changed, 56 insertions(+), 12 deletions(-) -- 2.1.4 diff --git a/include/asm-generic/bitops/lock.h b/include/asm-generic/bitops/lock.h index 67ab280ad134..3ae021368f48 100644 --- a/include/asm-generic/bitops/lock.h +++ b/include/asm-generic/bitops/lock.h @@ -2,6 +2,10 @@ #ifndef _ASM_GENERIC_BITOPS_LOCK_H_ #define _ASM_GENERIC_BITOPS_LOCK_H_ +#include +#include +#include + /** * test_and_set_bit_lock - Set a bit and return its old value, for lock * @nr: Bit to set @@ -11,7 +15,20 @@ * the returned value is 0. * It can be used to implement bit locks. */ -#define test_and_set_bit_lock(nr, addr) test_and_set_bit(nr, addr) +static inline int test_and_set_bit_lock(unsigned int nr, + volatile unsigned long *p) +{ + long old; + unsigned long mask = BIT_MASK(nr); + + p += BIT_WORD(nr); + if (READ_ONCE(*p) & mask) + return 1; + + old = atomic_long_fetch_or_acquire(mask, (atomic_long_t *)p); + return !!(old & mask); +} + /** * clear_bit_unlock - Clear a bit in memory, for unlock @@ -20,11 +37,11 @@ * * This operation is atomic and provides release barrier semantics. */ -#define clear_bit_unlock(nr, addr) \ -do { \ - smp_mb__before_atomic(); \ - clear_bit(nr, addr); \ -} while (0) +static inline void clear_bit_unlock(unsigned int nr, volatile unsigned long *p) +{ + p += BIT_WORD(nr); + atomic_long_fetch_andnot_release(BIT_MASK(nr), (atomic_long_t *)p); +} /** * __clear_bit_unlock - Clear a bit in memory, for unlock @@ -37,11 +54,38 @@ do { \ * * See for example x86's implementation. */ -#define __clear_bit_unlock(nr, addr) \ -do { \ - smp_mb__before_atomic(); \ - clear_bit(nr, addr); \ -} while (0) +static inline void __clear_bit_unlock(unsigned int nr, + volatile unsigned long *p) +{ + unsigned long old; -#endif /* _ASM_GENERIC_BITOPS_LOCK_H_ */ + p += BIT_WORD(nr); + old = READ_ONCE(*p); + old &= ~BIT_MASK(nr); + atomic_long_set_release((atomic_long_t *)p, old); +} + +/** + * clear_bit_unlock_is_negative_byte - Clear a bit in memory and test if bottom + * byte is negative, for unlock. + * @nr: the bit to clear + * @addr: the address to start counting from + * + * This is a bit of a one-trick-pony for the filemap code, which clears + * PG_locked and tests PG_waiters, + */ +#ifndef clear_bit_unlock_is_negative_byte +static inline bool clear_bit_unlock_is_negative_byte(unsigned int nr, + volatile unsigned long *p) +{ + long old; + unsigned long mask = BIT_MASK(nr); + + p += BIT_WORD(nr); + old = atomic_long_fetch_andnot_release(mask, (atomic_long_t *)p); + return !!(old & BIT(7)); +} +#define clear_bit_unlock_is_negative_byte clear_bit_unlock_is_negative_byte +#endif +#endif /* _ASM_GENERIC_BITOPS_LOCK_H_ */ From patchwork Mon Feb 26 15:04:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 129670 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp301084lja; Mon, 26 Feb 2018 07:06:32 -0800 (PST) X-Google-Smtp-Source: AH8x226KLp1Sgl8/EPxBbZalbK8os5ry2/+Ky9IPfTIkl64U9vhHyhiI33cW62ovruKcc25RItQi X-Received: by 2002:a17:902:968e:: with SMTP id n14-v6mr11023057plp.21.1519657592708; Mon, 26 Feb 2018 07:06:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519657592; cv=none; d=google.com; s=arc-20160816; b=xs6siP9nHM95QDWM7wju3Me9wp/3sQ/hGiQk4Yzxh5ZdsWrQwKTkEFLor0WwuvgrI2 CKILFJDHcEaJoA/NDoU0YRNNMgVI0umBIysIWsgxAHObQBQfgpZYKC8Z7/0sTc2Lg5i8 rszGZGms0QnFuBnDTGixDfSQLduoOqZ3DgrmCMAZ2w05BpNQk2qkq41ubAERnitVXjU+ Jj9TiEwgSQj+XqefCoXZmZq9XBiXD1NT29jLbT7L0omj9EhgBYJGHsYGOVFfzSrstnMO baK5cRPhYMi5ysOLzXI0FWB6evx1ro90u/OhGhlxuc2nhSBTlhHnWVJjKiEbmqBKsbvg KTMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=dGx2np7lZ7ebNDSNCdjeMawKlshuOn4jhUAX2wpYfQ4=; b=jweVRQQpOlRFYNpKUyv0ZpClpbVcXbf0SP62YUVIYJ68Z0GnA0f4+Wfs30KHLZ6BAR O5Anfy+QGkyliSjaeuUDhf/nbV7jilVXZVoNwu5oaNKO3d66Ylp73EGfzEEFqeooaR4d GVAMcnvD7AkACVahL3ZNRhzBpTRk223EGrGEV+U2R1PS2TU5cRsN9MLPduILIXA1PCqx gxfhYJ8tbYQKurQII6H5Zlw6ZLCUcFRaKK2D18bs2669lKhIXePuhYAs0RhBt7zjXiDf Ps6r54qx74biOwDBKJdMUJvIVhgoq7SB5E9btx1nJCI9t6Q+v0uXSx8KOsBGop8Etppz fCqw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f64-v6si6860754plb.377.2018.02.26.07.06.32; Mon, 26 Feb 2018 07:06:32 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754176AbeBZPG3 (ORCPT + 28 others); Mon, 26 Feb 2018 10:06:29 -0500 Received: from foss.arm.com ([217.140.101.70]:51200 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754007AbeBZPFB (ORCPT ); Mon, 26 Feb 2018 10:05:01 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 128FC174E; Mon, 26 Feb 2018 07:05:01 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D896F3F59D; Mon, 26 Feb 2018 07:05:00 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 1297F1AE53B3; Mon, 26 Feb 2018 15:05:02 +0000 (GMT) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [RFC PATCH v2 11/12] arm64: Replace our atomic/lock bitop implementations with asm-generic Date: Mon, 26 Feb 2018 15:04:59 +0000 Message-Id: <1519657500-15094-12-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1519657500-15094-1-git-send-email-will.deacon@arm.com> References: <1519657500-15094-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The asm-generic/bitops/{atomic,lock}.h implementations are built around the atomic-fetch ops, which we implement efficiently for both LSE and LL/SC systems. Use that instead of our hand-rolled, out-of-line bitops.S. Signed-off-by: Will Deacon --- arch/arm64/include/asm/bitops.h | 14 ++------ arch/arm64/lib/Makefile | 2 +- arch/arm64/lib/bitops.S | 76 ----------------------------------------- 3 files changed, 3 insertions(+), 89 deletions(-) delete mode 100644 arch/arm64/lib/bitops.S -- 2.1.4 diff --git a/arch/arm64/include/asm/bitops.h b/arch/arm64/include/asm/bitops.h index 9c19594ce7cb..13501460be6b 100644 --- a/arch/arm64/include/asm/bitops.h +++ b/arch/arm64/include/asm/bitops.h @@ -17,22 +17,11 @@ #define __ASM_BITOPS_H #include -#include #ifndef _LINUX_BITOPS_H #error only can be included directly #endif -/* - * Little endian assembly atomic bitops. - */ -extern void set_bit(int nr, volatile unsigned long *p); -extern void clear_bit(int nr, volatile unsigned long *p); -extern void change_bit(int nr, volatile unsigned long *p); -extern int test_and_set_bit(int nr, volatile unsigned long *p); -extern int test_and_clear_bit(int nr, volatile unsigned long *p); -extern int test_and_change_bit(int nr, volatile unsigned long *p); - #include #include #include @@ -44,8 +33,9 @@ extern int test_and_change_bit(int nr, volatile unsigned long *p); #include #include -#include +#include +#include #include #include diff --git a/arch/arm64/lib/Makefile b/arch/arm64/lib/Makefile index 4e696f96451f..73095a04c0ad 100644 --- a/arch/arm64/lib/Makefile +++ b/arch/arm64/lib/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -lib-y := bitops.o clear_user.o delay.o copy_from_user.o \ +lib-y := clear_user.o delay.o copy_from_user.o \ copy_to_user.o copy_in_user.o copy_page.o \ clear_page.o memchr.o memcpy.o memmove.o memset.o \ memcmp.o strcmp.o strncmp.o strlen.o strnlen.o \ diff --git a/arch/arm64/lib/bitops.S b/arch/arm64/lib/bitops.S deleted file mode 100644 index 43ac736baa5b..000000000000 --- a/arch/arm64/lib/bitops.S +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Based on arch/arm/lib/bitops.h - * - * Copyright (C) 2013 ARM Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include - -/* - * x0: bits 5:0 bit offset - * bits 31:6 word offset - * x1: address - */ - .macro bitop, name, llsc, lse -ENTRY( \name ) - and w3, w0, #63 // Get bit offset - eor w0, w0, w3 // Clear low bits - mov x2, #1 - add x1, x1, x0, lsr #3 // Get word offset -alt_lse " prfm pstl1strm, [x1]", "nop" - lsl x3, x2, x3 // Create mask - -alt_lse "1: ldxr x2, [x1]", "\lse x3, [x1]" -alt_lse " \llsc x2, x2, x3", "nop" -alt_lse " stxr w0, x2, [x1]", "nop" -alt_lse " cbnz w0, 1b", "nop" - - ret -ENDPROC(\name ) - .endm - - .macro testop, name, llsc, lse -ENTRY( \name ) - and w3, w0, #63 // Get bit offset - eor w0, w0, w3 // Clear low bits - mov x2, #1 - add x1, x1, x0, lsr #3 // Get word offset -alt_lse " prfm pstl1strm, [x1]", "nop" - lsl x4, x2, x3 // Create mask - -alt_lse "1: ldxr x2, [x1]", "\lse x4, x2, [x1]" - lsr x0, x2, x3 -alt_lse " \llsc x2, x2, x4", "nop" -alt_lse " stlxr w5, x2, [x1]", "nop" -alt_lse " cbnz w5, 1b", "nop" -alt_lse " dmb ish", "nop" - - and x0, x0, #1 - ret -ENDPROC(\name ) - .endm - -/* - * Atomic bit operations. - */ - bitop change_bit, eor, steor - bitop clear_bit, bic, stclr - bitop set_bit, orr, stset - - testop test_and_change_bit, eor, ldeoral - testop test_and_clear_bit, bic, ldclral - testop test_and_set_bit, orr, ldsetal From patchwork Mon Feb 26 15:05:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 129669 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp300998lja; Mon, 26 Feb 2018 07:06:28 -0800 (PST) X-Google-Smtp-Source: AH8x227XHWo6TbG12tIsWy34/Pu3ae5mPTNFCfEFhWv4qoOq6Fe/Sv0EIcgaNYrgYoqi9oyhI1UN X-Received: by 10.99.110.199 with SMTP id j190mr8663768pgc.404.1519657588310; Mon, 26 Feb 2018 07:06:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519657588; cv=none; d=google.com; s=arc-20160816; b=nYWi3F9Ac4COWyu+Rv4OfI9hhVBiIXV0xbUiNX5ZuOFCHuR5SWx/E7DXO3cbHLro5a 1r7sWOUZ8aV9nOGg71/j6XaY0MBHrYQPrRPhG88GdLKV9nXLQjHNsvWmVKIt0TGgc1aV JCCe00KzdWtmnvfMv0wYLuScCZij+Eh5Rwkqu/61iZrfMPQIDgBocl+a167ttrKx3gAS cV4QEv0UBgs1kMG2NX5k/uEZ5hm7hB6r3zDXAcsuiHenfujQ11b+cjahOH5zlD3lYqa4 X3etKjx31aHYzIZIE7uOmQgb0RrdjdyOfTtbdryuitMKHSihlmQyIGaikjGsLA2N/rOx j5aA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=n5MGW/pfF/fJTATDJDJJ2DG14cgfSYeD3F8Z9NccPfo=; b=vR6K3KCMYoBT96OsdhPDPebHxzFlaYinlEpHvxeJU9BE3CqjoIQdacBZ+sqFPl1EUB BW15cWj5e5ZtTJHVKZnS4wc230875Xt4ah2mM1YPHaPEddmWWvzfGP38Ee7i4pMm7mWg FogNkiGRhHfxnkNtrcSjkucSFggTApR4lffiRC+i+dIc+Du6tqg6J4FIrghzoMx5S00h X/0SEQypYGhh9EamdUzNfhZ59IjhjWYX047v+wi5XlMyCSs2VkNmGdz/EQd3BsrCemnU 3pkp6i9WsGsgZFsqdKVveIhgwP3BXNNpJ5QQDda4Q/kxtno97dSKJdXj9mSH27STQVcd wA+g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e16-v6si6926861pli.337.2018.02.26.07.06.27; Mon, 26 Feb 2018 07:06:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754163AbeBZPGY (ORCPT + 28 others); Mon, 26 Feb 2018 10:06:24 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:51204 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754010AbeBZPFB (ORCPT ); Mon, 26 Feb 2018 10:05:01 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1B1EF1993; Mon, 26 Feb 2018 07:05:01 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E19193F614; Mon, 26 Feb 2018 07:05:00 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 2382D1AE53B4; Mon, 26 Feb 2018 15:05:02 +0000 (GMT) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [RFC PATCH v2 12/12] arm64: bitops: Include Date: Mon, 26 Feb 2018 15:05:00 +0000 Message-Id: <1519657500-15094-13-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1519657500-15094-1-git-send-email-will.deacon@arm.com> References: <1519657500-15094-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org asm-generic/bitops/ext2-atomic-setbit.h provides the ext2 atomic bitop definitions, so we don't need to define our own. Signed-off-by: Will Deacon --- arch/arm64/include/asm/bitops.h | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) -- 2.1.4 diff --git a/arch/arm64/include/asm/bitops.h b/arch/arm64/include/asm/bitops.h index 13501460be6b..10d536b1af74 100644 --- a/arch/arm64/include/asm/bitops.h +++ b/arch/arm64/include/asm/bitops.h @@ -38,11 +38,6 @@ #include #include #include - -/* - * Ext2 is defined to use little-endian byte ordering. - */ -#define ext2_set_bit_atomic(lock, nr, p) test_and_set_bit_le(nr, p) -#define ext2_clear_bit_atomic(lock, nr, p) test_and_clear_bit_le(nr, p) +#include #endif /* __ASM_BITOPS_H */