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[23.128.96.18]) by mx.google.com with ESMTP id d3si4858373edj.258.2021.01.15.11.31.52; Fri, 15 Jan 2021 11:31:52 -0800 (PST) Received-SPF: pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="Ec/XUrM7"; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388516AbhAOTak (ORCPT + 7 others); Fri, 15 Jan 2021 14:30:40 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:38106 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388463AbhAOTak (ORCPT ); Fri, 15 Jan 2021 14:30:40 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 10FJT14L067846; Fri, 15 Jan 2021 13:29:02 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1610738942; bh=a4WKsfBoOdvu5pp5r1p8Yye/NFAUVUGkrv5Ii2OAPJk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Ec/XUrM7KqjOW+cpjHfyQ8uV1Qr1rnpi09gQVdKEHW/Jlne6TiwwWHIheV8AhQJrI ZQl7f8kkQHHkd4xvzocBMPE462Ot+qyM5/p7IcnrVhbxojL1Gh4H3Ky18CAx8kRCg1 XC81tpSJNjApyjILk5BREQsB8W6bocaXp/0TQSyw= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 10FJT1m0025469 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 15 Jan 2021 13:29:01 -0600 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 15 Jan 2021 13:29:01 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 15 Jan 2021 13:29:01 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 10FJT0cC006836; Fri, 15 Jan 2021 13:29:01 -0600 From: Grygorii Strashko To: "David S. Miller" , , Jakub Kicinski , Peter Ujfalusi , Vignesh Raghavendra , Rob Herring CC: , Sekhar Nori , , Grygorii Strashko Subject: [net-next 1/6] dt-binding: ti: am65x-cpts: add assigned-clock and power-domains props Date: Fri, 15 Jan 2021 21:28:48 +0200 Message-ID: <20210115192853.5469-2-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210115192853.5469-1-grygorii.strashko@ti.com> References: <20210115192853.5469-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The CPTS clock is usually a clk-mux which allows to select CPTS reference clock by using 'assigned-clock-parents', 'assigned-clocks' DT properties. Also depending on integration the power-domains has to be specified to enable CPTS IP. Hence add 'assigned-clock-parents', 'assigned-clocks' and 'power-domains' properties to the CPTS DT bindings to avoid dtbs_check warnings: cpts@310d0000: 'assigned-clock-parents', 'assigned-clocks' do not match any of the regexes: 'pinctrl-[0-9]+' cpts@310d0000: 'power-domains' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Grygorii Strashko --- .../devicetree/bindings/net/ti,k3-am654-cpts.yaml | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml b/Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml index 9b7117920d90..ce43a1c58a57 100644 --- a/Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml +++ b/Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml @@ -73,6 +73,13 @@ properties: items: - const: cpts + assigned-clock-parents: true + + assigned-clocks: true + + power-domains: + maxItems: 1 + ti,cpts-ext-ts-inputs: $ref: /schemas/types.yaml#/definitions/uint32 maximum: 8 From patchwork Fri Jan 15 19:28:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 363739 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp144738jap; Fri, 15 Jan 2021 11:31:54 -0800 (PST) X-Google-Smtp-Source: ABdhPJw8E/gCSApU/aTZQ2oQpTo4gPNf3/XFR/rIWAxGKeVSTaCpLCgSH3YFCe5EjCcuzvUtR2bo X-Received: by 2002:a17:906:9588:: with SMTP id r8mr9709964ejx.148.1610739114546; Fri, 15 Jan 2021 11:31:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610739114; cv=none; d=google.com; s=arc-20160816; b=WvEmV3AJA4aidY9zFqnqkjJ+HJ32ZZacVchH+v06FmJRQAEHMIV/ikwcmrL9r5xJ+x BUQXllflE0XpvTGIxnvsiQ7y5P81I9KWW6lIq45TxA4vtNJQKepsa8vPHQekB/53zBT5 iW0udXGKl/mkEMSM+JoIyYGKhIvZl0LwBbzr+fce1AYZ/DJuSG/lwNEZwTAqPu6Hjxee X6SEhQz8jEtU9GfsIjujjCKyacSAIdQy47rpp1K4i/e7kNpfa9za+ltWq7itdWzZGsXu gny4hs9JfwbTIN9V2OOm7t4Q8u8K3LkSQfmStD8unAB+BxVarGLU15uPjw8NhEVNPM+Q lipg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=DTcsPI5R3ZBLY6K8EfeF7t+7yYHjb/L62A3vXpYnKmI=; b=SqLx0yTFOPWNnSy/sOgvPloMowkiwRJWTjZmbNO70947cZOdscC+kEqNMAaTjAHm6I SFlD/WHoYmF1nszW5yrpDzIBSKyFLP5iyp8jfbwTPrmPVvyvdHSRGlXu/yoQ+1Add/Pf de/xFir9W12qxTcKgvvTinTCyQ50lgX9KPwYBo/zZKT/MLiG9v2UMo8qkoKvCjtm77aV b4BMuT02eJ/hzcvtafoOKaKAAxCALaSM70o+SpifuTaG5gOoAxMQgVb2Q8bIYwNzJi8w e5bfr15dvMOxIumLF6n6CQC+pE4MKYsRCDCZtjTgnIofTcc6fZBT0IQXW97tMPsmMHWp EcQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FSwBWz8Z; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , , Jakub Kicinski , Peter Ujfalusi , Vignesh Raghavendra , Rob Herring CC: , Sekhar Nori , , Grygorii Strashko Subject: [net-next 2/6] dt-binding: net: ti: k3-am654-cpsw-nuss: update bindings for am64x cpsw3g Date: Fri, 15 Jan 2021 21:28:49 +0200 Message-ID: <20210115192853.5469-3-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210115192853.5469-1-grygorii.strashko@ti.com> References: <20210115192853.5469-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Update DT binding for recently introduced TI K3 AM642x SoC [1] which contains 3 port (2 external ports) CPSW3g module. The CPSW3g integrated in MAIN domain and can be configured in multi port or switch modes. The overall functionality and DT bindings are similar to other K3 CPSWxg versions, so DT binding changes are minimal: - reword description - add new compatible 'ti,am642-cpsw-nuss' - allow 2 external ports child nodes - add missed 'assigned-clock' props [1] https://www.ti.com/lit/pdf/spruim2 Signed-off-by: Grygorii Strashko --- .../bindings/net/ti,k3-am654-cpsw-nuss.yaml | 50 +++++++++++-------- 1 file changed, 30 insertions(+), 20 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml index c47b58f3e3f6..3fae9a5f0c6a 100644 --- a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml +++ b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: The TI AM654x/J721E SoC Gigabit Ethernet MAC (Media Access Controller) Device Tree Bindings +title: The TI AM654x/J721E/AM642x SoC Gigabit Ethernet MAC (Media Access Controller) Device Tree Bindings maintainers: - Grygorii Strashko @@ -13,19 +13,16 @@ maintainers: description: The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports (one external) and provides Ethernet packet communication for the device. - CPSW2G NUSS features - the Reduced Gigabit Media Independent Interface (RGMII), - Reduced Media Independent Interface (RMII), the Management Data - Input/Output (MDIO) interface for physical layer device (PHY) management, - new version of Common Platform Time Sync (CPTS), updated Address Lookup - Engine (ALE). - One external Ethernet port (port 1) with selectable RGMII/RMII interfaces and - an internal Communications Port Programming Interface (CPPI5) (Host port 0). + The TI AM642x SoC Gigabit Ethernet MAC (CPSW3G NUSS) has three ports + (two external) and provides Ethernet packet communication and switching. + + The internal Communications Port Programming Interface (CPPI5) (Host port 0). Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels - and one RX channels and operating by TI AM654x/J721E NAVSS Unified DMA - Peripheral Root Complex (UDMA-P) controller. - The CPSW2G NUSS is integrated into device MCU domain named MCU_CPSW0. + and one RX channels and operating by NAVSS Unified DMA Peripheral Root + Complex (UDMA-P) controller. - Additional features + CPSWxG features + updated Address Lookup Engine (ALE). priority level Quality Of Service (QOS) support (802.1p) Support for Audio/Video Bridging (P802.1Qav/D6.0) Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F) @@ -38,10 +35,18 @@ description: VLAN support, 802.1Q compliant, Auto add port VLAN for untagged frames on ingress, Auto VLAN removal on egress and auto pad to minimum frame size. RX/TX csum offload + Management Data Input/Output (MDIO) interface for PHYs management + RMII/RGMII Interfaces support + new version of Common Platform Time Sync (CPTS) + + The CPSWxG NUSS is integrated into + device MCU domain named MCU_CPSW0 on AM654x/J721E SoC. + device MAIN domain named CPSW0 on AM642x SoC. Specifications can be found at - http://www.ti.com/lit/ug/spruid7e/spruid7e.pdf - http://www.ti.com/lit/ug/spruil1a/spruil1a.pdf + https://www.ti.com/lit/pdf/spruid7 + https://www.ti.com/lit/zip/spruil1 + https://www.ti.com/lit/pdf/spruim2 properties: "#address-cells": true @@ -51,11 +56,12 @@ properties: oneOf: - const: ti,am654-cpsw-nuss - const: ti,j721e-cpsw-nuss + - const: ti,am642-cpsw-nuss reg: maxItems: 1 description: - The physical base address and size of full the CPSW2G NUSS IO range + The physical base address and size of full the CPSWxG NUSS IO range reg-names: items: @@ -66,12 +72,16 @@ properties: dma-coherent: true clocks: - description: CPSW2G NUSS functional clock + description: CPSWxG NUSS functional clock clock-names: items: - const: fck + assigned-clock-parents: true + + assigned-clocks: true + power-domains: maxItems: 1 @@ -99,16 +109,16 @@ properties: const: 0 patternProperties: - port@1: + port@[1-2]: type: object - description: CPSW2G NUSS external ports + description: CPSWxG NUSS external ports $ref: ethernet-controller.yaml# properties: reg: - items: - - const: 1 + minimum: 1 + maximum: 2 description: CPSW port number phys: From patchwork Fri Jan 15 19:28:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 363735 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp143518jap; Fri, 15 Jan 2021 11:30:17 -0800 (PST) X-Google-Smtp-Source: ABdhPJzVFV6Ow9k6zj3UtAk1m3Dc38rQA3LjcJxoD0gTu91lDFNo8+UxjmkyhxLoK161H3mt+g3a X-Received: by 2002:a17:906:fb9b:: with SMTP id lr27mr10348808ejb.175.1610739017244; Fri, 15 Jan 2021 11:30:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610739017; cv=none; d=google.com; s=arc-20160816; b=0KzROHp9KZo9rnyuN7QZ4Gnsf3lRBEKDb4cpAcF3ZhHnB8+yCLhkqO8BvZCHF2BD1s QveMF6shy+oWT3ykqtnNU+VodFXuMeOzsKGLh/w9clwfwCN3nLugz6iJr52vXexxGEt7 ey8oFpxxFeIoSP5anHa8huRhCmmhry/Pongp+gOFG0+v+LKTlNPV31Mpmg97B0CYId75 zKab6GGWM/Q77c0Nu/Ojf2Ad+UvqTWsDOvEWHyn88IEGRJbPBm/fX3ZzXl2iO8uHIPNS 8kaI470oTVn7ZbXtQNOUl/xHnxXMu2mHZc2cNVRoMXGj91otNT8rObEeNJHB9mOqD17+ j5WA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=YU8h/JKbEX8iab3wV0fKVymghQSmxnIshynrNKiOPt8=; b=AfpprO/H+OofLxClZlEevLj1hocvotk5gsFDCvC3oUv6RCvtkpyY8KAnRAXzwIQX5f +H5gRJdkp54y1S/2asQqz6x+qpnMm+duetU2CmP26hoBdRohLWlzre86ttv/FkqX5o5A UDg5yAQxiqpcUS0Lu1qYHT4G+LH4nABDEA44SYZ3xN29uTiNvpZ8CzpQhpw8m1FHfELv kiCyDWqe30xm+HzDfn6jwrWAe7zpZVnnVjMRCd/wq6gOSocd0sUe2NrWNyu8jZRdohW4 hHKuaYH0JfI6J6c9fpQkISx1mYmMv5q480yACDaEOEVOuJUvhV1j+XGhI/OBUYfknifU GqKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=k7zMEuAY; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , , Jakub Kicinski , Peter Ujfalusi , Vignesh Raghavendra , Rob Herring CC: , Sekhar Nori , , Grygorii Strashko Subject: [net-next 4/6] net: ethernet: ti: am65-cpsw-nuss: Support for transparent ASEL handling Date: Fri, 15 Jan 2021 21:28:51 +0200 Message-ID: <20210115192853.5469-5-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210115192853.5469-1-grygorii.strashko@ti.com> References: <20210115192853.5469-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Peter Ujfalusi Use the glue layer's functions to convert the dma_addr_t to and from CPPI5 address (with the ASEL bits), which should be used within the descriptors and data buffers. - Per channel coherency support The DMAs use the 'ASEL' bits to select data and configuration fetch path. The ASEL bits are placed at the unused parts of any address field used by the DMAs (pointers to descriptors, addresses in descriptors, ring base addresses). The ASEL is not part of the address (the DMAs can address 48bits). Individual channels can be configured to be coherent (via ACP port) or non coherent individually by configuring the ASEL to appropriate value. [1] https://lore.kernel.org/patchwork/cover/1350756/ Signed-off-by: Peter Ujfalusi Co-developed-by: Vignesh Raghavendra Signed-off-by: Vignesh Raghavendra Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/am65-cpsw-nuss.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.17.1 diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c index 8bf48cf3be9b..d060744dd0b2 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -376,6 +376,7 @@ static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common, cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, AM65_CPSW_NAV_PS_DATA_SIZE); + k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma); cppi5_hdesc_attach_buf(desc_rx, buf_dma, skb_tailroom(skb), buf_dma, skb_tailroom(skb)); swdata = cppi5_hdesc_get_swdata(desc_rx); *((void **)swdata) = skb; @@ -692,6 +693,7 @@ static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma) swdata = cppi5_hdesc_get_swdata(desc_rx); skb = *swdata; cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); + k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); @@ -780,6 +782,7 @@ static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, swdata = cppi5_hdesc_get_swdata(desc_rx); skb = *swdata; cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); + k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); pkt_len = cppi5_hdesc_get_pktlen(desc_rx); cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); dev_dbg(dev, "%s rx port_id:%d\n", __func__, port_id); @@ -875,19 +878,23 @@ static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn, next_desc = first_desc; cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); + k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, DMA_TO_DEVICE); next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); + k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); while (next_desc_dma) { next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, next_desc_dma); cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); + k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len, DMA_TO_DEVICE); next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); + k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); } @@ -1140,6 +1147,7 @@ static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb, cppi5_hdesc_set_pkttype(first_desc, 0x7); cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id); + k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); swdata = cppi5_hdesc_get_swdata(first_desc); *(swdata) = skb; @@ -1185,11 +1193,13 @@ static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb, } cppi5_hdesc_reset_hbdesc(next_desc); + k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); cppi5_hdesc_attach_buf(next_desc, buf_dma, frag_size, buf_dma, frag_size); desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, next_desc); + k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma); cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); pkt_len += frag_size; From patchwork Fri Jan 15 19:28:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 363740 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp144759jap; Fri, 15 Jan 2021 11:31:56 -0800 (PST) X-Google-Smtp-Source: ABdhPJw2K+lk3sJKZ5oqpQTV0GUjqUGEGXnnnSm2sAmhYt/gZHuJf8p8O93XgWLNQHeam2W7nIjQ X-Received: by 2002:a05:6402:407:: with SMTP id q7mr10939791edv.312.1610739115950; Fri, 15 Jan 2021 11:31:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610739115; cv=none; d=google.com; s=arc-20160816; b=NW3BTKZlKBAUYkLXa10CiUNaclp8U1FAjYodJSKGJUnrnSSThd97kQEL+xPrx3DklU NjsDIvySD4zycQP2nktPyWQYt1HoCUtYugy9eLCJNhhAo0st8XOikHEEp4wUVfcMJ48p NTMhqNNPVYBaSo5YDK/H8ozE9MeMbtVTVGqvbpyZlNr+tON6xbSNA1dayj4Sch2K8Sna 2+Ji9kzVM1TrAsYfrcJQXN4iDUA5jkOMwcUTf/W18oKY2STVlmu2peBit0pNigBZGRSr VYoWdu2Hdpx3S5BGwgu6WIjlfzQO692wqBNfscN19lSxWB75cFAdKsFNUiKVrjSeCYdQ z/NA== ARC-Message-Signature: i=1; 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Miller" , , Jakub Kicinski , Peter Ujfalusi , Vignesh Raghavendra , Rob Herring CC: , Sekhar Nori , , Grygorii Strashko Subject: [net-next 5/6] net: ti: cpsw_ale: add driver data for AM64 CPSW3g Date: Fri, 15 Jan 2021 21:28:52 +0200 Message-ID: <20210115192853.5469-6-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210115192853.5469-1-grygorii.strashko@ti.com> References: <20210115192853.5469-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Vignesh Raghavendra The AM642x CPSW3g is similar to j721e-cpswxg except its ALE table size is 512 entries. Add entry for the same. Signed-off-by: Vignesh Raghavendra Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/cpsw_ale.c | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.17.1 diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index cdc308a2aa3e..d828f856237a 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -1256,6 +1256,13 @@ static const struct cpsw_ale_dev_id cpsw_ale_id_match[] = { .major_ver_mask = 0x7, .vlan_entry_tbl = vlan_entry_k3_cpswxg, }, + { + .dev_id = "am64-cpswxg", + .features = CPSW_ALE_F_STATUS_REG | CPSW_ALE_F_HW_AUTOAGING, + .major_ver_mask = 0x7, + .vlan_entry_tbl = vlan_entry_k3_cpswxg, + .tbl_entries = 512, + }, { }, }; From patchwork Fri Jan 15 19:28:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 363736 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp143534jap; Fri, 15 Jan 2021 11:30:19 -0800 (PST) X-Google-Smtp-Source: ABdhPJxDmdBgXCxfg1nHhM3GPEkG6lcyn6na55rn0Y664arelDPxu3dx7EMEF6Nz39Q2jLxiQBAb X-Received: by 2002:a17:907:214d:: with SMTP id rk13mr10292737ejb.501.1610739018753; Fri, 15 Jan 2021 11:30:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610739018; cv=none; d=google.com; s=arc-20160816; b=hBnUgJ/x+sCyhW5mtVRcR6MvKIKlr6N2kCOSH5xi13/m7Sqv8cZ4zWFIa5kJDsvPhr /+0KgQZB4/C+FTJ4PPddqQHMCNkR/e5dbMYmXq1iYF+FurHP/zj1twPQv7axY3Prg5gb LI3y/Lged9EY9SjOcyEbIg7DcQ5C9GMmd3TGl3TTcDFALb+fGmG4DFJgnE/4Bt6I128r 1dRkyaEuLa43eDi43bWdVBk4SMSinmU1ej+U0Z0QaNMd0PCcuM8XnorP7SeUPHtGggPw vYmUVUCC4unGA9vARTucrmQpeZmOc/17TTE0d1IjSsgDu3/VAPvAiwV3Q6pa9vwTVxQw CcHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=RVk08ZYJ9d6t9cvlnZCVuB1ibN+rBkiw/DHXFibDelI=; b=MqNj6VZARLZe/r7sDzM0IzTL3ipJrybGz66gP56rz7Ij71OQzQ511ISYIo2b0iR41a 0n0ixGFMW26NFs/Gif37DbaGe26ROPIt3jxuXxCaD6+KfC/tyJTQa6KkZRcIEC5FH773 GpRnppsDWdrCYGvdrKLj7iwru13GTXH2+92z1y9fitqK5N+JY+1h24YYVhQmxf7oI2QW lhQaJz6Igl6Wb+/Rz6mtXoBKD5GgiWK6+P6mxOmNgDBBwSd3eU51Q/RX5VaSO4e6uHLN eGX334HR8KDTwJ9VH6z3WmRplzlWAjeqe0xuKeBYDRFn1/wGUhxqCUlbQAwy4BI7edbj I3QQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=sZXyARS2; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , , Jakub Kicinski , Peter Ujfalusi , Vignesh Raghavendra , Rob Herring CC: , Sekhar Nori , , Grygorii Strashko Subject: [net-next 6/6] net: ethernet: ti: am65-cpsw: add support for am64x cpsw3g Date: Fri, 15 Jan 2021 21:28:53 +0200 Message-ID: <20210115192853.5469-7-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210115192853.5469-1-grygorii.strashko@ti.com> References: <20210115192853.5469-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Vignesh Raghavendra The TI AM64x SoCs Gigabit Ethernet Switch subsystem (CPSW3g NUSS) has three ports (2 ext. ports) and provides Ethernet packet communication for the device and can be configured in multi port mode or as an Ethernet switch. This patch adds support for the corresponding CPSW3g version. Signed-off-by: Vignesh Raghavendra Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/am65-cpsw-nuss.c | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.17.1 diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c index d060744dd0b2..1850743c04da 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -2115,9 +2115,16 @@ static const struct am65_cpsw_pdata j721e_pdata = { .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, }; +static const struct am65_cpsw_pdata am64x_cpswxg_pdata = { + .quirks = 0, + .ale_dev_id = "am64-cpswxg", + .fdqring_mode = K3_RINGACC_RING_MODE_RING, +}; + static const struct of_device_id am65_cpsw_nuss_of_mtable[] = { { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0}, { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata}, + { .compatible = "ti,am642-cpsw-nuss", .data = &am64x_cpswxg_pdata}, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable);