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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b3sm10353807wrn.70.2021.01.15.12.12.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 12:12:09 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 01/11] hw/m68k/next-cube: Make next_irq() function static Date: Fri, 15 Jan 2021 20:11:56 +0000 Message-Id: <20210115201206.17347-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210115201206.17347-1-peter.maydell@linaro.org> References: <20210115201206.17347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The next_irq() function is global, but isn't actually used anywhere outside next-cube.c. Make it static. Signed-off-by: Peter Maydell --- include/hw/m68k/next-cube.h | 2 -- hw/m68k/next-cube.c | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) -- 2.20.1 Reviewed-by: Thomas Huth diff --git a/include/hw/m68k/next-cube.h b/include/hw/m68k/next-cube.h index a3be2b32abb..5a56c354b8e 100644 --- a/include/hw/m68k/next-cube.h +++ b/include/hw/m68k/next-cube.h @@ -42,6 +42,4 @@ enum next_irqs { NEXT_SND_I }; -void next_irq(void *opaque, int number, int level); - #endif /* NEXT_CUBE_H */ diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c index 37bc35dfa43..f622d6589c8 100644 --- a/hw/m68k/next-cube.c +++ b/hw/m68k/next-cube.c @@ -724,7 +724,7 @@ static const MemoryRegionOps dma_ops = { * TODO: set the shift numbers as values in the enum, so the first switch * will not be needed */ -void next_irq(void *opaque, int number, int level) +static void next_irq(void *opaque, int number, int level) { M68kCPU *cpu = opaque; int shift = 0; From patchwork Fri Jan 15 20:11:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 363757 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp173769jap; Fri, 15 Jan 2021 12:15:49 -0800 (PST) X-Google-Smtp-Source: ABdhPJzT8FCaJnarX0s3qSkjWiP6ouJEyvQNhwowD/JZJlVIybW5Pqo2fAh4ulba4oUCHGyZMznx X-Received: by 2002:a25:3801:: with SMTP id f1mr20888365yba.321.1610741749659; Fri, 15 Jan 2021 12:15:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610741749; cv=none; d=google.com; s=arc-20160816; b=US6BoDJ24DPHQMISL38GvQK8St+v/5HhpJ0kRnZmmk5TEkOb3OepWs3b82zRNvVcjK ZVOOCjFtVaeSCeCniQuo/y/n3gdqqI0qdnZseM4m5Dbw+D2NLyx91fiqvLvKUTnfp1uv CN65+vNT3muNTdDSOedJFo4C8NwpqM68iIw/oREQdedpOciT1v/k+r0j0DfvumkwapvJ ncBYm9m4f5nMD9EcnnrtbuFu3R9UqVFjw29Wjqz/U5P+6qL0cNxWsjAxGRE4lKbVgZ7H 0JTO2+CVGqVsoNS3ee6QpwOqcMqwlkHJrRg63AeAjz1UDGrxO0V8dHka00l/Pyx6j2e1 SltA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rTWJIJzyn/d0f9c+f8XIvnchNfg5WqrGoOxuJbOhu5Q=; b=WNeYLY0ssfKC5n9enX0ZIZge5XGOztVd0391Sw9z8Hsr1crlJs7OnLfPIavVfSt1DY 0JiS01WyP0G6/PY7yac+Q84haxg/DKFojPzhUybmFKNNsS63B72+nKS12N/SpCqv/QXy m4NFMNY8JWMzuBF/q3xcTNWnCsYfko9oVTGcd487A+yYO4KdEH39wgVUfsblJ8FFDPeV TS+tVMuGkirhT1IL9XWPnuJwHzmoG2aeP3Y6GJjZOxvoOJS7vyQXFkLHJHchvLfa6XgU +BEbzPZQrhvDCHdr9/dHKsi9/FhfX6DemuArE9T4kRAGVWNsPtc8ls9AZsUofQiNoqp8 4H7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=D0uQ59eX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b3sm10353807wrn.70.2021.01.15.12.12.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 12:12:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 02/11] hw/m68k/next-cube: Move register/interrupt functionality into a device Date: Fri, 15 Jan 2021 20:11:57 +0000 Message-Id: <20210115201206.17347-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210115201206.17347-1-peter.maydell@linaro.org> References: <20210115201206.17347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently the next-cube board code open-codes a lot of handling of interrupts and some miscellaneous registers. Move this into a proper QOM device. In the real hardware this functionality seems to be the responsibility of the Peripheral Controller (PC) chip, so name the device that. There are several different things that will need to be moved into this device: * the mmio_iops register set * the scr_ops register set * the next_irq IRQ handling To ease review, we structure the change as a sequence of commits: in this first commit we create the skeleton of the NeXTPC device with no content, but with a backdoor pointer to the NeXTState machine's state struct so we can move parts of the code and still have refactored and non-refactored code using the same struct data fields. Further commits will move functionality into the new device piece by piece. At the end we will be able to remove the backdoor pointer because all the data fields will be in the NeXTPC struct and not the NeXTState struct. We'll add the VMState for the new device at the end of all that; this is in theory a migration compatibility break but this machine does not currently support migration at all anyway. Signed-off-by: Peter Maydell --- hw/m68k/next-cube.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) -- 2.20.1 diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c index f622d6589c8..dccf3eb4313 100644 --- a/hw/m68k/next-cube.c +++ b/hw/m68k/next-cube.c @@ -90,6 +90,16 @@ struct NeXTState { NextRtc rtc; }; +#define TYPE_NEXT_PC "next-pc" +OBJECT_DECLARE_SIMPLE_TYPE(NeXTPC, NEXT_PC) + +struct NeXTPC { + SysBusDevice parent_obj; + + /* Temporary until all functionality has been moved into this device */ + NeXTState *ns; +}; + /* Thanks to NeXT forums for this */ /* static const uint8_t rtc_ram3[32] = { @@ -857,6 +867,31 @@ static void next_escc_init(M68kCPU *cpu) sysbus_mmio_map(s, 0, 0x2118000); } +static void next_pc_reset(DeviceState *dev) +{ +} + +static void next_pc_realize(DeviceState *dev, Error **errp) +{ +} + +static void next_pc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->desc = "NeXT Peripheral Controller"; + dc->realize = next_pc_realize; + dc->reset = next_pc_reset; + /* We will add the VMState in a later commit */ +} + +static const TypeInfo next_pc_info = { + .name = TYPE_NEXT_PC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(NeXTPC), + .class_init = next_pc_class_init, +}; + static void next_cube_init(MachineState *machine) { M68kCPU *cpu; @@ -871,6 +906,7 @@ static void next_cube_init(MachineState *machine) const char *bios_name = machine->firmware ?: ROM_FILE; NeXTState *ns = NEXT_MACHINE(machine); DeviceState *dev; + DeviceState *pcdev; /* Initialize the cpu core */ cpu = M68K_CPU(cpu_create(machine->cpu_type)); @@ -884,6 +920,12 @@ static void next_cube_init(MachineState *machine) env->vbr = 0; env->sr = 0x2700; + /* Peripheral Controller */ + pcdev = qdev_new(TYPE_NEXT_PC); + sysbus_realize_and_unref(SYS_BUS_DEVICE(pcdev), &error_fatal); + /* Temporary while we refactor this code */ + NEXT_PC(pcdev)->ns = ns; + /* Set internal registers to initial values */ /* 0x0000XX00 << vital bits */ ns->scr1 = 0x00011102; @@ -978,6 +1020,7 @@ static const TypeInfo next_typeinfo = { static void next_register_type(void) { type_register_static(&next_typeinfo); + type_register_static(&next_pc_info); } type_init(next_register_type) From patchwork Fri Jan 15 20:11:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 363759 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp174808jap; Fri, 15 Jan 2021 12:17:29 -0800 (PST) X-Google-Smtp-Source: ABdhPJyTixCrsCJauDKaY9EH3gfa1SYWVacMS8z8FeZ02JhQ8zEOoXp0Qp5ZEdP9FGZ8adBc/WoI X-Received: by 2002:a25:bc51:: with SMTP id d17mr8159519ybk.72.1610741849623; Fri, 15 Jan 2021 12:17:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610741849; cv=none; d=google.com; s=arc-20160816; b=edzUYNmAQmCFXf9fKF1kEtEhKZ5+LaVF8J4lhkIPdE8UWmUO+FDuAUwVtnFRlCjWH3 io2tmTmbUBaBHRjVEs0CbMhViLxbsafbkrisYwy2jNw+35JH7YZrna12Ve+hwSWCG3lr m/oljGuuenotOeIqF6VXX8I/3qCIkYKlyrGPNjYbpZjNOnp276tRXfx63kgDd+O6tECr ax75Zipqlow3aO3iU6Z6UmuFCdaihd8cbYygyM20UpidfCCF1Pb4RZEaglXPc1tIDrY7 MUUcVMixYc/WvYvSOMwFrxpeKpey7yzm8MMpHcMaP3GR4qWz55/7qdetIdCgbWluRCCr TPvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=UNbBc4SXLU0U2IV+7GjuHGXmjGUHTU+KZlWo4uGsEzI=; b=b6dNlSGpWAYoVJwjHdF6DOedh6HySSVdvkIkx1EnP0yNSyqr58OmEVDxn2va6S2Hke yrcyBK5TFCciYUp64K1aUbJ77wwDuforaMm2tkHFS1edSX7eNxkVfxTB9Lx4d6pun5QO dNzD4NBTvyDgRNLsN28DlhJMrlHiCogPxY7zLpDzJG1/ScTQv2dznrPsAMKFMCS9ETre bBAT5elBgvc4+3nPghS8bzlXwUOs8LzKyQs0Q4dzoYrGPJpvtjcEWOHAInraevfjkEjC 1pZxzkyPWeHieDY0FamDBPQJQgt9j0WGELtcbm1m2OhaBQOjk1w6I7lIrumXIhvB9TYU PKUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="OLudL/tl"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b3sm10353807wrn.70.2021.01.15.12.12.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 12:12:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 03/11] hw/m68k/next-cube: Move mmio_ops into NeXTPC device Date: Fri, 15 Jan 2021 20:11:58 +0000 Message-Id: <20210115201206.17347-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210115201206.17347-1-peter.maydell@linaro.org> References: <20210115201206.17347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the registers handled by the mmio_ops struct into the NeXTPC device. This allows us to also move the scr1 and scr2 data fields. Signed-off-by: Peter Maydell --- hw/m68k/next-cube.c | 80 +++++++++++++++++++++++++-------------------- 1 file changed, 44 insertions(+), 36 deletions(-) -- 2.20.1 Reviewed-by: Thomas Huth diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c index dccf3eb4313..ff121143e92 100644 --- a/hw/m68k/next-cube.c +++ b/hw/m68k/next-cube.c @@ -84,9 +84,6 @@ struct NeXTState { qemu_irq scsi_reset; qemu_irq *fd_irq; - uint32_t scr1; - uint32_t scr2; - NextRtc rtc; }; @@ -98,6 +95,11 @@ struct NeXTPC { /* Temporary until all functionality has been moved into this device */ NeXTState *ns; + + MemoryRegion mmiomem; + + uint32_t scr1; + uint32_t scr2; }; /* Thanks to NeXT forums for this */ @@ -120,13 +122,13 @@ static const uint8_t rtc_ram2[32] = { #define SCR2_RTDATA 0x4 #define SCR2_TOBCD(x) (((x / 10) << 4) + (x % 10)) -static void nextscr2_write(NeXTState *s, uint32_t val, int size) +static void nextscr2_write(NeXTPC *s, uint32_t val, int size) { static int led; static int phase; static uint8_t old_scr2; uint8_t scr2_2; - NextRtc *rtc = &s->rtc; + NextRtc *rtc = &s->ns->rtc; if (size == 4) { scr2_2 = (val >> 8) & 0xFF; @@ -238,7 +240,7 @@ static void nextscr2_write(NeXTState *s, uint32_t val, int size) /* clear FTU */ if (rtc->value & 0x04) { rtc->status = rtc->status & (~0x18); - s->int_status = s->int_status & (~0x04); + s->ns->int_status = s->ns->int_status & (~0x04); } } } @@ -254,7 +256,7 @@ static void nextscr2_write(NeXTState *s, uint32_t val, int size) old_scr2 = scr2_2; } -static uint32_t mmio_readb(NeXTState *s, hwaddr addr) +static uint32_t mmio_readb(NeXTPC *s, hwaddr addr) { switch (addr) { case 0xc000: @@ -284,7 +286,7 @@ static uint32_t mmio_readb(NeXTState *s, hwaddr addr) } } -static uint32_t mmio_readw(NeXTState *s, hwaddr addr) +static uint32_t mmio_readw(NeXTPC *s, hwaddr addr) { switch (addr) { default: @@ -293,16 +295,16 @@ static uint32_t mmio_readw(NeXTState *s, hwaddr addr) } } -static uint32_t mmio_readl(NeXTState *s, hwaddr addr) +static uint32_t mmio_readl(NeXTPC *s, hwaddr addr) { switch (addr) { case 0x7000: - /* DPRINTF("Read INT status: %x\n", s->int_status); */ - return s->int_status; + /* DPRINTF("Read INT status: %x\n", s->ns->int_status); */ + return s->ns->int_status; case 0x7800: - DPRINTF("MMIO Read INT mask: %x\n", s->int_mask); - return s->int_mask; + DPRINTF("MMIO Read INT mask: %x\n", s->ns->int_mask); + return s->ns->int_mask; case 0xc000: return s->scr1; @@ -316,7 +318,7 @@ static uint32_t mmio_readl(NeXTState *s, hwaddr addr) } } -static void mmio_writeb(NeXTState *s, hwaddr addr, uint32_t val) +static void mmio_writeb(NeXTPC *s, hwaddr addr, uint32_t val) { switch (addr) { case 0xd003: @@ -328,21 +330,21 @@ static void mmio_writeb(NeXTState *s, hwaddr addr, uint32_t val) } -static void mmio_writew(NeXTState *s, hwaddr addr, uint32_t val) +static void mmio_writew(NeXTPC *s, hwaddr addr, uint32_t val) { DPRINTF("MMIO Write W\n"); } -static void mmio_writel(NeXTState *s, hwaddr addr, uint32_t val) +static void mmio_writel(NeXTPC *s, hwaddr addr, uint32_t val) { switch (addr) { case 0x7000: - DPRINTF("INT Status old: %x new: %x\n", s->int_status, val); - s->int_status = val; + DPRINTF("INT Status old: %x new: %x\n", s->ns->int_status, val); + s->ns->int_status = val; break; case 0x7800: - DPRINTF("INT Mask old: %x new: %x\n", s->int_mask, val); - s->int_mask = val; + DPRINTF("INT Mask old: %x new: %x\n", s->ns->int_mask, val); + s->ns->int_mask = val; break; case 0xc000: DPRINTF("SCR1 Write: %x\n", val); @@ -358,15 +360,15 @@ static void mmio_writel(NeXTState *s, hwaddr addr, uint32_t val) static uint64_t mmio_readfn(void *opaque, hwaddr addr, unsigned size) { - NeXTState *ns = NEXT_MACHINE(opaque); + NeXTPC *s = NEXT_PC(opaque); switch (size) { case 1: - return mmio_readb(ns, addr); + return mmio_readb(s, addr); case 2: - return mmio_readw(ns, addr); + return mmio_readw(s, addr); case 4: - return mmio_readl(ns, addr); + return mmio_readl(s, addr); default: g_assert_not_reached(); } @@ -375,17 +377,17 @@ static uint64_t mmio_readfn(void *opaque, hwaddr addr, unsigned size) static void mmio_writefn(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - NeXTState *ns = NEXT_MACHINE(opaque); + NeXTPC *s = NEXT_PC(opaque); switch (size) { case 1: - mmio_writeb(ns, addr, value); + mmio_writeb(s, addr, value); break; case 2: - mmio_writew(ns, addr, value); + mmio_writew(s, addr, value); break; case 4: - mmio_writel(ns, addr, value); + mmio_writel(s, addr, value); break; default: g_assert_not_reached(); @@ -869,10 +871,23 @@ static void next_escc_init(M68kCPU *cpu) static void next_pc_reset(DeviceState *dev) { + NeXTPC *s = NEXT_PC(dev); + + /* Set internal registers to initial values */ + /* 0x0000XX00 << vital bits */ + s->scr1 = 0x00011102; + s->scr2 = 0x00ff0c80; } static void next_pc_realize(DeviceState *dev, Error **errp) { + NeXTPC *s = NEXT_PC(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + + memory_region_init_io(&s->mmiomem, OBJECT(s), &mmio_ops, s, + "next.mmio", 0xD0000); + + sysbus_init_mmio(sbd, &s->mmiomem); } static void next_pc_class_init(ObjectClass *klass, void *data) @@ -897,7 +912,6 @@ static void next_cube_init(MachineState *machine) M68kCPU *cpu; CPUM68KState *env; MemoryRegion *rom = g_new(MemoryRegion, 1); - MemoryRegion *mmiomem = g_new(MemoryRegion, 1); MemoryRegion *scrmem = g_new(MemoryRegion, 1); MemoryRegion *dmamem = g_new(MemoryRegion, 1); MemoryRegion *bmapm1 = g_new(MemoryRegion, 1); @@ -926,10 +940,6 @@ static void next_cube_init(MachineState *machine) /* Temporary while we refactor this code */ NEXT_PC(pcdev)->ns = ns; - /* Set internal registers to initial values */ - /* 0x0000XX00 << vital bits */ - ns->scr1 = 0x00011102; - ns->scr2 = 0x00ff0c80; ns->rtc.status = 0x90; /* Load RTC RAM - TODO: provide possibility to load contents from file */ @@ -944,9 +954,7 @@ static void next_cube_init(MachineState *machine) sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x0B000000); /* MMIO */ - memory_region_init_io(mmiomem, NULL, &mmio_ops, machine, "next.mmio", - 0xD0000); - memory_region_add_subregion(sysmem, 0x02000000, mmiomem); + sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 0, 0x02000000); /* BMAP memory */ memory_region_init_ram_shared_nomigrate(bmapm1, NULL, "next.bmapmem", 64, From patchwork Fri Jan 15 20:11:59 2021 Content-Type: text/plain; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b3sm10353807wrn.70.2021.01.15.12.12.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 12:12:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 04/11] hw/m68k/next-cube: Move scr_ops into NeXTPC device Date: Fri, 15 Jan 2021 20:11:59 +0000 Message-Id: <20210115201206.17347-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210115201206.17347-1-peter.maydell@linaro.org> References: <20210115201206.17347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the registers handled by the scr_ops struct into the NeXTPC device. Signed-off-by: Peter Maydell --- hw/m68k/next-cube.c | 50 ++++++++++++++++++++++----------------------- 1 file changed, 25 insertions(+), 25 deletions(-) -- 2.20.1 Reviewed-by: Thomas Huth diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c index ff121143e92..f5575cb43b8 100644 --- a/hw/m68k/next-cube.c +++ b/hw/m68k/next-cube.c @@ -76,8 +76,6 @@ struct NeXTState { uint32_t int_mask; uint32_t int_status; - uint8_t scsi_csr_1; - uint8_t scsi_csr_2; next_dma dma[10]; qemu_irq *scsi_irq; qemu_irq scsi_dma; @@ -97,9 +95,12 @@ struct NeXTPC { NeXTState *ns; MemoryRegion mmiomem; + MemoryRegion scrmem; uint32_t scr1; uint32_t scr2; + uint8_t scsi_csr_1; + uint8_t scsi_csr_2; }; /* Thanks to NeXT forums for this */ @@ -402,7 +403,7 @@ static const MemoryRegionOps mmio_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static uint32_t scr_readb(NeXTState *s, hwaddr addr) +static uint32_t scr_readb(NeXTPC *s, hwaddr addr) { switch (addr) { case 0x14108: @@ -436,13 +437,13 @@ static uint32_t scr_readb(NeXTState *s, hwaddr addr) } } -static uint32_t scr_readw(NeXTState *s, hwaddr addr) +static uint32_t scr_readw(NeXTPC *s, hwaddr addr) { DPRINTF("BMAP Read W @ %x\n", (unsigned int)addr); return 0; } -static uint32_t scr_readl(NeXTState *s, hwaddr addr) +static uint32_t scr_readl(NeXTPC *s, hwaddr addr) { DPRINTF("BMAP Read L @ %x\n", (unsigned int)addr); return 0; @@ -455,7 +456,7 @@ static uint32_t scr_readl(NeXTState *s, hwaddr addr) #define SCSICSR_CPUDMA 0x10 /* if set, dma enabled */ #define SCSICSR_INTMASK 0x20 /* if set, interrupt enabled */ -static void scr_writeb(NeXTState *s, hwaddr addr, uint32_t value) +static void scr_writeb(NeXTPC *s, hwaddr addr, uint32_t value) { switch (addr) { case 0x14108: @@ -501,9 +502,9 @@ static void scr_writeb(NeXTState *s, hwaddr addr, uint32_t value) DPRINTF("SCSICSR CPUDMA\n"); /* qemu_irq_raise(s->scsi_dma); */ - s->int_status |= 0x4000000; + s->ns->int_status |= 0x4000000; } else { - s->int_status &= ~(0x4000000); + s->ns->int_status &= ~(0x4000000); } if (value & SCSICSR_INTMASK) { DPRINTF("SCSICSR INTMASK\n"); @@ -533,27 +534,27 @@ static void scr_writeb(NeXTState *s, hwaddr addr, uint32_t value) } } -static void scr_writew(NeXTState *s, hwaddr addr, uint32_t value) +static void scr_writew(NeXTPC *s, hwaddr addr, uint32_t value) { DPRINTF("BMAP Write W @ %x with %x\n", (unsigned int)addr, value); } -static void scr_writel(NeXTState *s, hwaddr addr, uint32_t value) +static void scr_writel(NeXTPC *s, hwaddr addr, uint32_t value) { DPRINTF("BMAP Write L @ %x with %x\n", (unsigned int)addr, value); } static uint64_t scr_readfn(void *opaque, hwaddr addr, unsigned size) { - NeXTState *ns = NEXT_MACHINE(opaque); + NeXTPC *s = NEXT_PC(opaque); switch (size) { case 1: - return scr_readb(ns, addr); + return scr_readb(s, addr); case 2: - return scr_readw(ns, addr); + return scr_readw(s, addr); case 4: - return scr_readl(ns, addr); + return scr_readl(s, addr); default: g_assert_not_reached(); } @@ -562,17 +563,17 @@ static uint64_t scr_readfn(void *opaque, hwaddr addr, unsigned size) static void scr_writefn(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - NeXTState *ns = NEXT_MACHINE(opaque); + NeXTPC *s = NEXT_PC(opaque); switch (size) { case 1: - scr_writeb(ns, addr, value); + scr_writeb(s, addr, value); break; case 2: - scr_writew(ns, addr, value); + scr_writew(s, addr, value); break; case 4: - scr_writel(ns, addr, value); + scr_writel(s, addr, value); break; default: g_assert_not_reached(); @@ -886,8 +887,10 @@ static void next_pc_realize(DeviceState *dev, Error **errp) memory_region_init_io(&s->mmiomem, OBJECT(s), &mmio_ops, s, "next.mmio", 0xD0000); - + memory_region_init_io(&s->scrmem, OBJECT(s), &scr_ops, s, + "next.scr", 0x20000); sysbus_init_mmio(sbd, &s->mmiomem); + sysbus_init_mmio(sbd, &s->scrmem); } static void next_pc_class_init(ObjectClass *klass, void *data) @@ -912,7 +915,6 @@ static void next_cube_init(MachineState *machine) M68kCPU *cpu; CPUM68KState *env; MemoryRegion *rom = g_new(MemoryRegion, 1); - MemoryRegion *scrmem = g_new(MemoryRegion, 1); MemoryRegion *dmamem = g_new(MemoryRegion, 1); MemoryRegion *bmapm1 = g_new(MemoryRegion, 1); MemoryRegion *bmapm2 = g_new(MemoryRegion, 1); @@ -956,6 +958,9 @@ static void next_cube_init(MachineState *machine) /* MMIO */ sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 0, 0x02000000); + /* BMAP IO - acts as a catch-all for now */ + sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02100000); + /* BMAP memory */ memory_region_init_ram_shared_nomigrate(bmapm1, NULL, "next.bmapmem", 64, true, &error_fatal); @@ -964,11 +969,6 @@ static void next_cube_init(MachineState *machine) memory_region_init_alias(bmapm2, NULL, "next.bmapmem2", bmapm1, 0x0, 64); memory_region_add_subregion(sysmem, 0x820c0000, bmapm2); - /* BMAP IO - acts as a catch-all for now */ - memory_region_init_io(scrmem, NULL, &scr_ops, machine, "next.scr", - 0x20000); - memory_region_add_subregion(sysmem, 0x02100000, scrmem); - /* KBD */ dev = qdev_new(TYPE_NEXTKBD); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); From patchwork Fri Jan 15 20:12:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 363760 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp175052jap; Fri, 15 Jan 2021 12:17:55 -0800 (PST) X-Google-Smtp-Source: ABdhPJxk4L8/lZlEg82S/9icRNNoH/zs9zv15G7Kdnyvprp4RCP7o7WBcXRbqYBGnur+vWXf51p1 X-Received: by 2002:a25:cf03:: with SMTP id f3mr21603740ybg.216.1610741875037; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b3sm10353807wrn.70.2021.01.15.12.12.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 12:12:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 05/11] hw/m68k/next-cube: Make next_irq take NeXTPC* as its opaque Date: Fri, 15 Jan 2021 20:12:00 +0000 Message-Id: <20210115201206.17347-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210115201206.17347-1-peter.maydell@linaro.org> References: <20210115201206.17347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Make the next_irq function take a NeXTPC* as its opaque rather than the M68kCPU*. This will make it simpler to turn the next_irq function into a gpio input line of the NeXTPC device in the next commit. For this to work we have to pass the CPU to the NeXTPC device via a link property, in the same way we do in q800.c (and for the same reason). Signed-off-by: Peter Maydell --- hw/m68k/next-cube.c | 31 +++++++++++++++++++++++-------- 1 file changed, 23 insertions(+), 8 deletions(-) -- 2.20.1 Reviewed-by: Thomas Huth diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c index f5575cb43b8..a9e57304e04 100644 --- a/hw/m68k/next-cube.c +++ b/hw/m68k/next-cube.c @@ -94,6 +94,8 @@ struct NeXTPC { /* Temporary until all functionality has been moved into this device */ NeXTState *ns; + M68kCPU *cpu; + MemoryRegion mmiomem; MemoryRegion scrmem; @@ -739,9 +741,9 @@ static const MemoryRegionOps dma_ops = { */ static void next_irq(void *opaque, int number, int level) { - M68kCPU *cpu = opaque; + NeXTPC *s = NEXT_PC(opaque); + M68kCPU *cpu = s->cpu; int shift = 0; - NeXTState *ns = NEXT_MACHINE(qdev_get_machine()); /* first switch sets interupt status */ /* DPRINTF("IRQ %i\n",number); */ @@ -796,14 +798,14 @@ static void next_irq(void *opaque, int number, int level) * this HAS to be wrong, the interrupt handlers in mach and together * int_status and int_mask and return if there is a hit */ - if (ns->int_mask & (1 << shift)) { + if (s->ns->int_mask & (1 << shift)) { DPRINTF("%x interrupt masked @ %x\n", 1 << shift, cpu->env.pc); /* return; */ } /* second switch triggers the correct interrupt */ if (level) { - ns->int_status |= 1 << shift; + s->ns->int_status |= 1 << shift; switch (number) { /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ @@ -832,7 +834,7 @@ static void next_irq(void *opaque, int number, int level) break; } } else { - ns->int_status &= ~(1 << shift); + s->ns->int_status &= ~(1 << shift); cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); } } @@ -847,9 +849,9 @@ static void next_serial_irq(void *opaque, int n, int level) } } -static void next_escc_init(M68kCPU *cpu) +static void next_escc_init(DeviceState *pcdev) { - qemu_irq *ser_irq = qemu_allocate_irqs(next_serial_irq, cpu, 2); + qemu_irq *ser_irq = qemu_allocate_irqs(next_serial_irq, pcdev, 2); DeviceState *dev; SysBusDevice *s; @@ -893,6 +895,17 @@ static void next_pc_realize(DeviceState *dev, Error **errp) sysbus_init_mmio(sbd, &s->scrmem); } +/* + * If the m68k CPU implemented its inbound irq lines as GPIO lines + * rather than via the m68k_set_irq_level() function we would not need + * this cpu link property and could instead provide outbound IRQ lines + * that the board could wire up to the CPU. + */ +static Property next_pc_properties[] = { + DEFINE_PROP_LINK("cpu", NeXTPC, cpu, TYPE_M68K_CPU, M68kCPU *), + DEFINE_PROP_END_OF_LIST(), +}; + static void next_pc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -900,6 +913,7 @@ static void next_pc_class_init(ObjectClass *klass, void *data) dc->desc = "NeXT Peripheral Controller"; dc->realize = next_pc_realize; dc->reset = next_pc_reset; + device_class_set_props(dc, next_pc_properties); /* We will add the VMState in a later commit */ } @@ -938,6 +952,7 @@ static void next_cube_init(MachineState *machine) /* Peripheral Controller */ pcdev = qdev_new(TYPE_NEXT_PC); + object_property_set_link(OBJECT(pcdev), "cpu", OBJECT(cpu), &error_abort); sysbus_realize_and_unref(SYS_BUS_DEVICE(pcdev), &error_fatal); /* Temporary while we refactor this code */ NEXT_PC(pcdev)->ns = ns; @@ -996,7 +1011,7 @@ static void next_cube_init(MachineState *machine) } /* Serial */ - next_escc_init(cpu); + next_escc_init(pcdev); /* TODO: */ /* Network */ From patchwork Fri Jan 15 20:12:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 363761 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp176342jap; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b3sm10353807wrn.70.2021.01.15.12.12.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 12:12:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 06/11] hw/m68k/next-cube: Move int_status and int_mask to NeXTPC struct Date: Fri, 15 Jan 2021 20:12:01 +0000 Message-Id: <20210115201206.17347-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210115201206.17347-1-peter.maydell@linaro.org> References: <20210115201206.17347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" All the code which accesses int_status and int_mask is now doing so via the NeXTPC->NeXTState indirection, so we can move these fields into the NeXTPC struct where they belong. Signed-off-by: Peter Maydell --- hw/m68k/next-cube.c | 33 ++++++++++++++++----------------- 1 file changed, 16 insertions(+), 17 deletions(-) -- 2.20.1 Reviewed-by: Thomas Huth diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c index a9e57304e04..6b4bcfd4b9b 100644 --- a/hw/m68k/next-cube.c +++ b/hw/m68k/next-cube.c @@ -73,9 +73,6 @@ typedef struct NextRtc { struct NeXTState { MachineState parent; - uint32_t int_mask; - uint32_t int_status; - next_dma dma[10]; qemu_irq *scsi_irq; qemu_irq scsi_dma; @@ -103,6 +100,8 @@ struct NeXTPC { uint32_t scr2; uint8_t scsi_csr_1; uint8_t scsi_csr_2; + uint32_t int_mask; + uint32_t int_status; }; /* Thanks to NeXT forums for this */ @@ -243,7 +242,7 @@ static void nextscr2_write(NeXTPC *s, uint32_t val, int size) /* clear FTU */ if (rtc->value & 0x04) { rtc->status = rtc->status & (~0x18); - s->ns->int_status = s->ns->int_status & (~0x04); + s->int_status = s->int_status & (~0x04); } } } @@ -302,12 +301,12 @@ static uint32_t mmio_readl(NeXTPC *s, hwaddr addr) { switch (addr) { case 0x7000: - /* DPRINTF("Read INT status: %x\n", s->ns->int_status); */ - return s->ns->int_status; + /* DPRINTF("Read INT status: %x\n", s->int_status); */ + return s->int_status; case 0x7800: - DPRINTF("MMIO Read INT mask: %x\n", s->ns->int_mask); - return s->ns->int_mask; + DPRINTF("MMIO Read INT mask: %x\n", s->int_mask); + return s->int_mask; case 0xc000: return s->scr1; @@ -342,12 +341,12 @@ static void mmio_writel(NeXTPC *s, hwaddr addr, uint32_t val) { switch (addr) { case 0x7000: - DPRINTF("INT Status old: %x new: %x\n", s->ns->int_status, val); - s->ns->int_status = val; + DPRINTF("INT Status old: %x new: %x\n", s->int_status, val); + s->int_status = val; break; case 0x7800: - DPRINTF("INT Mask old: %x new: %x\n", s->ns->int_mask, val); - s->ns->int_mask = val; + DPRINTF("INT Mask old: %x new: %x\n", s->int_mask, val); + s->int_mask = val; break; case 0xc000: DPRINTF("SCR1 Write: %x\n", val); @@ -504,9 +503,9 @@ static void scr_writeb(NeXTPC *s, hwaddr addr, uint32_t value) DPRINTF("SCSICSR CPUDMA\n"); /* qemu_irq_raise(s->scsi_dma); */ - s->ns->int_status |= 0x4000000; + s->int_status |= 0x4000000; } else { - s->ns->int_status &= ~(0x4000000); + s->int_status &= ~(0x4000000); } if (value & SCSICSR_INTMASK) { DPRINTF("SCSICSR INTMASK\n"); @@ -798,14 +797,14 @@ static void next_irq(void *opaque, int number, int level) * this HAS to be wrong, the interrupt handlers in mach and together * int_status and int_mask and return if there is a hit */ - if (s->ns->int_mask & (1 << shift)) { + if (s->int_mask & (1 << shift)) { DPRINTF("%x interrupt masked @ %x\n", 1 << shift, cpu->env.pc); /* return; */ } /* second switch triggers the correct interrupt */ if (level) { - s->ns->int_status |= 1 << shift; + s->int_status |= 1 << shift; switch (number) { /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ @@ -834,7 +833,7 @@ static void next_irq(void *opaque, int number, int level) break; } } else { - s->ns->int_status &= ~(1 << shift); + s->int_status &= ~(1 << shift); cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); } } From patchwork Fri Jan 15 20:12:02 2021 Content-Type: text/plain; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b3sm10353807wrn.70.2021.01.15.12.12.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 12:12:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 07/11] hw/m68k/next-cube: Make next_irq GPIO inputs to NEXT_PC device Date: Fri, 15 Jan 2021 20:12:02 +0000 Message-Id: <20210115201206.17347-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210115201206.17347-1-peter.maydell@linaro.org> References: <20210115201206.17347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Make the next_irq function be GPIO inputs to the NEXT_PC device, rather than a freestanding set of qemu_irq lines. This fixes a minor Coverity issue where it correctly points out the trivial memory leak of the memory allocated in the call to qemu_allocate_irqs(). Fixes: CID 1421962 Signed-off-by: Peter Maydell --- include/hw/m68k/next-cube.h | 3 ++- hw/m68k/next-cube.c | 21 ++++----------------- 2 files changed, 6 insertions(+), 18 deletions(-) -- 2.20.1 Acked-by: Thomas Huth diff --git a/include/hw/m68k/next-cube.h b/include/hw/m68k/next-cube.h index 5a56c354b8e..d38c52d540d 100644 --- a/include/hw/m68k/next-cube.h +++ b/include/hw/m68k/next-cube.h @@ -39,7 +39,8 @@ enum next_irqs { NEXT_ENRX_DMA_I, NEXT_SCSI_DMA_I, NEXT_SCC_DMA_I, - NEXT_SND_I + NEXT_SND_I, + NEXT_NUM_IRQS }; #endif /* NEXT_CUBE_H */ diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c index 6b4bcfd4b9b..5a8fc24ed35 100644 --- a/hw/m68k/next-cube.c +++ b/hw/m68k/next-cube.c @@ -734,10 +734,6 @@ static const MemoryRegionOps dma_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -/* - * TODO: set the shift numbers as values in the enum, so the first switch - * will not be needed - */ static void next_irq(void *opaque, int number, int level) { NeXTPC *s = NEXT_PC(opaque); @@ -838,19 +834,8 @@ static void next_irq(void *opaque, int number, int level) } } -static void next_serial_irq(void *opaque, int n, int level) -{ - /* DPRINTF("SCC IRQ NUM %i\n",n); */ - if (n) { - next_irq(opaque, NEXT_SCC_DMA_I, level); - } else { - next_irq(opaque, NEXT_SCC_I, level); - } -} - static void next_escc_init(DeviceState *pcdev) { - qemu_irq *ser_irq = qemu_allocate_irqs(next_serial_irq, pcdev, 2); DeviceState *dev; SysBusDevice *s; @@ -866,8 +851,8 @@ static void next_escc_init(DeviceState *pcdev) s = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(s, &error_fatal); - sysbus_connect_irq(s, 0, ser_irq[0]); - sysbus_connect_irq(s, 1, ser_irq[1]); + sysbus_connect_irq(s, 0, qdev_get_gpio_in(pcdev, NEXT_SCC_I)); + sysbus_connect_irq(s, 1, qdev_get_gpio_in(pcdev, NEXT_SCC_DMA_I)); sysbus_mmio_map(s, 0, 0x2118000); } @@ -886,6 +871,8 @@ static void next_pc_realize(DeviceState *dev, Error **errp) NeXTPC *s = NEXT_PC(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + qdev_init_gpio_in(dev, next_irq, NEXT_NUM_IRQS); + memory_region_init_io(&s->mmiomem, OBJECT(s), &mmio_ops, s, "next.mmio", 0xD0000); memory_region_init_io(&s->scrmem, OBJECT(s), &scr_ops, s, From patchwork Fri Jan 15 20:12:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 363763 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp177914jap; Fri, 15 Jan 2021 12:22:09 -0800 (PST) X-Google-Smtp-Source: ABdhPJzc5cm8qNNlrdjeB+hJvrokZizv9H5I7RgKTV0QuuueeBvlb02AztAgT4xov7+IT9kOB5yf X-Received: by 2002:a25:c786:: with SMTP id w128mr20847716ybe.322.1610742129561; Fri, 15 Jan 2021 12:22:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610742129; cv=none; d=google.com; s=arc-20160816; b=DKvM2yVhtojswfpgIoSjMge4s25INxBcXx247p+Sn20ir2fBavjYke5NL1SNIQ5nJC Ur1DtQs64qFxBqOLIa/NqTOWRCdGWPUAlSxjYzY20fkSCd2RMk6cWbAb31rfGFAFg3Jb I5IpERXfzJeI0yajKIVvLUmQmapjSu36xres/bD9pMn82oGO8w550b5/FDF3q2ArUuRA NgwMh/trRpaLYhydZEKN6QWiBjRxakYQFzo6RPELgRebbMOA42cuM8SJtCBZFT+b1fcQ 8pAUAmepnw9uUa9cNVPeekopas4H4WcWuI2/m6chK/TUSYT1/TCr7jHyEmw8UP58/AU0 Bpkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=s8uTdRNQNLyJc2a5BTXUw8GgoVjbscNIEvNw+cn6bTs=; b=px+AfX/klxcgIV0lXxTryKUO0MLlpEI1Y0nnTjOlqtv1TjYugswyF8bx+sJi6nU0+y UftAFNIZlqvWtNpb1WRkdHf0db+mvh2G2UzsgYgDHOmzLLcKluQ4vDImVPc/XTyH5+UA XQKbAsZKLKK7lSmfbMpRMe41NRRGorPZ3lFO81sNt/Xa9li2umHy63Ce/Z34PyGnVDb/ M7sjsJkOObwNj7MJyjWyNcr3dPyrtQL8kLcpC6iy7i1fLOwXCfDCmJhVnX2dJQwgYx9r IedeqGMKOOR0RDmQBaoFm4quyLVPGTc3+g7J3kmc5i7BEVmqk+Kyib1BTVT/5s3vBPbg cLyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b0UAPeg5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b3sm10353807wrn.70.2021.01.15.12.12.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 12:12:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 08/11] hw/m68k/next-cube: Move rtc into NeXTPC struct Date: Fri, 15 Jan 2021 20:12:03 +0000 Message-Id: <20210115201206.17347-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210115201206.17347-1-peter.maydell@linaro.org> References: <20210115201206.17347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the rtc into the NeXTPC struct. Since this is the last use of the 'backdoor' NextState pointer we can now remove that. Probably the RTC should be its own device at some point: in hardware there is a separate MCS1850 RTC chip connected to the Peripheral Controller via a 1-bit serial interface. That goes beyond the remit of the current refactoring, though. Signed-off-by: Peter Maydell --- hw/m68k/next-cube.c | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) -- 2.20.1 Reviewed-by: Thomas Huth diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c index 5a8fc24ed35..3c83b874c56 100644 --- a/hw/m68k/next-cube.c +++ b/hw/m68k/next-cube.c @@ -78,8 +78,6 @@ struct NeXTState { qemu_irq scsi_dma; qemu_irq scsi_reset; qemu_irq *fd_irq; - - NextRtc rtc; }; #define TYPE_NEXT_PC "next-pc" @@ -88,9 +86,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(NeXTPC, NEXT_PC) struct NeXTPC { SysBusDevice parent_obj; - /* Temporary until all functionality has been moved into this device */ - NeXTState *ns; - M68kCPU *cpu; MemoryRegion mmiomem; @@ -102,6 +97,8 @@ struct NeXTPC { uint8_t scsi_csr_2; uint32_t int_mask; uint32_t int_status; + + NextRtc rtc; }; /* Thanks to NeXT forums for this */ @@ -130,7 +127,7 @@ static void nextscr2_write(NeXTPC *s, uint32_t val, int size) static int phase; static uint8_t old_scr2; uint8_t scr2_2; - NextRtc *rtc = &s->ns->rtc; + NextRtc *rtc = &s->rtc; if (size == 4) { scr2_2 = (val >> 8) & 0xFF; @@ -864,6 +861,11 @@ static void next_pc_reset(DeviceState *dev) /* 0x0000XX00 << vital bits */ s->scr1 = 0x00011102; s->scr2 = 0x00ff0c80; + + s->rtc.status = 0x90; + + /* Load RTC RAM - TODO: provide possibility to load contents from file */ + memcpy(s->rtc.ram, rtc_ram2, 32); } static void next_pc_realize(DeviceState *dev, Error **errp) @@ -920,7 +922,6 @@ static void next_cube_init(MachineState *machine) MemoryRegion *bmapm2 = g_new(MemoryRegion, 1); MemoryRegion *sysmem = get_system_memory(); const char *bios_name = machine->firmware ?: ROM_FILE; - NeXTState *ns = NEXT_MACHINE(machine); DeviceState *dev; DeviceState *pcdev; @@ -940,13 +941,6 @@ static void next_cube_init(MachineState *machine) pcdev = qdev_new(TYPE_NEXT_PC); object_property_set_link(OBJECT(pcdev), "cpu", OBJECT(cpu), &error_abort); sysbus_realize_and_unref(SYS_BUS_DEVICE(pcdev), &error_fatal); - /* Temporary while we refactor this code */ - NEXT_PC(pcdev)->ns = ns; - - ns->rtc.status = 0x90; - - /* Load RTC RAM - TODO: provide possibility to load contents from file */ - memcpy(ns->rtc.ram, rtc_ram2, 32); /* 64MB RAM starting at 0x04000000 */ memory_region_add_subregion(sysmem, 0x04000000, machine->ram); From patchwork Fri Jan 15 20:12:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 363754 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp172179jap; Fri, 15 Jan 2021 12:13:23 -0800 (PST) X-Google-Smtp-Source: ABdhPJwRVd6K+MVke7UGHGE/QsQ30E3w0PGYhPDNC2y5mDJf5I7VfExXF4aNqVtBnRunf09TwwyW X-Received: by 2002:a25:5556:: with SMTP id j83mr20256631ybb.348.1610741603070; Fri, 15 Jan 2021 12:13:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610741603; cv=none; d=google.com; s=arc-20160816; b=q6Rdx9DOtdzQ1J1Q0XvLToF6lbwbra0qxzqXJBd3Ho7+39T0+2MgOUdo9+eo58rjVQ 9fZeZPykO7R6Q+605MUqC2dJCvOmeG3Ob0hxef0qczERLOynWuCdJsOqmEBB2xliSVpT t+XJBjzukARgw5w61/wGNlDkRRdmLJ6OLHUUwCo5z2XrO3XfIRh+Pl3jJ3OAtXE7oZaN +NsKLWhee5IMryV72xjOW37DHnS8z9GXjoYZD04CT1mtjq2qXeMXu3L1a1QQ3hq6cDr+ fKJXh/W2i1Ik0l+IBJQjrpT3VSHS1ZDQX2ztFZGeJx1Aq7bjPGpInxW3eXZWlQYLyhr6 ChCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=z2/OxhZnl1+hCx4R296hZXKkrZrY01o//F5I89aw4RA=; b=a9qDMZAP8SpMZQx8BO45srgFs78VCK7OFYLkbk0taIq6I1PFnnsoO2j6V4eT0gqy+R wN4waTI1j0D6wQy/LTh0W2tehxZ8yIvcCrDuMj1aaENn+STGk9XdL8q6ZQFc1/I4S6Xy 4DQ/XS7v3Ak6viVnI/oguMRkI2IHNgVOAhJoR9vPfHUKpMhMDjIKN7I0m9K6GRk1w8ok jYvx40S+wUu7Cox+2NrV17XkoFhrUIkAIQQ5B0EENgiggJUJC9RoWqadiijEJjHuKA3+ XmqziqDJkKcr9p0d+qdpgIF+HWhlR6JP257RQh/9u3O9P+IxK/nKY57Lllkhg/tkibd+ QGYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="EY/xswtq"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b3sm10353807wrn.70.2021.01.15.12.12.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 12:12:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 09/11] hw/m68k/next-cube: Remove unused fields from NeXTState Date: Fri, 15 Jan 2021 20:12:04 +0000 Message-Id: <20210115201206.17347-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210115201206.17347-1-peter.maydell@linaro.org> References: <20210115201206.17347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fields scsi_irq, scsi_dma, scsi_reset and fd_irq in NeXTState are all unused, except in commented out "this should do something like this" code. Remove the unused fields. As and when the functionality that might use them is added, we can put in the correct kind of wiring (which might or might not need to be a qemu_irq, but which in any case will need to be in the NeXTPC device, not in NeXTState). Signed-off-by: Peter Maydell --- hw/m68k/next-cube.c | 4 ---- 1 file changed, 4 deletions(-) -- 2.20.1 Reviewed-by: Thomas Huth diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c index 3c83b874c56..dd0a2a5aea0 100644 --- a/hw/m68k/next-cube.c +++ b/hw/m68k/next-cube.c @@ -74,10 +74,6 @@ struct NeXTState { MachineState parent; next_dma dma[10]; - qemu_irq *scsi_irq; - qemu_irq scsi_dma; - qemu_irq scsi_reset; - qemu_irq *fd_irq; }; #define TYPE_NEXT_PC "next-pc" From patchwork Fri Jan 15 20:12:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 363762 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp177879jap; Fri, 15 Jan 2021 12:22:07 -0800 (PST) X-Google-Smtp-Source: ABdhPJzQEA6rsMFo5JqMRPQqw9Z0HQcoNcuKBnB3s69LXQ3Es9tIEE/fnagaxC4+JzQXYB8Tb5ug X-Received: by 2002:a25:4d05:: with SMTP id a5mr19999244ybb.429.1610742126941; Fri, 15 Jan 2021 12:22:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610742126; cv=none; d=google.com; s=arc-20160816; b=03cxZeJAf0m6dlQDZ+S7YmdOVnaMMcdcuAJg+7fY/JmoGCHCDNiGqmo7sKhYtq8oQH lB950zIkJm7FeKTszKyUMfP8P96y6ps4hvf3tlA7+8b3Xf39YK/08MT5EOWYnMAWsmim Vel2XARqzNDKST7RlMhL3wKdugM9OfFYqQnkm4IJZVLw1klDhUXZWuvcbQfyPyvuDdBV IYIVhl6Ovz8RqJEl1KDNYDK5nX7BUMR3tPVYcqN0tp0mppgxZZhKLOPcHF+jvYdZ1x2g fovxliUVa+FVb2l0XEKyGcf5Em74ygmIy/a7Gp9fhwnjUcNRor4rmOcMxy6AYOm6LHML G8uA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Dg8m2zopNi5seDJ3Lmhy2PyjbDdEnmQIoHpz7Tv3WJ0=; b=YYpTJSoW584EcggIPlbssyHxU+H+/70eLPlCtuHz3rtWzOL3TClrOYXDgMHmg/xmOm CezM7Yb+DMr6Lq8V57jQlPvWiCOMwOJY4GUbCr0kwSRZZIGeolBPrAOy1urF5yVMPSS4 8oDDI+368jxoowKBPBPkgvvDZr2gkA4G9+Ov0mJQ35OLS2OJJMjrRXSHeX0ze58V6NoI BgSHEp1/6QYcCI8wHELUNYSAWBm+JcGc0Q31l8goHkuOPWcdUDJZ8AD+IVekiwx2UgS3 KgAq1XQkamYSr0YIYvlAYs+nO1j+wZp3LCHw3lbEtlRuzHpnw3FsVmBp8ReWy6GNDDgg 6Xog== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=An9KiHFN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b3sm10353807wrn.70.2021.01.15.12.12.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 12:12:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 10/11] hw/m68k/next-cube: Add vmstate for NeXTPC device Date: Fri, 15 Jan 2021 20:12:05 +0000 Message-Id: <20210115201206.17347-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210115201206.17347-1-peter.maydell@linaro.org> References: <20210115201206.17347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add the vmstate for the new NeXTPC devic; this is in theory a migration compatibility break, but this machine doesn't have working migration currently anyway. Signed-off-by: Peter Maydell --- hw/m68k/next-cube.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) -- 2.20.1 Acked-by: Thomas Huth diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c index dd0a2a5aea0..9eb1e31752b 100644 --- a/hw/m68k/next-cube.c +++ b/hw/m68k/next-cube.c @@ -28,6 +28,7 @@ #include "qapi/error.h" #include "ui/console.h" #include "target/m68k/cpu.h" +#include "migration/vmstate.h" /* #define DEBUG_NEXT */ #ifdef DEBUG_NEXT @@ -890,6 +891,37 @@ static Property next_pc_properties[] = { DEFINE_PROP_END_OF_LIST(), }; +static const VMStateDescription next_rtc_vmstate = { + .name = "next-rtc", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT8_ARRAY(ram, NextRtc, 32), + VMSTATE_UINT8(command, NextRtc), + VMSTATE_UINT8(value, NextRtc), + VMSTATE_UINT8(status, NextRtc), + VMSTATE_UINT8(control, NextRtc), + VMSTATE_UINT8(retval, NextRtc), + VMSTATE_END_OF_LIST() + }, +}; + +static const VMStateDescription next_pc_vmstate = { + .name = "next-pc", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(scr1, NeXTPC), + VMSTATE_UINT32(scr2, NeXTPC), + VMSTATE_UINT32(int_mask, NeXTPC), + VMSTATE_UINT32(int_status, NeXTPC), + VMSTATE_UINT8(scsi_csr_1, NeXTPC), + VMSTATE_UINT8(scsi_csr_2, NeXTPC), + VMSTATE_STRUCT(rtc, NeXTPC, 0, next_rtc_vmstate, NextRtc), + VMSTATE_END_OF_LIST() + }, +}; + static void next_pc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -898,7 +930,7 @@ static void next_pc_class_init(ObjectClass *klass, void *data) dc->realize = next_pc_realize; dc->reset = next_pc_reset; device_class_set_props(dc, next_pc_properties); - /* We will add the VMState in a later commit */ + dc->vmsd = &next_pc_vmstate; } static const TypeInfo next_pc_info = { From patchwork Fri Jan 15 20:12:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 363764 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp178742jap; Fri, 15 Jan 2021 12:23:30 -0800 (PST) X-Google-Smtp-Source: ABdhPJw87IKLkbdZPJ2XfGGo0XeTGQtIKZzngGQiZlBE0JNzq47RmBOb/ACqfG0Z0/v4y57oCMQ1 X-Received: by 2002:a25:5303:: with SMTP id h3mr21398397ybb.58.1610742210350; Fri, 15 Jan 2021 12:23:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610742210; cv=none; d=google.com; s=arc-20160816; b=TOa0Lmew28mUsjF4W3PEyMCowZvBAsdyFiuwOLKPhSiP8qN5YgE3hR0wofah1y1U1Z 1JNB1AvxvQoeBLIq732N9/k2oHVSRVxWZ5ddwYr9BgTsjMonK2R8cWtBElwOhmYuuIyV coN/0J2D8JRGUo4Ax8/SKkT4PKxAD3Cz6w8lu1iNqlRowmkTR62Ok5HvYgIcqFuSlTB4 Q3nF3+yr80QeF+XedW91SMvEYWPriAKjb65XFHY9EoqzTctJ0ravpftsX2p1oKQmPdXt PS7EN1p0NEcBr5P1egTA1SCmVqN9jqms2ciytYIssuD5dbOArVqROMOhRQOmYKJACtHe JdDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Y0DR22hMXp9oKz60CvU6efbhqp4d7kzllxBIJtK8094=; b=G9Nmmhu2rgtbvPPbsnRaQPzX6kTqyD6RDdP+cFIrtEr0d8LLJ92EuJDauvzGvsdaLa S3DRxRV0OLph+T9O+jmREReYjdIXHwssSnknDDzRH/kvveAQOMm+QDKJX3ah0PLr+qyq uV6TYEAC66i7Z46HBnTnMpwUsvER5kxpJsDL9bHF9eYiP2jjWp5JhvBFpPox/33WTnvw oklkDYfgmd7ps1JGN4X0h1rat8Olt2Kp4ngzU4wU3mC+XJswbDQ5O5zMthTzfN2X8dSv Z72hzA0Bh5t8capqR8hrJ7XlRdoLI3GvnXx93NdRQ8c0uur4XnK4vYum9MyebE8shN/5 p37Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DT7xskEi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b3sm10353807wrn.70.2021.01.15.12.12.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 12:12:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 11/11] hw/m68k/next-cube: Add missing header comment to next-cube.h Date: Fri, 15 Jan 2021 20:12:06 +0000 Message-Id: <20210115201206.17347-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210115201206.17347-1-peter.maydell@linaro.org> References: <20210115201206.17347-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The next-cube.h file is missing the usual copyright-and-license header; add it (same as the next-cube.c one). Signed-off-by: Peter Maydell --- include/hw/m68k/next-cube.h | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.20.1 Reviewed-by: Thomas Huth diff --git a/include/hw/m68k/next-cube.h b/include/hw/m68k/next-cube.h index d38c52d540d..43577282d15 100644 --- a/include/hw/m68k/next-cube.h +++ b/include/hw/m68k/next-cube.h @@ -1,3 +1,13 @@ +/* + * NeXT Cube + * + * Copyright (c) 2011 Bryce Lanham + * + * This code is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published + * by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. + */ #ifndef NEXT_CUBE_H #define NEXT_CUBE_H