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[198.145.21.10]) by mx.google.com with ESMTPS id e34-v6si3102248plb.588.2018.03.01.06.01.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Mar 2018 06:01:58 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=SzNug6HP; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 6195B224E6931; Thu, 1 Mar 2018 05:55:49 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::244; helo=mail-wm0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 695DE224E692A for ; Thu, 1 Mar 2018 05:55:47 -0800 (PST) Received: by mail-wm0-x244.google.com with SMTP id h21so11929048wmd.1 for ; Thu, 01 Mar 2018 06:01:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=oOIBX2iU/Xhn4UGBolIHwMn7MS2Y4NrBBoICvjGzsQU=; b=SzNug6HPFHWs8hX8SZxS0YSXmTAkqhPrQ4aY+GPqJo9JJDrulhu4PXjL10UIcrVSMN WFqMsyP5sUU4fczdm2Gw9MgHTWnfaptMuQnLBRLCKj2LuMd3Y1bFnWdR1wyxN8z0Omtc WFd2fbqB6d8BZlTxM9ucWUjrRU+xkh3cEdPZg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=oOIBX2iU/Xhn4UGBolIHwMn7MS2Y4NrBBoICvjGzsQU=; b=Zpn/1pG53r/wW9nk/sfQnOaefhGgcfH8SeNlk9Zpqsnq+PMtgyCpeZvKTl5lNy3vR0 4QJbbFQJVbfiQGBvArFHnk6wT2aTdYFD8O77KVs1B26YPMKcDAT8/zdXwS9a+Z16Xt+E 3YEOlyHju7RQBmkycgnuPnys/p0g/x+6mB4s/2Acp5eEPjOv5k0OAdFNqghxxrovDWtK 7rxIEtGIYeMTPNbEyfExmO6yaxOzZFBO9UNS6Wg/eapY3lZg5kCrDthzsWQD4xpULu0Q LBwpwh+L3d6KZjaUoYwmgFx0QTQZoPWWHVhM2oYnabv63Bdsq05F1g4FrcOkwrrxsoKj wkpw== X-Gm-Message-State: AElRT7H3x+J8Gl2g36BEGI3FZtx2/X3+ayog4+cxAGfqoABj8SBYPTJX iqBnRK/aoMdxfbd5wapLrk4MhQ/uefA= X-Received: by 10.28.184.21 with SMTP id i21mr1978363wmf.94.1519912911765; Thu, 01 Mar 2018 06:01:51 -0800 (PST) Received: from localhost.localdomain ([196.71.216.221]) by smtp.gmail.com with ESMTPSA id w74sm23960776wmd.1.2018.03.01.06.01.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Mar 2018 06:01:50 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 1 Mar 2018 14:01:45 +0000 Message-Id: <20180301140145.10659-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Subject: [edk2] [PATCH edk2-platforms] Silicon/SynQuacer/DeviceTree: use more specific PMU 'compatible string X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Replace the PMU compatible string "arm,armv8-pmuv3" with the more accurate "arm,cortex-a53-pmu", potentially making more event types available. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index fdaccb984483..2db7de3d5b96 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -379,7 +379,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = ; };