From patchwork Thu Jan 21 19:05:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 367864 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp848749jam; Thu, 21 Jan 2021 11:23:24 -0800 (PST) X-Google-Smtp-Source: ABdhPJyWMlNKGdBVYOoMA5Hx8aLf1clzu9HRtrKf6JK/+wAm7yd0EiwWxEmgL1aM+6rEnXBZkpIa X-Received: by 2002:a5b:4c:: with SMTP id e12mr1266051ybp.355.1611257004240; Thu, 21 Jan 2021 11:23:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611257004; cv=none; d=google.com; s=arc-20160816; b=CLt1dt/BHHSR9mzqUXX73fvQJjUZctF3pqHY0/+itHehydmfUp1jwMEXzJJ2kpEH3V BhboeeOygeBq6JVPee8GgWeqB9oOduxHYXBO0PkONnyk824WgghGL8rzzboUSOPnwD9e Kqz8Nu3dWPMij81+04PbdTIV2oINCNq/87mVd8/tQEQ1blHvTkMM3ZnJniR3bFxlMl3i 97hBi1xuFJtXjkRIy85/P5cXJntz8ofLAMGy53Wu24yxb/IDNKhZBxEiwtJ99jOg4Jts n1FJotpX4swvduAvG03vPMlYx53Je/FE8+ctAVJkGlewwFpHmMWicC+loi2xHKA9dhFo z/lQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=CMkjp0id/Ultib0Bf01Fa0R4lEkPZ5/dYQA5kFPJtl0=; b=e/uyH+2Z55QrFEHBXKqaoa8N46ilzHOoQgGdR9I1/hdOA2MvrZQGYnEGLZp6OsW8dg QDQFmz5FtxzaUwjbCxunr28YMpTCZJ7jrUqv41hIWJvsmq81hAm9zRWqUADAF4c5XZIO Bj16tWSLqIKmy6m7tcUByzOc/4o0THLP+AAq2EsrHsJeiKVrQDv/OBbMhbxEFwhPdkuK J0lH/CUoqRSx6ou8J/+yd9S3ts0DYSWf5Oh7n/76yjWSoRd/SaC3hFemcWQ8vL4QVMT3 sKMy18yXFDvJFONO5h1E9cGHYVQRW4oi9oUgjbqVJ4Mtn+zyxj3shM04KX07wxPkaJ2S XjDQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZzR2c6Lc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m65si5962760ybc.55.2021.01.21.11.23.24 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jan 2021 11:23:24 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZzR2c6Lc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34598 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2fYB-0000kl-JX for patch@linaro.org; Thu, 21 Jan 2021 14:23:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55772) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIL-0002MO-4c for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:02 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:46148) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI1-0005kZ-1e for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:06:59 -0500 Received: by mail-wr1-x435.google.com with SMTP id q7so2797059wre.13 for ; Thu, 21 Jan 2021 11:06:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CMkjp0id/Ultib0Bf01Fa0R4lEkPZ5/dYQA5kFPJtl0=; b=ZzR2c6LcIZG+nAvsY8WT9NBeBekCHgIaKMSHtduHxKdS8aEKGaivd62tbC7yz7/7HG iZPqSndP3TLv4W0696PeTouTpl9oEoJQ1wpUSeIfSDpsWXPs0myMNMY/xr/NTndZpStA E6vT78LnVR21gmhRu2i3X7t/av/rD2jm9l4zoriX1NO8rY/R9p2pxph0znXM1UI95uXk BOAm6BqjDjp2kG+RRxI6OPR+dFXgUP9GJRGCEzuzEmHxeIo4InUDkBVkGX9MeTp6wggM GEuvtthWVEIFNNsrxWaxH6Uek67sO19X0Fx/g5YH1aT9MtIxGx9Z6mJdpsGIMXbSOqVu GFyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CMkjp0id/Ultib0Bf01Fa0R4lEkPZ5/dYQA5kFPJtl0=; b=Xf6xfiQhdNG1GPJfa93zu1vw4Xz/ptTvFnuiQ2zhyEwAEESYGhT851y2V1CvuyxH5s JH7SVQe5iurLhxLo7YzmkO8Y80TFvfF1Qx8hZoBqHPJj20NsVPWtoLG50ldzkNYAbhwR rttjNWtAKlmzU5AFGHoyWociIMfSMqcCsCY9rweohkWba1ywxaeeDv8cICXSKvi0Yrfh 7hIY9Tqj5nf1NW/hP4+cs9nBqqzPag6ShU3wXl/vbaO1TRSa7Y2X6HM87p3PKMezN6YM reF3orjM3Kb+aQTp+yEdhIfCz9Y0s389ROkHKgaG6u5gRRz+3YXD+emoLNIkUR5xbtIG IfdQ== X-Gm-Message-State: AOAM532jk71AbY8nrdWqwZn2lRcAvFPSOFubXq/0vc7KxrpzVQ7pTI5l YaPmPCjf2OVIvqdx6Uk/MDa0xIPsExYddw== X-Received: by 2002:a5d:43d2:: with SMTP id v18mr912137wrr.326.1611255986528; Thu, 21 Jan 2021 11:06:26 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:25 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 01/25] ptimer: Add new ptimer_set_period_from_clock() function Date: Thu, 21 Jan 2021 19:05:58 +0000 Message-Id: <20210121190622.22000-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The ptimer API currently provides two methods for setting the period: ptimer_set_period(), which takes a period in nanoseconds, and ptimer_set_freq(), which takes a frequency in Hz. Neither of these lines up nicely with the Clock API, because although both the Clock and the ptimer track the frequency using a representation of whole and fractional nanoseconds, conversion via either period-in-ns or frequency-in-Hz will introduce a rounding error. Add a new function ptimer_set_period_from_clock() which takes the Clock object directly to avoid the rounding issues. This includes a facility for the user to specify that there is a frequency divider between the Clock proper and the timer, as some timer devices like the CMSDK APB dualtimer need this. To avoid having to drag in clock.h from ptimer.h we add the Clock type to typedefs.h. Signed-off-by: Peter Maydell --- Side note, I forget why we didn't go for 64.32 fixedpoint for the Clock too. I kinda feel we might run into the "clocks can't handle periods greater than 4 seconds" limit some day. Hopefully we can backwards-compatibly expand it if that day ever comes... The 'divisor' functionality seemed like the simplest way to get to what I needed for the dualtimer; perhaps we should think about whether we can have generic lightweight support for clock frequency divider/multipliers... --- include/hw/ptimer.h | 22 ++++++++++++++++++++++ include/qemu/typedefs.h | 1 + hw/core/ptimer.c | 34 ++++++++++++++++++++++++++++++++++ 3 files changed, 57 insertions(+) -- 2.20.1 Reviewed-by: Luc Michel diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h index 412763fffb2..c443218475b 100644 --- a/include/hw/ptimer.h +++ b/include/hw/ptimer.h @@ -165,6 +165,28 @@ void ptimer_transaction_commit(ptimer_state *s); */ void ptimer_set_period(ptimer_state *s, int64_t period); +/** + * ptimer_set_period_from_clock - Set counter increment from a Clock + * @s: ptimer to configure + * @clk: pointer to Clock object to take period from + * @divisor: value to scale the clock frequency down by + * + * If the ptimer is being driven from a Clock, this is the preferred + * way to tell the ptimer about the period, because it avoids any + * possible rounding errors that might happen if the internal + * representation of the Clock period was converted to either a period + * in ns or a frequency in Hz. + * + * If the ptimer should run at the same frequency as the clock, + * pass 1 as the @divisor; if the ptimer should run at half the + * frequency, pass 2, and so on. + * + * This function will assert if it is called outside a + * ptimer_transaction_begin/commit block. + */ +void ptimer_set_period_from_clock(ptimer_state *s, const Clock *clock, + unsigned int divisor); + /** * ptimer_set_freq - Set counter frequency in Hz * @s: ptimer to configure diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 976b529dfb5..68deb74ef6f 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -34,6 +34,7 @@ typedef struct BlockDriverState BlockDriverState; typedef struct BusClass BusClass; typedef struct BusState BusState; typedef struct Chardev Chardev; +typedef struct Clock Clock; typedef struct CompatProperty CompatProperty; typedef struct CoMutex CoMutex; typedef struct CPUAddressSpace CPUAddressSpace; diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c index 2aa97cb665c..6ba19fd9658 100644 --- a/hw/core/ptimer.c +++ b/hw/core/ptimer.c @@ -15,6 +15,7 @@ #include "sysemu/qtest.h" #include "block/aio.h" #include "sysemu/cpus.h" +#include "hw/clock.h" #define DELTA_ADJUST 1 #define DELTA_NO_ADJUST -1 @@ -348,6 +349,39 @@ void ptimer_set_period(ptimer_state *s, int64_t period) } } +/* Set counter increment interval from a Clock */ +void ptimer_set_period_from_clock(ptimer_state *s, const Clock *clk, + unsigned int divisor) +{ + /* + * The raw clock period is a 64-bit value in units of 2^-32 ns; + * put another way it's a 32.32 fixed-point ns value. Our internal + * representation of the period is 64.32 fixed point ns, so + * the conversion is simple. + */ + uint64_t raw_period = clock_get(clk); + uint64_t period_frac; + + assert(s->in_transaction); + s->delta = ptimer_get_count(s); + s->period = extract64(raw_period, 32, 32); + period_frac = extract64(raw_period, 0, 32); + /* + * divisor specifies a possible frequency divisor between the + * clock and the timer, so it is a multiplier on the period. + * We do the multiply after splitting the raw period out into + * period and frac to avoid having to do a 32*64->96 multiply. + */ + s->period *= divisor; + period_frac *= divisor; + s->period += extract64(period_frac, 32, 32); + s->period_frac = (uint32_t)period_frac; + + if (s->enabled) { + s->need_reload = true; + } +} + /* Set counter frequency in Hz. */ void ptimer_set_freq(ptimer_state *s, uint32_t freq) { From patchwork Thu Jan 21 19:05:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 367855 Delivered-To: patch@linaro.org Received: by 2002:a17:906:24d5:0:0:0:0 with SMTP id f21csp752178ejb; Thu, 21 Jan 2021 11:10:56 -0800 (PST) X-Google-Smtp-Source: ABdhPJwPquM4GVDSjg6QF81A+neU7cTgp/kxnkezeM9oyrwea4cDhuv/9rUa/0kW5zaxvJ+oEl2e X-Received: by 2002:a25:bbc3:: with SMTP id c3mr1091597ybk.345.1611256256859; Thu, 21 Jan 2021 11:10:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611256256; cv=none; d=google.com; s=arc-20160816; b=0kVpThevySDYITR99A5VsZ21udErijNtAURB5VKoLnM3dkrTcfOpo5uWXOtAU3DtXq MoEXRoCi3YY/C0epceEKerAdt4ahKSZo9JEYhZahUAgf0eBqJWv6ye7rM0MNbgYyEFlK rNwZdkH2+DhDiFofn40Y+JEAXQpJdr3R6GNUW5KCRfRvbIs+XhumNhu0dC2xGsmo8D+R xovza/67IZWpH95SjHV5VTcZHpR1YcJTAEkEsHnK5XM3+1sXkaTnLBzZ0k11sIQ1EInK VVCJlfaBR72vP8BgQNO7kvHXsPlLp7F7D2KZw03HbBAknm5ZmpkqLiUa0hs/Kj7v+g8Z nA1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=upN7NId7waDqdq/y54Hzrsu+F+aVKMHy5OMUTW9rDEw=; b=XJi+VdWNZMzkujdAODgSPtPlEYea5UNxy/SfORWbCqJkI1Njv3rzrgigJ7xCsmdDTZ lHItEdS2OZPLpiPIDs5lgMBxDPeX/ED375C7w+sGRe/2aHWsYkrhJG+GlK3X1GnA1Kxh ZiJhg4GR2qx+z4jwuEQZCy2YZb1sHSQP6KuPnWCO6ZsHN+69w26ABsC1i0CpmiMQEPKe Uz/w7MFIq4futh5/gQHHT+rP7nRpC1iya1cFHMA4O1rWCAQge74GHbv32RBzshoLBrEo uu6IFGYXGdY4bvZE106I9SMO6YzGG5ucYMqTAkrYLnzCJ00jbADPmouYcJA/ut12TlXH T1Zw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=sn0dGRte; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e2si5681722ybq.177.2021.01.21.11.10.56 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jan 2021 11:10:56 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=sn0dGRte; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39046 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2fM8-00073t-7y for patch@linaro.org; Thu, 21 Jan 2021 14:10:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55444) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fI1-0002AP-F3 for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:06:41 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:32893) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fHr-0005kk-G6 for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:06:41 -0500 Received: by mail-wr1-x42f.google.com with SMTP id 7so2830908wrz.0 for ; Thu, 21 Jan 2021 11:06:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=upN7NId7waDqdq/y54Hzrsu+F+aVKMHy5OMUTW9rDEw=; b=sn0dGRtex5P42T3hk2ht1eoYTF/07UWBYlpSpd3RZbe8zb9QSZ4BIdtMinLn+Uxt0o 2bNlUqkjAroSzWDqS/6rvaOr93syDheLNOfwXaqpDFjyqAUzZMAx5n2I6Z77uZLuscUk 79N2daVjLwtxNHbJDblLS2TpjR3w5P9KnUV5VPFKJrJQ7oAQiln3Sdny6I03xtjWfSO4 t11S/3QGsYWV2BnugGlB8mLqViHSzPkgi6EKxlItt1LYZraJIecs90zfilH4+aWkuKq0 I38sTjrCwRakEVEfu/kfI4s5wa9437NhcOlDxG/8ZT3UcBb3cHFFCxvMmYFYNVHbi3hw VNlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=upN7NId7waDqdq/y54Hzrsu+F+aVKMHy5OMUTW9rDEw=; b=UfiEIhXYJWr4Sip5PRkV0/WRpbLj5c7dERpHdEAS8zjMbXRO8dE3SbM4aUQbUba67r xhF+DL2zPOwvm6mn81ut3RCkjqVojR81t8vIKagJrVBPeVTMhu5Vcwf4kGXPIDk0kPm5 UUouPnUUEic0ita9AYwqW0IvMhsbnBrmZXV27NjNGAGLg/IEpBOtDIjI/5nglWUB5Gx5 Hubq6hMiL1y7CVivsvhQdeGovItEsKhIUw5Jxns0jmhaHiplqTPsAFFYkHRLZCtjce0Y rHAoEKfZXNScmIV2VQTKlPXF28x4L+PEQK+EUJul17Hhf36kuSGU1J4QziT4J6FF8DMi fgjg== X-Gm-Message-State: AOAM532nr3iw5a46/oo3sX6go6mXrbNHvjx6tzpl8RjpU3g+XCxxDJv7 AX+P3EXHXb6GlV7ZFErjdqgTDQ== X-Received: by 2002:adf:cc81:: with SMTP id p1mr858184wrj.339.1611255987447; Thu, 21 Jan 2021 11:06:27 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:26 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 02/25] clock: Add new clock_has_source() function Date: Thu, 21 Jan 2021 19:05:59 +0000 Message-Id: <20210121190622.22000-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add a function for checking whether a clock has a source. This is useful for devices which have input clocks that must be wired up by the board as it allows them to fail in realize rather than ploughing on with a zero-period clock. Signed-off-by: Peter Maydell --- docs/devel/clocks.rst | 16 ++++++++++++++++ include/hw/clock.h | 15 +++++++++++++++ 2 files changed, 31 insertions(+) -- 2.20.1 Reviewed-by: Luc Michel Reviewed-by: Philippe Mathieu-Daudé diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst index 2548d842322..c54bbb82409 100644 --- a/docs/devel/clocks.rst +++ b/docs/devel/clocks.rst @@ -235,6 +235,22 @@ object during device instance init. For example: /* set initial value to 10ns / 100MHz */ clock_set_ns(clk, 10); +To enforce that the clock is wired up by the board code, you can +call ``clock_has_source()`` in your device's realize method: + +.. code-block:: c + + if (!clock_has_source(s->clk)) { + error_setg(errp, "MyDevice: clk input must be connected"); + return; + } + +Note that this only checks that the clock has been wired up; it is +still possible that the output clock connected to it is disabled +or has not yet been configured, in which case the period will be +zero. You should use the clock callback to find out when the clock +period changes. + Fetching clock frequency/period ------------------------------- diff --git a/include/hw/clock.h b/include/hw/clock.h index 6382f346569..e5f45e2626d 100644 --- a/include/hw/clock.h +++ b/include/hw/clock.h @@ -139,6 +139,21 @@ void clock_clear_callback(Clock *clk); */ void clock_set_source(Clock *clk, Clock *src); +/** + * clock_has_source: + * @clk: the clock + * + * Returns true if the clock has a source clock connected to it. + * This is useful for devices which have input clocks which must + * be connected by the board/SoC code which creates them. The + * device code can use this to check in its realize method that + * the clock has been connected. + */ +static inline bool clock_has_source(const Clock *clk) +{ + return clk->source != NULL; +} + /** * clock_set: * @clk: the clock to initialize. From patchwork Thu Jan 21 19:06:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 367858 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp843936jam; Thu, 21 Jan 2021 11:16:01 -0800 (PST) X-Google-Smtp-Source: ABdhPJxrQTaK7MS3gaBCSyDN77R+eeaj2O3Mr3JYxhB0d1pZQ/J/oLVrP2fCrXxi5kpVE0BoRUNt X-Received: by 2002:a25:afce:: with SMTP id d14mr1174378ybj.457.1611256560895; Thu, 21 Jan 2021 11:16:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611256560; cv=none; d=google.com; s=arc-20160816; b=B2h9TD1+X6zG/mQH8LsIILDx/j9TNEwAzKEBlA8GEfR88o1/+f6kN28NOamWW2htAN 1cy+5hTueuve8n7o5Cl1f7JNaq+CB8Zx+/7KF8O8lgHDbMAqXm1LG3wL09Lw/AgXm6n8 reV6Ruufq9VhWoLntkLpG/FjKhTaDq96h8P7yhxP+jleXF7thoputAOXljytgmDfZnGP RDs+ijTpn4AlSiFX3ukudOBTAAJhi7jj38Wb1jOhwNWGVDE6FWnsboXEpE8257+J1QPi JbTkdwL4k2JiSK8Hiq9R8PnVWRqBSbJcVY9Kt1/pmu2GR4y7AYwTSN7h7ztp3dGtbUBA PFiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lAXftL8tozQWWTPvWf+4JDafcrxm0XnUCLn5NpEaPkY=; b=iMtIYGtY6mZbLfdM5cMdsYEZjod2INvFDpAHty9rIOh6eBAeK3RKxn4M47z7d2wzPz vwYTWzlCtjyKZJE9IKDLFHVfx1wAmIPfuY5E813cOA98veTWMb+/Hq7e7A60crlJCLqy DqU71uw0s6/bTPWLZ2yEdHjAnBzYhEOvArXLVHJ0lQhl6zUF0YYkkCDwOXFetOkGqbu4 3BhhM9KtGWl7Qr95mDafqj1grOrwkVUc7igjiu28rdNdOUtNqY8hLBSo3oVqDrq7E/Io SFTJtJDiu8MLwg2bHFI0G1djPyeYTX5xuDSuHeWpcf2etsEgULLjXUxscmnFFGOXnu7T 5hoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=pCE1bNoz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s206si5844582ybs.207.2021.01.21.11.16.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jan 2021 11:16:00 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=pCE1bNoz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47734 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2fR2-0002dQ-86 for patch@linaro.org; Thu, 21 Jan 2021 14:16:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55532) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fI4-0002D7-7V for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:06:44 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:45314) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fHr-0005lb-Tt for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:06:44 -0500 Received: by mail-wr1-x42b.google.com with SMTP id m1so2128226wrq.12 for ; Thu, 21 Jan 2021 11:06:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lAXftL8tozQWWTPvWf+4JDafcrxm0XnUCLn5NpEaPkY=; b=pCE1bNozYjUvvwp5pd2YvLY+xKm67VBFoeN3W0PYb1xbEwS/n7ofQalSvv3g/RpH9j nUSk2+2FQLNxZhgc4ZKLSDABf0La9RaNZ8iKF3b05jEfzA4cEr4Cbl577AoNocaQ9wav MqNYDAOoIo3K7gni2kjWiaYbUFUdqT0XX98vhGHNvkrLvJTLBeF85QQyPuBY8jCFuZZg R7OovvRgxe3haCiRmFBCJg+n+x4yYgO8Qae67mXGKcYzqMjVDweWDTmyFt5LeuWIp1N0 V5vJZVUmGH/l98hfMa+l4IMcJsAOgshNzImGF7NG+ygo6vL9asgv75/XkfMElWoF04h5 H1Sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lAXftL8tozQWWTPvWf+4JDafcrxm0XnUCLn5NpEaPkY=; b=ERvsmOTwa9mbXm3I7bJNmC21mT4K8rT2kGuw8oygFBTt1xPLlq3UrsDMhSvcFJZtFJ o+e7q/l2RONlxFE7EGepKWofeYDq9eYCo1qnE2JbD8t8USTwe6uta9FIf3mAwhdud3/j +4P7IRS+ros7fC7QqmXAcqofBSzacJddnP63SVV2G+u2T56ytQH3AVfgBwe3ZvXO3/Wn swlOhdntSn1mX3PEWkZJ5EmiJ2aBxRu2GKD6WV4pHyKoL0SXEhTiryBA/05PXQWOHWLa +bwJirDTMwyNlkljlA5PnWamofSXc0rm+r6bbTqiSeHqUio2qEacti2FI9Db7SVGwPbx geWw== X-Gm-Message-State: AOAM531TQV+4DnH5V/SVkPD8s0G3Qm/ecLMgqEfaGEgDNv5Yra7+Up38 ZFwLRGMi+5Bj8NQEIDE3aroqtw== X-Received: by 2002:adf:ec8c:: with SMTP id z12mr912237wrn.208.1611255988353; Thu, 21 Jan 2021 11:06:28 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:27 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 03/25] tests: Add a simple test of the CMSDK APB timer Date: Thu, 21 Jan 2021 19:06:00 +0000 Message-Id: <20210121190622.22000-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add a simple test of the CMSDK APB timer, since we're about to do some refactoring of how it is clocked. Signed-off-by: Peter Maydell --- tests/qtest/cmsdk-apb-timer-test.c | 76 ++++++++++++++++++++++++++++++ MAINTAINERS | 1 + tests/qtest/meson.build | 1 + 3 files changed, 78 insertions(+) create mode 100644 tests/qtest/cmsdk-apb-timer-test.c -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel diff --git a/tests/qtest/cmsdk-apb-timer-test.c b/tests/qtest/cmsdk-apb-timer-test.c new file mode 100644 index 00000000000..085005cce99 --- /dev/null +++ b/tests/qtest/cmsdk-apb-timer-test.c @@ -0,0 +1,76 @@ +/* + * QTest testcase for the CMSDK APB timer device + * + * Copyright (c) 2021 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" + +/* IoTKit/ARMSSE-200 timer0; driven at 25MHz in mps2-an385, so 40ns per tick */ +#define TIMER_BASE 0x40000000 + +#define CTRL 0 +#define VALUE 4 +#define RELOAD 8 +#define INTSTATUS 0xc + +static void test_timer(void) +{ + g_assert_true(readl(TIMER_BASE + INTSTATUS) == 0); + + /* Start timer: will fire after 40000 ns */ + writel(TIMER_BASE + RELOAD, 1000); + writel(TIMER_BASE + CTRL, 9); + + /* Step to just past the 500th tick and check VALUE */ + clock_step(20001); + g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 0); + g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 500); + + /* Just past the 1000th tick: timer should have fired */ + clock_step(20000); + g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 1); + g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 0); + + /* VALUE reloads at the following tick */ + clock_step(40); + g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 1000); + + /* Check write-1-to-clear behaviour of INTSTATUS */ + writel(TIMER_BASE + INTSTATUS, 0); + g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 1); + writel(TIMER_BASE + INTSTATUS, 1); + g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 0); + + /* Turn off the timer */ + writel(TIMER_BASE + CTRL, 0); +} + +int main(int argc, char **argv) +{ + QTestState *s; + int r; + + g_test_init(&argc, &argv, NULL); + + s = qtest_start("-machine mps2-an385"); + + qtest_add_func("/cmsdk-apb-timer/timer", test_timer); + + r = g_test_run(); + + qtest_end(); + + return r; +} diff --git a/MAINTAINERS b/MAINTAINERS index 3216387521d..010405b0884 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -581,6 +581,7 @@ F: include/hw/rtc/pl031.h F: include/hw/arm/primecell.h F: hw/timer/cmsdk-apb-timer.c F: include/hw/timer/cmsdk-apb-timer.h +F: tests/qtest/cmsdk-apb-timer-test.c F: hw/timer/cmsdk-apb-dualtimer.c F: include/hw/timer/cmsdk-apb-dualtimer.h F: hw/char/cmsdk-apb-uart.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 16d04625b8b..74addd74868 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -141,6 +141,7 @@ qtests_npcm7xx = \ 'npcm7xx_timer-test', 'npcm7xx_watchdog_timer-test'] qtests_arm = \ + (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \ (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \ (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \ ['arm-cpu-features', From patchwork Thu Jan 21 19:06:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 367866 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp849406jam; Thu, 21 Jan 2021 11:24:37 -0800 (PST) X-Google-Smtp-Source: ABdhPJyK193upEK43bSdIb+VQZEUn/d8rSGYRtL4BHQa76I5gjhqKFhh7FE+MgfXZ5SzQwEP4+WM X-Received: by 2002:a25:bd0a:: with SMTP id f10mr1226968ybk.69.1611257077659; Thu, 21 Jan 2021 11:24:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611257077; cv=none; d=google.com; s=arc-20160816; b=arnghJlCubnGdyGtjTqTDkX8j2nOSOsKhybpPxzqZblWoShyLcRqkuFrV3Z+Awpwdv Z89dy12FEVjYmzlGOvuk4+CZ7e4Z8JKXl5ln3po9va379ZvGjQCbJ4Bk9p4W/hsUiTAW ltaa+ZvaHwPhwUwOHT3DEpVuFlxJO2sNCnP7/HzmXXCVQt9IqMhWKc7B6wpz8QaVqaI6 +CP9j5WB7WW7jyTQoZ7LawCmbZneBv6z68LzgIgDb+ts77UOMR9IoNSUNamUe/n/rmCq 5IB0LcMz5naYx6nZAqeWUGZIOKb0bZ5pSfEelLwchoAqBMcvmL+2pJbIDerD5eVfKgMk B1WQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=TB7wjfajbIvKGvglJefMlToUTk7cmyyxw+srKxsN0iM=; b=CfCYdqihFD+ZwqjUtsaLKTzY0+hgcnc2jbIPhbZ2AaaFxr67P3cBM7Lg5MF6DIAFzJ MOnzHbpA7YlcJfVG9X8jUBv0nFi/2K+3micJrRptzxoUtYTRY/KLwrtiHzpfDzI9B13V ti76jpxi0fXiiJuP9IihVcAlaRTfL273AJ4jCo+Rp68uoAkcXbowPDKVLxtCTYO+ufMm DJVjQI9JreQiaXFygNJMY8K/tyg8Q2sPRLbQkkzDsAs2xEiIG2Y9IClxzMzXhMzddIdQ NdaFnzreaJPRmPxhI+lDX7s28FqNkhTDMKJKzes9Qo/ytU0Kq3XPfHvVdO5QaFv68H/l C1jw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=tG46E8L4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e141si6187362ybb.120.2021.01.21.11.24.37 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jan 2021 11:24:37 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=tG46E8L4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38072 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2fZN-0002DZ-3Y for patch@linaro.org; Thu, 21 Jan 2021 14:24:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55684) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fID-0002ID-0A for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:06:54 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:32897) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fHu-0005ml-Fz for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:06:50 -0500 Received: by mail-wr1-x433.google.com with SMTP id 7so2830971wrz.0 for ; Thu, 21 Jan 2021 11:06:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TB7wjfajbIvKGvglJefMlToUTk7cmyyxw+srKxsN0iM=; b=tG46E8L4NhWAz79VmzTFQli25+44SF+SEEPyDCObVfykbsivI3dQzc+yyaK5dkpgpX 1QiPeanvfPTyI1K0E5v57PSSIbxhvEwb09Z1aSTjnwIyhfhOYSCSb2QZDorfq3YsCjGw zojMo4+fQF88bx72fZMLfCJ+9OgGPBVJwjCT1jU9GOFum0yj0TNsz42oY7ghRM83+vvB yPpISmsPO2DF9aXpB4aUbOuIhvf6pH8m+UdtG2rSI+8uXeQs613FTTa0Xb96Unxnlm2o vOfr4yR3MNchPQiBeO8+tHil4nYEq4fjnCBIOCEL8ZzRW5agHddZ4UJBapIM0Jx0H5Xe UAyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TB7wjfajbIvKGvglJefMlToUTk7cmyyxw+srKxsN0iM=; b=p76KQxmzaD8uKLmnDD0vA9OfJ9oQnpOAxPynOhc1gIiq2k8DGERPr80szV9W4AUewB 7xK5f/z49P3eE383gdhCKEDCTV+4j/s6UkvIJjcwRXJKwVo3KWJM9gKJmWxDWovGqVf1 Dj+MC6PyT9nJrdRcPzir6gkHO5BSk+OkaIlOUEA+8Ms9z2wklOOlhnhaMJH8rkvu7SvG zSei/9pGRVSr1sIj4Axo1/ltcZi1yA7wlmSD8MApWWi80dVfNElVT2MzqZn6RNE5wM4N BudYOOTmuQfb5WLfIPZxpdrbYWbacWxeUNhAdsG6ED0DRe6DUJSn1x+kLm5lTkttPAF3 ThBg== X-Gm-Message-State: AOAM530HxLlttELkA9g58xf1krz5EKKUWXmDTqyK5l9w2KreFq/O3kMB bUFBkZaJ29nvGFwUlQk1TjFhGA== X-Received: by 2002:adf:dc89:: with SMTP id r9mr932065wrj.52.1611255989324; Thu, 21 Jan 2021 11:06:29 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:28 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 04/25] tests: Add a simple test of the CMSDK APB watchdog Date: Thu, 21 Jan 2021 19:06:01 +0000 Message-Id: <20210121190622.22000-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add a simple test of the CMSDK watchdog, since we're about to do some refactoring of how it is clocked. Signed-off-by: Peter Maydell --- tests/qtest/cmsdk-apb-watchdog-test.c | 80 +++++++++++++++++++++++++++ MAINTAINERS | 1 + tests/qtest/meson.build | 1 + 3 files changed, 82 insertions(+) create mode 100644 tests/qtest/cmsdk-apb-watchdog-test.c -- 2.20.1 Reviewed-by: Luc Michel Reviewed-by: Philippe Mathieu-Daudé diff --git a/tests/qtest/cmsdk-apb-watchdog-test.c b/tests/qtest/cmsdk-apb-watchdog-test.c new file mode 100644 index 00000000000..c6add1fee85 --- /dev/null +++ b/tests/qtest/cmsdk-apb-watchdog-test.c @@ -0,0 +1,80 @@ +/* + * QTest testcase for the CMSDK APB watchdog device + * + * Copyright (c) 2021 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" + +/* + * lm3s811evb watchdog; at board startup this runs at 200MHz / 16 == 12.5MHz, + * which is 80ns per tick. + */ +#define WDOG_BASE 0x40000000 + +#define WDOGLOAD 0 +#define WDOGVALUE 4 +#define WDOGCONTROL 8 +#define WDOGINTCLR 0xc +#define WDOGRIS 0x10 +#define WDOGMIS 0x14 +#define WDOGLOCK 0xc00 + +static void test_watchdog(void) +{ + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); + + writel(WDOG_BASE + WDOGCONTROL, 1); + writel(WDOG_BASE + WDOGLOAD, 1000); + + /* Step to just past the 500th tick */ + clock_step(500 * 80 + 1); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500); + + /* Just past the 1000th tick: timer should have fired */ + clock_step(500 * 80); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 0); + + /* VALUE reloads at following tick */ + clock_step(80); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000); + + /* Writing any value to WDOGINTCLR clears the interrupt and reloads */ + clock_step(500 * 80); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1); + writel(WDOG_BASE + WDOGINTCLR, 0); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); +} + +int main(int argc, char **argv) +{ + QTestState *s; + int r; + + g_test_init(&argc, &argv, NULL); + + s = qtest_start("-machine lm3s811evb"); + + qtest_add_func("/cmsdk-apb-watchdog/watchdog", test_watchdog); + + r = g_test_run(); + + qtest_end(); + + return r; +} diff --git a/MAINTAINERS b/MAINTAINERS index 010405b0884..58956497888 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -588,6 +588,7 @@ F: hw/char/cmsdk-apb-uart.c F: include/hw/char/cmsdk-apb-uart.h F: hw/watchdog/cmsdk-apb-watchdog.c F: include/hw/watchdog/cmsdk-apb-watchdog.h +F: tests/qtest/cmsdk-apb-watchdog-test.c F: hw/misc/tz-ppc.c F: include/hw/misc/tz-ppc.h F: hw/misc/tz-mpc.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 74addd74868..9e2ebc47041 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -142,6 +142,7 @@ qtests_npcm7xx = \ 'npcm7xx_watchdog_timer-test'] qtests_arm = \ (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \ + (config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-watchdog-test'] : []) + \ (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \ (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \ ['arm-cpu-features', From patchwork Thu Jan 21 19:06:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 367863 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp848465jam; Thu, 21 Jan 2021 11:22:56 -0800 (PST) X-Google-Smtp-Source: ABdhPJwhiADIjOBrzyc8j6i7t8Ulr37+SA0mPaKyFNb7bJxbdBIvxRjKIrDD/1qW9N9HJp9nfcjV X-Received: by 2002:a5b:610:: with SMTP id d16mr1164810ybq.507.1611256976784; Thu, 21 Jan 2021 11:22:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611256976; cv=none; d=google.com; s=arc-20160816; b=RXhni1RB3izORgb/8E02T7bod3VeJ6Oo82mQuZFLL9ojvtwVEJ1hsaxZHk6AlOXPYS YPCKHZ3b51mO3fxRAErlaXYBDwX7JkiRqNTqxn3sTmiflN9DEVboZcWx2ymUG8tcLDVT es+uehDrmuD7g0+xkFjkMZsZp4RbaF19ut0tcHKBb7SJvUv9jzdN4avPQJWIt0Q4l5xx 1zimPZFu1g40Wsj1eFlrEXNegzdw0kGBjC/r8d+JUGWVeBcu+V+8qw7TFJofVBFsHfyW 0KprD3ECrqO5TKcAsSzNWwc5XQDmujB9XiadBgdo0hAOp4RN7OvD3VauHnsmLH0NgKkr 9JJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MgUOZVXgTuq+ewB882N1Uysmr2goe72Go52/tWAmfH4=; b=O8UBv/Tsi/l/xLAP+eCCKJvBmRVEscrxvAMbmj9LN8jwJoQ4kEyjjPOCi53+DNCf+c wuTAI9pW6Xb/PtjuPnbTWVQoqluv78A8kwjLIWENLIf7WJLFShYT3LSWD9GMGN4yXGEK NFoBvlgtw2F1DHc1U83+HRLgn1iVBRGAWJNbmbUDagJehe2c6J6RuV3rnzKfIQnWO3f+ DytQSHsDPV+41/ZOMB3PZxHGpQvzCVTm3VW5sZe0wV/kYHT5nT/qmWchsSmIrUrcPO3C Kv82sim1j2Aq5GtpKXYLJYhvctyCtJxc8vyiBMwZq66mWBIRzudLa9FFpcahd7AoBMTF beGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Y11OzRdJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d10si5831715yba.140.2021.01.21.11.22.56 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jan 2021 11:22:56 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Y11OzRdJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33932 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2fXk-0000Su-3H for patch@linaro.org; Thu, 21 Jan 2021 14:22:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55842) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIP-0002Qm-29 for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:05 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:35044) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI1-0005mw-3U for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:04 -0500 Received: by mail-wr1-x42e.google.com with SMTP id l12so2830982wry.2 for ; Thu, 21 Jan 2021 11:06:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MgUOZVXgTuq+ewB882N1Uysmr2goe72Go52/tWAmfH4=; b=Y11OzRdJGKxQNZokVvT7EEd/YMEtfNqxfPCkKaDdsIWPQYvm5tVmRbf3V5AJd9NcLh VqMhDz8M3SvuMP5Ts6uBvhVyniaJ6hKiLJTxf8b1VY3ci0KfLmNubK25xS0gzSoCzXJJ rKbha/8+Ev6QUeesyjzxx4M+X1TK4kHq1v0f9DltHYeh9dBZtZDPuTP2Dg1y99HiVyjh hnwEZSBznbftF79j8GHSjFrUhos02/5nOY/8zm+SrE8gSue5Htc4AFxqJB18Qo3H85eD mmcKWppHT3DLWQgYs507NZKql06enx5VDJUzhvUwPXb5WilI78j+6giAxCUQcJjJgVG+ 3N4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MgUOZVXgTuq+ewB882N1Uysmr2goe72Go52/tWAmfH4=; b=o1pdf3LR4t5TqDF23s2IJv488RZf8Lnl+K5+G/Nen/7qDRAYdKcN1RzpBVA2A668lD zKVm3j02kc/cLXAb6TcLf5h5NHgNJf8SV4PbwjxSOC89x5XchyaaMwAtsLSC4tPgbe7k BZtptAO8YrDBho0fFUgrptL5AkheyKfJWmJ2IRZJbQuT+jO2dUvUk1DjaC0o0Q80N6GC X6204jCV9UBrXJ7XFxajPuUN66Wuij0ek9Rl1tu0iO9CGDKdWdz511RzjEwYXVDdPNyn wuaTMisjtG+yRfbx0zuKS99Y3QU2TqN78dzpSwVADlX4JMka4tS7Ct0IyxsyN1jV97dY BGqg== X-Gm-Message-State: AOAM533FX8uYGUrATIWa3d3YUg5+bN5o6/o7pJs6lWVNMvTUucqS3+9Q zNpHR7u76MXsJMmrXc+jm1rlUA== X-Received: by 2002:a5d:6204:: with SMTP id y4mr940444wru.48.1611255990430; Thu, 21 Jan 2021 11:06:30 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:29 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 05/25] tests: Add a simple test of the CMSDK APB dual timer Date: Thu, 21 Jan 2021 19:06:02 +0000 Message-Id: <20210121190622.22000-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add a simple test of the CMSDK dual timer, since we're about to do some refactoring of how it is clocked. Signed-off-by: Peter Maydell --- tests/qtest/cmsdk-apb-dualtimer-test.c | 131 +++++++++++++++++++++++++ MAINTAINERS | 1 + tests/qtest/meson.build | 1 + 3 files changed, 133 insertions(+) create mode 100644 tests/qtest/cmsdk-apb-dualtimer-test.c -- 2.20.1 diff --git a/tests/qtest/cmsdk-apb-dualtimer-test.c b/tests/qtest/cmsdk-apb-dualtimer-test.c new file mode 100644 index 00000000000..5a29d65fd6d --- /dev/null +++ b/tests/qtest/cmsdk-apb-dualtimer-test.c @@ -0,0 +1,131 @@ +/* + * QTest testcase for the CMSDK APB dualtimer device + * + * Copyright (c) 2021 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" + +/* IoTKit/ARMSSE dualtimer; driven at 25MHz in mps2-an385, so 40ns per tick */ +#define TIMER_BASE 0x40002000 + +#define TIMER1LOAD 0 +#define TIMER1VALUE 4 +#define TIMER1CONTROL 8 +#define TIMER1INTCLR 0xc +#define TIMER1RIS 0x10 +#define TIMER1MIS 0x14 +#define TIMER1BGLOAD 0x18 + +#define TIMER2LOAD 0x20 +#define TIMER2VALUE 0x24 +#define TIMER2CONTROL 0x28 +#define TIMER2INTCLR 0x2c +#define TIMER2RIS 0x30 +#define TIMER2MIS 0x34 +#define TIMER2BGLOAD 0x38 + +#define CTRL_ENABLE (1 << 7) +#define CTRL_PERIODIC (1 << 6) +#define CTRL_INTEN (1 << 5) +#define CTRL_PRESCALE_1 (0 << 2) +#define CTRL_PRESCALE_16 (1 << 2) +#define CTRL_PRESCALE_256 (2 << 2) +#define CTRL_32BIT (1 << 1) +#define CTRL_ONESHOT (1 << 0) + +static void test_dualtimer(void) +{ + g_assert_true(readl(TIMER_BASE + TIMER1RIS) == 0); + + /* Start timer: will fire after 40000 ns */ + writel(TIMER_BASE + TIMER1LOAD, 1000); + /* enable in free-running, wrapping, interrupt mode */ + writel(TIMER_BASE + TIMER1CONTROL, CTRL_ENABLE | CTRL_INTEN); + + /* Step to just past the 500th tick and check VALUE */ + clock_step(20001); + g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 0); + g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 500); + + /* Just past the 1000th tick: timer should have fired */ + clock_step(20000); + g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 1); + g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 0); + + /* + * We are in free-running wrapping 16-bit mode, so on the following + * tick VALUE should have wrapped round to 0xffff. + */ + clock_step(40); + g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 0xffff); + + /* Check that any write to INTCLR clears interrupt */ + writel(TIMER_BASE + TIMER1INTCLR, 1); + g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 0); + + /* Turn off the timer */ + writel(TIMER_BASE + TIMER1CONTROL, 0); +} + +static void test_prescale(void) +{ + g_assert_true(readl(TIMER_BASE + TIMER2RIS) == 0); + + /* Start timer: will fire after 40 * 256 * 1000 == 1024000 ns */ + writel(TIMER_BASE + TIMER2LOAD, 1000); + /* enable in periodic, wrapping, interrupt mode, prescale 256 */ + writel(TIMER_BASE + TIMER2CONTROL, + CTRL_ENABLE | CTRL_INTEN | CTRL_PERIODIC | CTRL_PRESCALE_256); + + /* Step to just past the 500th tick and check VALUE */ + clock_step(40 * 256 * 501); + g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 0); + g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 500); + + /* Just past the 1000th tick: timer should have fired */ + clock_step(40 * 256 * 500); + g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 1); + g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 0); + + /* In periodic mode the tick VALUE now reloads */ + clock_step(256); + g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 1000); + + /* Check that any write to INTCLR clears interrupt */ + writel(TIMER_BASE + TIMER2INTCLR, 1); + g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 0); + + /* Turn off the timer */ + writel(TIMER_BASE + TIMER2CONTROL, 0); +} + +int main(int argc, char **argv) +{ + QTestState *s; + int r; + + g_test_init(&argc, &argv, NULL); + + s = qtest_start("-machine mps2-an385"); + + qtest_add_func("/cmsdk-apb-dualtimer/dualtimer", test_dualtimer); + qtest_add_func("/cmsdk-apb-dualtimer/prescale", test_prescale); + + r = g_test_run(); + + qtest_end(); + + return r; +} diff --git a/MAINTAINERS b/MAINTAINERS index 58956497888..118f70e47fb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -584,6 +584,7 @@ F: include/hw/timer/cmsdk-apb-timer.h F: tests/qtest/cmsdk-apb-timer-test.c F: hw/timer/cmsdk-apb-dualtimer.c F: include/hw/timer/cmsdk-apb-dualtimer.h +F: tests/qtest/cmsdk-apb-dualtimer-test.c F: hw/char/cmsdk-apb-uart.c F: include/hw/char/cmsdk-apb-uart.h F: hw/watchdog/cmsdk-apb-watchdog.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 9e2ebc47041..69dd4a8547c 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -141,6 +141,7 @@ qtests_npcm7xx = \ 'npcm7xx_timer-test', 'npcm7xx_watchdog_timer-test'] qtests_arm = \ + (config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-dualtimer-test'] : []) + \ (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \ (config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-watchdog-test'] : []) + \ (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \ From patchwork Thu Jan 21 19:06:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 367853 Delivered-To: patch@linaro.org Received: by 2002:a17:906:24d5:0:0:0:0 with SMTP id f21csp749736ejb; Thu, 21 Jan 2021 11:07:32 -0800 (PST) X-Google-Smtp-Source: ABdhPJytSqv340/4eFRU/+OXC5u2Bbx+GAYNhDcMz33AWa2YIVtOPLMiJbMDmpesGQxeQAKIjin3 X-Received: by 2002:a25:918f:: with SMTP id w15mr1125880ybl.54.1611256051859; Thu, 21 Jan 2021 11:07:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611256051; cv=none; d=google.com; s=arc-20160816; b=ZQlGBeHXKqKvQKhDWMVcZ/ie5b5m86NXUi1GgTruM+DZnS5QtMg0iTcbVEVQqWIc6p p6w1fsHhpJwajn0Dhk8xTzweS/JwH89UJ7GiVuK8vXK+UNSc8hpnmKgm+kKoiSzSJPPG y8oRzkLGJce3Jq8IotL05zquXYTmoN7reGqOoeQzVogehrgca7/uArXuJgCMF6EDG26W Iol5yKZlHvA/r5HQ+Wz/dPbes1SnqkRdnaOmheHJUOYkB2vdo1z22URNG+qfVK8Rro4J mnQLOEP4UvK/j89XqIGCA5PodkGInNY206xQiJWjfJRd6P8M7HJu33o1ICj3sFApSbWX eZNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jof7Fo3+SWgxMSAxHIHQk0SnRA/MK6xgKMN5PCrEdn4=; b=QAWul//oplFpUcxuOwdvwLwDWtzAjyoHhM9LRtcHIjciCiQRedSEm9mUn18MRh3lPd pUSosvLs/vgxuFeL51ODe67BDAmVxwv2JiV3F6jtxhmOfnh2IC5+fsEXLwVHHQYYF9j1 pIkh+24CjwJ/V37XTbmzgtndR+ZuMtkAWNQ7RjR6erW+5rGfsC4otTW4Kz2kidTDpmmR 1qztbk1NaTGELxyeW4kUesPSPzgdjrwuDzucIX5rtHH3KH2bjL+Lom4CCsJPiKHtsmdM IB2yRXIs5slJifLhMej/i+hIxtKNC7M2SChoO5nB/k//j4Jl2Qt7uiu/ThSMnXv70+R5 HP9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PEMWggmt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g205si5291566ybg.317.2021.01.21.11.07.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jan 2021 11:07:31 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PEMWggmt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:58110 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2fIp-0002FA-5O for patch@linaro.org; Thu, 21 Jan 2021 14:07:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55516) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fI3-0002Co-P1 for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:06:44 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:33939) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fHv-0005n8-J7 for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:06:43 -0500 Received: by mail-wr1-x430.google.com with SMTP id g10so2827766wrx.1 for ; Thu, 21 Jan 2021 11:06:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jof7Fo3+SWgxMSAxHIHQk0SnRA/MK6xgKMN5PCrEdn4=; b=PEMWggmtPQvZUQmsl2AhjBvXnR7M7NGjsP2U0Hv96ihz0G0p6si77+eAoImqx6xvXg M7w9OG4Fs31uyDWbexjSX/mBVrrAFA9hSMEuGPzdWVUsT2/IB4aMGVJ5aHkDZPCpFBFL 35DehO7LQbdBMJTU1WU9Mc1ipnOJaz3cEnl4wmyk2yZlz3PouUG+ogeb5p5arM/irKmE RsQ9zid23b1HmwlMguRMoVG5Ks4MmTqGiyXcYXtXzwS+9fbgPQr5Nldziieq2joJpT97 gJJHc9v2IDJ8X96vwutfqWjYf3ZF6/zsEVfBX244sVB7G1WSyslt/guwKKKUmcTQQE/y wP0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jof7Fo3+SWgxMSAxHIHQk0SnRA/MK6xgKMN5PCrEdn4=; b=Vh2dZnfpUioNvWhMqEwxFNpH02LIUQSx4yx5ADJDgYe6qmCy5zr1vDjytWEHgU1Bqj c1CoTK92YfAL9IREcu1GuK60hqhlG2CLEkuzNUlNMuPkV8pGIwzmN6gEheq+9C0O+Aum +MSHFKOaroKkzNa5HqRv6i985g1guwhgnop6yADsyPASR5o1mMH4WbwDJMUTwV3y1an/ VCpOX3fVS3zg9u8m2vmOrDymIZZl+rIQsWkf2PQm1lvHmJSIqrdrRNVaSEjduErIGwGq Q5NlsDscOhoVJhBUV22s1011fyfOXY67Uq7KQBfg8HX2P3vZCOZOKlhnLvf/tewTdtmL BBlA== X-Gm-Message-State: AOAM533S0s9fYMpqtqqgQI0IWO0uPzVFITrLB+G3cWOUTNvhnij6Ak+f t4yod9C+qH4vN3nryKFayQGycQ== X-Received: by 2002:adf:d20b:: with SMTP id j11mr889515wrh.318.1611255991376; Thu, 21 Jan 2021 11:06:31 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:30 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 06/25] hw/timer/cmsdk-apb-timer: Rename CMSDKAPBTIMER struct to CMSDKAPBTimer Date: Thu, 21 Jan 2021 19:06:03 +0000 Message-Id: <20210121190622.22000-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The state struct for the CMSDK APB timer device doesn't follow our usual naming convention of camelcase -- "CMSDK" and "APB" are both acronyms, but "TIMER" is not so should not be all-uppercase. Globally rename the struct to "CMSDKAPBTimer" (bringing it into line with CMSDKAPBWatchdog and CMSDKAPBDualTimer; CMSDKAPBUART remains as-is because "UART" is an acronym). Commit created with: perl -p -i -e 's/CMSDKAPBTIMER/CMSDKAPBTimer/g' hw/timer/cmsdk-apb-timer.c include/hw/arm/armsse.h include/hw/timer/cmsdk-apb-timer.h Signed-off-by: Peter Maydell --- include/hw/arm/armsse.h | 6 +++--- include/hw/timer/cmsdk-apb-timer.h | 4 ++-- hw/timer/cmsdk-apb-timer.c | 28 ++++++++++++++-------------- 3 files changed, 19 insertions(+), 19 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 77f86771c30..83f5e28c16e 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -153,9 +153,9 @@ struct ARMSSE { TZPPC apb_ppc0; TZPPC apb_ppc1; TZMPC mpc[IOTS_NUM_MPC]; - CMSDKAPBTIMER timer0; - CMSDKAPBTIMER timer1; - CMSDKAPBTIMER s32ktimer; + CMSDKAPBTimer timer0; + CMSDKAPBTimer timer1; + CMSDKAPBTimer s32ktimer; qemu_or_irq ppc_irq_orgate; SplitIRQ sec_resp_splitter; SplitIRQ ppc_irq_splitter[NUM_PPCS]; diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h index 0d80b2a48cd..baa009bb2da 100644 --- a/include/hw/timer/cmsdk-apb-timer.h +++ b/include/hw/timer/cmsdk-apb-timer.h @@ -18,9 +18,9 @@ #include "qom/object.h" #define TYPE_CMSDK_APB_TIMER "cmsdk-apb-timer" -OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTIMER, CMSDK_APB_TIMER) +OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER) -struct CMSDKAPBTIMER { +struct CMSDKAPBTimer { /*< private >*/ SysBusDevice parent_obj; diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c index f85f1309f37..ae9c5422540 100644 --- a/hw/timer/cmsdk-apb-timer.c +++ b/hw/timer/cmsdk-apb-timer.c @@ -67,14 +67,14 @@ static const int timer_id[] = { 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ }; -static void cmsdk_apb_timer_update(CMSDKAPBTIMER *s) +static void cmsdk_apb_timer_update(CMSDKAPBTimer *s) { qemu_set_irq(s->timerint, !!(s->intstatus & R_INTSTATUS_IRQ_MASK)); } static uint64_t cmsdk_apb_timer_read(void *opaque, hwaddr offset, unsigned size) { - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque); + CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque); uint64_t r; switch (offset) { @@ -106,7 +106,7 @@ static uint64_t cmsdk_apb_timer_read(void *opaque, hwaddr offset, unsigned size) static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque); + CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque); trace_cmsdk_apb_timer_write(offset, value, size); @@ -181,7 +181,7 @@ static const MemoryRegionOps cmsdk_apb_timer_ops = { static void cmsdk_apb_timer_tick(void *opaque) { - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque); + CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque); if (s->ctrl & R_CTRL_IRQEN_MASK) { s->intstatus |= R_INTSTATUS_IRQ_MASK; @@ -191,7 +191,7 @@ static void cmsdk_apb_timer_tick(void *opaque) static void cmsdk_apb_timer_reset(DeviceState *dev) { - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev); + CMSDKAPBTimer *s = CMSDK_APB_TIMER(dev); trace_cmsdk_apb_timer_reset(); s->ctrl = 0; @@ -206,7 +206,7 @@ static void cmsdk_apb_timer_reset(DeviceState *dev) static void cmsdk_apb_timer_init(Object *obj) { SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(obj); + CMSDKAPBTimer *s = CMSDK_APB_TIMER(obj); memory_region_init_io(&s->iomem, obj, &cmsdk_apb_timer_ops, s, "cmsdk-apb-timer", 0x1000); @@ -216,7 +216,7 @@ static void cmsdk_apb_timer_init(Object *obj) static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) { - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev); + CMSDKAPBTimer *s = CMSDK_APB_TIMER(dev); if (s->pclk_frq == 0) { error_setg(errp, "CMSDK APB timer: pclk-frq property must be set"); @@ -239,17 +239,17 @@ static const VMStateDescription cmsdk_apb_timer_vmstate = { .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { - VMSTATE_PTIMER(timer, CMSDKAPBTIMER), - VMSTATE_UINT32(ctrl, CMSDKAPBTIMER), - VMSTATE_UINT32(value, CMSDKAPBTIMER), - VMSTATE_UINT32(reload, CMSDKAPBTIMER), - VMSTATE_UINT32(intstatus, CMSDKAPBTIMER), + VMSTATE_PTIMER(timer, CMSDKAPBTimer), + VMSTATE_UINT32(ctrl, CMSDKAPBTimer), + VMSTATE_UINT32(value, CMSDKAPBTimer), + VMSTATE_UINT32(reload, CMSDKAPBTimer), + VMSTATE_UINT32(intstatus, CMSDKAPBTimer), VMSTATE_END_OF_LIST() } }; static Property cmsdk_apb_timer_properties[] = { - DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTIMER, pclk_frq, 0), + DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTimer, pclk_frq, 0), DEFINE_PROP_END_OF_LIST(), }; @@ -266,7 +266,7 @@ static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data) static const TypeInfo cmsdk_apb_timer_info = { .name = TYPE_CMSDK_APB_TIMER, .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(CMSDKAPBTIMER), + .instance_size = sizeof(CMSDKAPBTimer), .instance_init = cmsdk_apb_timer_init, .class_init = cmsdk_apb_timer_class_init, }; From patchwork Thu Jan 21 19:06:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 367856 Delivered-To: patch@linaro.org Received: by 2002:a17:906:24d5:0:0:0:0 with SMTP id f21csp752912ejb; Thu, 21 Jan 2021 11:11:58 -0800 (PST) X-Google-Smtp-Source: ABdhPJw4x2oh5mFLaky+yh/9UFl8I5Y4sbsMcgvGSh3TpoICQ0IBv0hkRBGteONVEA66g5EOIfOV X-Received: by 2002:a25:be06:: with SMTP id h6mr1266016ybk.38.1611256317893; Thu, 21 Jan 2021 11:11:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611256317; cv=none; d=google.com; s=arc-20160816; b=mW6/0G9+q4q79TQuEhoG6jIq9bv9yPgkjryjPmtX/VtLfmtjc+kq56xw4Yx/I/Qy4F zZQDPdSysmR7lIyErlR9UPrE0JI7UyPKqlubIXXRaQYD3zka0YeO58z2kQ0mYax49s5r EmM9K+4mbRAyes0/BuNQvhKMdJ51zGa7v+B4o4yLIIk3Pz6f4QqkOxBqKy6204FAuN5V yXjfV9FFH/I/pD1GV4plj6MOcDI9U3yCVRkoy34oy2ApSUhP1LlGg2hpEEbnD7r0ymB/ eshYjRzH+/l07U9b9IS9sf/oY8UZNac33o1DWigA+KK848evmOqyfmHkk5KWHXuWcJiY ZVWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=J9BR/GO6dAcwmljpzro+bgjrMat3zg7pQ+dtLLqxHsc=; b=R4rBfPQuzKgmToAkv/UHGHbuQSxoQganIuK4iddYYMcWNRk0kJ3QcJkV1Os9i8eY4r RSzDQ85YYFxaxfUvzrMBYMIRIM7D+hoAX1QxiyTCipzrvHStauYvOnqTqVkERg+FiLNY iB9WvgEZk6RrHKStbT33ffHu9bgyQlL0+jCbBDlXvywREbkMuSPGwE1U9vftbp1/2Zoz OX0hpLo3+blInplRaHkhlMMiorNX4ZI4b8JLxrHc4KKS+KT/ckKjQbo5HlT47ff+CCd6 C5/GO6MVnIopS1w90NF+MrYjP3jS0WIn/MAB+w2v8t7U9Rubr8OkuW6/efa9MUQJIC2z Xonw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=u2DYnA5U; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c127si5925318yba.167.2021.01.21.11.11.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jan 2021 11:11:57 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=u2DYnA5U; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40740 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2fN7-0007y2-A2 for patch@linaro.org; Thu, 21 Jan 2021 14:11:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55572) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fI5-0002En-FN for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:06:47 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:52022) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fHz-0005o7-Do for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:06:45 -0500 Received: by mail-wm1-x336.google.com with SMTP id m2so2404689wmm.1 for ; Thu, 21 Jan 2021 11:06:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=J9BR/GO6dAcwmljpzro+bgjrMat3zg7pQ+dtLLqxHsc=; b=u2DYnA5U4Z8C3w7JhcYg0Vixe5xG6Jep7LASdE1W3KY+Xj7m+J/12cImVpSSKCBBhE l35JrWTh1MaUQJD8+vO9/Kmv9ZBsiGrMZbqyciGiaIS73Wsz6AkV5A8a3RhyQHAuCZL+ XdK6DapBZi8hAg5BNjFmirw+qIbFIndKAi20hgXaWAOrik35x74OF3qFUEWYhqcTG37o 0ay2Ze4AXXXEwk+pdP0dwAIYdYjI9ntVc3aFiZ+qsu1p+dK7c8V5UiULtYJSdmI+hc6J jPIFTro/oO0q+1QKAyu0m/GBXhxX523EpqlgWhsclABlZALXj/5O8fk2O9sEVY7OgQ3/ TZmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=J9BR/GO6dAcwmljpzro+bgjrMat3zg7pQ+dtLLqxHsc=; b=Dj1JDw2KF+j7pFrGJAFo9DhW+86LcS9HuIhFwbtLEXIm0OJ6YqBNzHMxMTtg3GX6HC QyIoYfNOZfPjOIMAti3FMzc3dY4xJdqZoHYXTPLzMowAfxhROc7fzUJi/IPZDGRa99Ew qIWzBJeRwYyY6pwSnydI1ujUNJyFY8b/FpyZYTV2peHIz8f6VAMZ2Uyrr5FcyUFyuQUx 7XArE4IZdKKJ8Sv9kPtOSfc32IFTJ9ZI9EoTl0cz4VkHwC1Pwm+Heiy1zeyu+x4z3hjO ML1v7eTFnE3vKB+xR04tEvTY7grP6UsJCLNwSGX69djFOdqCPgFkjtglct5K/d5fpytN 53VQ== X-Gm-Message-State: AOAM532qO2TVJaLYm/PpvZTT4DY1oSDmQm5VlLP5mfoDsyiIa0G586uz mAADN41kH0o4ouyGcQ835kfkSQ== X-Received: by 2002:a7b:ca4d:: with SMTP id m13mr788208wml.28.1611255992323; Thu, 21 Jan 2021 11:06:32 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:31 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 07/25] hw/timer/cmsdk-apb-timer: Add Clock input Date: Thu, 21 Jan 2021 19:06:04 +0000 Message-Id: <20210121190622.22000-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As the first step in converting the CMSDK_APB_TIMER device to the Clock framework, add a Clock input. For the moment we do nothing with this clock; we will change the behaviour from using the pclk-frq property to using the Clock once all the users of this device have been converted to wire up the Clock. Since the device doesn't already have a doc comment for its "QEMU interface", we add one including the new Clock. This is a migration compatibility break for machines mps2-an505, mps2-an521, musca-a, musca-b1. Signed-off-by: Peter Maydell --- include/hw/timer/cmsdk-apb-timer.h | 9 +++++++++ hw/timer/cmsdk-apb-timer.c | 7 +++++-- 2 files changed, 14 insertions(+), 2 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h index baa009bb2da..fc2aa97acac 100644 --- a/include/hw/timer/cmsdk-apb-timer.h +++ b/include/hw/timer/cmsdk-apb-timer.h @@ -15,11 +15,19 @@ #include "hw/qdev-properties.h" #include "hw/sysbus.h" #include "hw/ptimer.h" +#include "hw/clock.h" #include "qom/object.h" #define TYPE_CMSDK_APB_TIMER "cmsdk-apb-timer" OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER) +/* + * QEMU interface: + * + QOM property "pclk-frq": frequency at which the timer is clocked + * + Clock input "pclk": clock for the timer + * + sysbus MMIO region 0: the register bank + * + sysbus IRQ 0: timer interrupt TIMERINT + */ struct CMSDKAPBTimer { /*< private >*/ SysBusDevice parent_obj; @@ -29,6 +37,7 @@ struct CMSDKAPBTimer { qemu_irq timerint; uint32_t pclk_frq; struct ptimer_state *timer; + Clock *pclk; uint32_t ctrl; uint32_t value; diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c index ae9c5422540..c63145ff553 100644 --- a/hw/timer/cmsdk-apb-timer.c +++ b/hw/timer/cmsdk-apb-timer.c @@ -35,6 +35,7 @@ #include "hw/sysbus.h" #include "hw/irq.h" #include "hw/registerfields.h" +#include "hw/qdev-clock.h" #include "hw/timer/cmsdk-apb-timer.h" #include "migration/vmstate.h" @@ -212,6 +213,7 @@ static void cmsdk_apb_timer_init(Object *obj) s, "cmsdk-apb-timer", 0x1000); sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->timerint); + s->pclk = qdev_init_clock_in(DEVICE(s), "pclk", NULL, NULL); } static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) @@ -236,10 +238,11 @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) static const VMStateDescription cmsdk_apb_timer_vmstate = { .name = "cmsdk-apb-timer", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { VMSTATE_PTIMER(timer, CMSDKAPBTimer), + VMSTATE_CLOCK(pclk, CMSDKAPBTimer), VMSTATE_UINT32(ctrl, CMSDKAPBTimer), VMSTATE_UINT32(value, CMSDKAPBTimer), VMSTATE_UINT32(reload, CMSDKAPBTimer), From patchwork Thu Jan 21 19:06:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 367859 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp844166jam; Thu, 21 Jan 2021 11:16:21 -0800 (PST) X-Google-Smtp-Source: ABdhPJzDzjoWgcVo0EI/SIsvFARUlLri11jorFLj4GGdqrrAaH7DGux0jXKqOFkdZLL0otsyJaTz X-Received: by 2002:a5b:410:: with SMTP id m16mr1122607ybp.451.1611256581908; Thu, 21 Jan 2021 11:16:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611256581; cv=none; d=google.com; s=arc-20160816; b=n5D5NWU0mKkknbSCCY5eARxMYydMCaS+FHzUchN7OFOZqLa8eFVV5pO/vVX14s7N0O 2FAo3Z2iJDgtZ94T5aLzsGR7ezM3MysoA/nHZsDJj/1Gxz4S+/Vre7EAI3jwb5TzIjPv A/3bh4kTrJ6WZTkOUdZK/JCQZqkvh1ub8ylWA7lP7tUaWLmWKZFrdLIPUWGMAGeJAlVl G2fITT/dpu07YdILo0eHZdvmE6S5KEZcEDmPpCsOT3LvsojggNPzn7xeKs9R/uW4u6Ub q3AbKupoqvNrkuKTLyhXndIW1dh9rnASPoXMzod1qM9ljFp5ZUszXQuw8WRRSgu8EJ9E lY7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0rKrl7iJBderO7McLU9xdXqR32edl/U7+oETLREFgpc=; b=UvlhaXIc3Y9cjT6CB2FbFZdR4DCxPJteR6gsTVXmnDhwx25MiQzIpb3/3UdIae01Q5 fuVDp4JaYJX9ivGKU11MchdobF0D7QAVoqbTMtQfCRg7b3UsiPOrJNZxOpMKwkWqPoMH Ye5SXeZxGTs/d2sdjbQi421ZhR8sa2cu0GchrEWOam0sW1FvomhJfNB3UuGIIsKs88Bh CXksnJ6ht4tdgqwZSxJ3DhvUP+v179Iv760B0y9doNFJ0BWzfHGTWC7hVrCnlg6QOKN3 XE99stC21o09/tjU1qfaLf3735igdNR/ZaL1sWikkYsOu6z4YC2qCig6FDfnc4KwhDB/ WYRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=o5xVGYj6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y79si6123019ybe.233.2021.01.21.11.16.21 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jan 2021 11:16:21 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=o5xVGYj6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48254 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2fRN-00030I-9f for patch@linaro.org; Thu, 21 Jan 2021 14:16:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55542) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fI4-0002DO-Gf for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:06:44 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:44046) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fHz-0005oJ-2b for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:06:44 -0500 Received: by mail-wr1-x436.google.com with SMTP id d16so2144772wro.11 for ; Thu, 21 Jan 2021 11:06:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0rKrl7iJBderO7McLU9xdXqR32edl/U7+oETLREFgpc=; b=o5xVGYj6fJqYPGJqArDxdJUlPmUJ6v3eebK0MQPMjvr5Mq1HJ/phxgK3X11dcErZDc nIklC5LhCi7P8IeWH8JoxCJz1dJ0r0e+tT3YA3zkr15HbUKNyVwc33WvI+D73cFEvLH5 4+SdU2CFDMCTtw0FMGw+hqqSdUvzkiGR6TzOr5RnSQQ2h8YyChyFM0K1I9/okg+88jn4 tPo9v+u14kTXVc0Ur31wPHr/6UQmhkSqyJPWy0Hs3+0unVr/xPgeMAaODONR6Rpb9u33 5I0t14ZtLGyO9ca+rOEfi/lTzMh09F3csoxmoTgFnrbW31iKRvwFWrcUewAxOUvmOu8A xVoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0rKrl7iJBderO7McLU9xdXqR32edl/U7+oETLREFgpc=; b=K4U4weRa8ah2ACzbSRR2c9s1YxLltMNUFCmSihzhocy0rIk9qeOwXwg+jxEnu8wd/q NJ79FiwNEYjDfBJ8+7R5ACKl94/VAcifYmXGnFFSmW8eLn4ABnM9IJjvhdvVyd97oX8Y 12arZSAcQXaCwd+aQnvGy9g1U1prOeyinHy/V4VjfG/eS7t3kIPc6IBPI5GkBSrNupb5 dWQevftTwqiUxnq58rp6ZQQFtKjOyuvl8hk2/f/UIjWa9XeJj3spsvOQzjz+tDf9vtmh ho2ToPnWG+hSqRNr4wVAhC0lApT1BDvLhVGS0uc/WA2Cj5YGebUGXkBBQ41wVqCy8BX2 ANXg== X-Gm-Message-State: AOAM530oMCCmbMGl/rOjymi5+sNLa94J3Zm7Ky2fZBJ0teUxvZzpmMKZ Fl13gzR0DdQnhGRxAnPileo1Ymj/SAK13g== X-Received: by 2002:a5d:4ccb:: with SMTP id c11mr872864wrt.324.1611255993206; Thu, 21 Jan 2021 11:06:33 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:32 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 08/25] hw/timer/cmsdk-apb-dualtimer: Add Clock input Date: Thu, 21 Jan 2021 19:06:05 +0000 Message-Id: <20210121190622.22000-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As the first step in converting the CMSDK_APB_DUALTIMER device to the Clock framework, add a Clock input. For the moment we do nothing with this clock; we will change the behaviour from using the pclk-frq property to using the Clock once all the users of this device have been converted to wire up the Clock. We take the opportunity to correct the name of the clock input to match the hardware -- the dual timer names the clock which drives the timers TIMCLK. (It does also have a 'pclk' input, which is used only for the register and APB bus logic; on the SSE-200 these clocks are both connected together.) This is a migration compatibility break for machines mps2-an385, mps2-an386, mps2-an500, mps2-an511, mps2-an505, mps2-an521, musca-a, musca-b1. Signed-off-by: Peter Maydell --- include/hw/timer/cmsdk-apb-dualtimer.h | 3 +++ hw/timer/cmsdk-apb-dualtimer.c | 7 +++++-- 2 files changed, 8 insertions(+), 2 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel diff --git a/include/hw/timer/cmsdk-apb-dualtimer.h b/include/hw/timer/cmsdk-apb-dualtimer.h index 08d9e6fa3d5..3adbb01dd34 100644 --- a/include/hw/timer/cmsdk-apb-dualtimer.h +++ b/include/hw/timer/cmsdk-apb-dualtimer.h @@ -17,6 +17,7 @@ * * QEMU interface: * + QOM property "pclk-frq": frequency at which the timer is clocked + * + Clock input "TIMCLK": clock (for both timers) * + sysbus MMIO region 0: the register bank * + sysbus IRQ 0: combined timer interrupt TIMINTC * + sysbus IRO 1: timer block 1 interrupt TIMINT1 @@ -28,6 +29,7 @@ #include "hw/sysbus.h" #include "hw/ptimer.h" +#include "hw/clock.h" #include "qom/object.h" #define TYPE_CMSDK_APB_DUALTIMER "cmsdk-apb-dualtimer" @@ -62,6 +64,7 @@ struct CMSDKAPBDualTimer { MemoryRegion iomem; qemu_irq timerintc; uint32_t pclk_frq; + Clock *timclk; CMSDKAPBDualTimerModule timermod[CMSDK_APB_DUALTIMER_NUM_MODULES]; uint32_t timeritcr; diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c index f6534241b94..781b496037b 100644 --- a/hw/timer/cmsdk-apb-dualtimer.c +++ b/hw/timer/cmsdk-apb-dualtimer.c @@ -25,6 +25,7 @@ #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/registerfields.h" +#include "hw/qdev-clock.h" #include "hw/timer/cmsdk-apb-dualtimer.h" #include "migration/vmstate.h" @@ -445,6 +446,7 @@ static void cmsdk_apb_dualtimer_init(Object *obj) for (i = 0; i < ARRAY_SIZE(s->timermod); i++) { sysbus_init_irq(sbd, &s->timermod[i].timerint); } + s->timclk = qdev_init_clock_in(DEVICE(s), "TIMCLK", NULL, NULL); } static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp) @@ -485,9 +487,10 @@ static const VMStateDescription cmsdk_dualtimermod_vmstate = { static const VMStateDescription cmsdk_apb_dualtimer_vmstate = { .name = "cmsdk-apb-dualtimer", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { + VMSTATE_CLOCK(timclk, CMSDKAPBDualTimer), VMSTATE_STRUCT_ARRAY(timermod, CMSDKAPBDualTimer, CMSDK_APB_DUALTIMER_NUM_MODULES, 1, cmsdk_dualtimermod_vmstate, From patchwork Thu Jan 21 19:06:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 367854 Delivered-To: patch@linaro.org Received: by 2002:a17:906:24d5:0:0:0:0 with SMTP id f21csp750430ejb; Thu, 21 Jan 2021 11:08:28 -0800 (PST) X-Google-Smtp-Source: ABdhPJyN6keVw35t2Spa7OeQNkq6vMo5Kdoo/kfEHr33EeDx9VPaUw3g4qhfuj3dE+3mBDv+BFYH X-Received: by 2002:a25:16c5:: with SMTP id 188mr1224208ybw.62.1611256108584; Thu, 21 Jan 2021 11:08:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611256108; cv=none; d=google.com; s=arc-20160816; b=V/wJY6XsMIe0SPkjHKYYGOdDOgX2VUrt/0fA12cqLt869jLgTH0mCaIz154l9eVfZI zRQ+5wqptnLWCb+/zGt3H/iLjYib3kMBlFyg7f2XWlcPRBH3pKZFNOMwJTGQwJM+y6W2 6hgLyCQ008LJBLAvwz4od9zftiKEUKATs2G4Y+Pbwv6GFLTMHbfWMlOLeXNsX0tc4XJP twg062bglRwGUWgRYR6PLJJCJDh0MAyNHBYIzpKwVMWmWtY8+ZSfGE4u69eNWFdaZ2AI 3S92OFTCoz4bZgsM+n4/OvIb9FPoEKajYZXYaViqfxACPqH6THh1hWa8LTkGff8JbcM8 lVsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=H+D/Gt7JsF9hn1kRelKr/4gM1Ewyi0uJ0hZ0lBf0vAM=; b=Dbh11jtGIIaiImxzCcGABg7C20Q0JjsZLWhGHHrSr9Ze+LoHpqPxl5kz8UcpT5yJiU kwJTcznuTj7i5M1E8SiU18YtqLbYcAQX9UgXIqObNeHHN3x9KCgKhWJqiDUzl7tuBGLt bAyQ2btBlQWOwuTaB87uqaBNgDWHw050E5TanZUdaQuat0ktFQOHnecyxL7EcclEz2sK 0M/CkiKhyHdTycwUFMZ8DN4DKnCahsKFSIEKAuqYzgmsAtnz/HHHlgpcE8CQ4FLZru4g iWirqD2mxsbtcBQ8lqUNqMcKKkEBQpkI5FZQwc5UpAgTA3qHCoylFoxmyFz0BaqfvKbf pNQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="u/LvHBnQ"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m132si5910733ybm.153.2021.01.21.11.08.28 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jan 2021 11:08:28 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="u/LvHBnQ"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60880 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2fJj-0003Yu-Nh for patch@linaro.org; Thu, 21 Jan 2021 14:08:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55718) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIE-0002IU-T5 for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:06:56 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:41147) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI0-0005oX-1i for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:06:53 -0500 Received: by mail-wr1-x434.google.com with SMTP id a12so2816392wrv.8 for ; Thu, 21 Jan 2021 11:06:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=H+D/Gt7JsF9hn1kRelKr/4gM1Ewyi0uJ0hZ0lBf0vAM=; b=u/LvHBnQzZEe8w8M/W6QpoL4pX8rxzdR7/8jMb2FIn0Vhh+UuayocOGuvRt8zMK+O+ koDEMcOrMS0lZ4gnfbvvXJErp0/i/NtYB0eu1h5KHzglCJfoSW60VkUZMk4NlWTGRp16 +OsXoDhxSTRVX+ZLZjFxinzhZt+QNuViCTvh1kIcSpe6I5SwqGJja77g9GNYKCe5YBZS xTO8YuRZ/QdcUA6u1UHDbl6v1dU/LWAdUQmWEsuwcXBUi8frIlN5S7dfBin/Zn1+FsqE pUra+PE4l/5h8V2OhRfc2SDWQaYDI6DpnOiIn9cM0yz5SlEqEbDRJkQ2jHEVQNqKZp6d aZ8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=H+D/Gt7JsF9hn1kRelKr/4gM1Ewyi0uJ0hZ0lBf0vAM=; b=CDNlSZh548jB1FB63zrV+XNSxHcUHjF/7gZPXBMe8oyZew6hYiErssggEJccqDOWw5 T/RwSq5LFReHzy8AOwhc0D3PpeDqgl1ROndPFE8zPWzX0/BePzsFrBErT1QCRmf50swn ot3Yw/tQtbeaJ3zOVt9nYJ9vsE5CEC9D3zClkNet094tTaO0ST74V8n7JzWjjrIybjh4 9RrYSC0ZSD4lNQ4xOGf/o2VCmmWrVA3/AaUgX197cTsFO7NN11KZdmju0gvu57DLcGgI mPq19VKB3LlvXOXWIhEMStxy2q8vBZ5fBvfpcSXiTstPREvtJrxvhHGyoqE+seqKGt3h +YbQ== X-Gm-Message-State: AOAM532o38yR5hesteCowENGTJYCIuoDvRSWGy/3zlg+wy1aCIBJfk/4 RKPDKSpOKgO8Bgfy1CVHZ32aFw== X-Received: by 2002:a5d:68ce:: with SMTP id p14mr896028wrw.386.1611255994104; Thu, 21 Jan 2021 11:06:34 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:33 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 09/25] hw/watchdog/cmsdk-apb-watchdog: Add Clock input Date: Thu, 21 Jan 2021 19:06:06 +0000 Message-Id: <20210121190622.22000-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As the first step in converting the CMSDK_APB_TIMER device to the Clock framework, add a Clock input. For the moment we do nothing with this clock; we will change the behaviour from using the wdogclk-frq property to using the Clock once all the users of this device have been converted to wire up the Clock. This is a migration compatibility break for machines mps2-an385, mps2-an386, mps2-an500, mps2-an511, mps2-an505, mps2-an521, musca-a, musca-b1, lm3s811evb, lm3s6965evb. Signed-off-by: Peter Maydell --- include/hw/watchdog/cmsdk-apb-watchdog.h | 3 +++ hw/watchdog/cmsdk-apb-watchdog.c | 7 +++++-- 2 files changed, 8 insertions(+), 2 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel diff --git a/include/hw/watchdog/cmsdk-apb-watchdog.h b/include/hw/watchdog/cmsdk-apb-watchdog.h index 3da0d43e355..34069ca6969 100644 --- a/include/hw/watchdog/cmsdk-apb-watchdog.h +++ b/include/hw/watchdog/cmsdk-apb-watchdog.h @@ -17,6 +17,7 @@ * * QEMU interface: * + QOM property "wdogclk-frq": frequency at which the watchdog is clocked + * + Clock input "WDOGCLK": clock for the watchdog's timer * + sysbus MMIO region 0: the register bank * + sysbus IRQ 0: watchdog interrupt * @@ -33,6 +34,7 @@ #include "hw/sysbus.h" #include "hw/ptimer.h" +#include "hw/clock.h" #include "qom/object.h" #define TYPE_CMSDK_APB_WATCHDOG "cmsdk-apb-watchdog" @@ -54,6 +56,7 @@ struct CMSDKAPBWatchdog { uint32_t wdogclk_frq; bool is_luminary; struct ptimer_state *timer; + Clock *wdogclk; uint32_t control; uint32_t intstatus; diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c index 5bbadadfa68..b03bcb73628 100644 --- a/hw/watchdog/cmsdk-apb-watchdog.c +++ b/hw/watchdog/cmsdk-apb-watchdog.c @@ -30,6 +30,7 @@ #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/registerfields.h" +#include "hw/qdev-clock.h" #include "hw/watchdog/cmsdk-apb-watchdog.h" #include "migration/vmstate.h" @@ -318,6 +319,7 @@ static void cmsdk_apb_watchdog_init(Object *obj) s, "cmsdk-apb-watchdog", 0x1000); sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->wdogint); + s->wdogclk = qdev_init_clock_in(DEVICE(s), "WDOGCLK", NULL, NULL); s->is_luminary = false; s->id = cmsdk_apb_watchdog_id; @@ -346,9 +348,10 @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp) static const VMStateDescription cmsdk_apb_watchdog_vmstate = { .name = "cmsdk-apb-watchdog", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { + VMSTATE_CLOCK(wdogclk, CMSDKAPBWatchdog), VMSTATE_PTIMER(timer, CMSDKAPBWatchdog), VMSTATE_UINT32(control, CMSDKAPBWatchdog), VMSTATE_UINT32(intstatus, CMSDKAPBWatchdog), From patchwork Thu Jan 21 19:06:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 367867 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp850407jam; Thu, 21 Jan 2021 11:26:25 -0800 (PST) X-Google-Smtp-Source: ABdhPJxhR64EGoZltDvKLuEfH5dnQinLZoEbKKRNgyU4GWb841tyjSgx7XWEFUpnof5dCP/1Npk1 X-Received: by 2002:a25:7b82:: with SMTP id w124mr1155146ybc.492.1611257185527; Thu, 21 Jan 2021 11:26:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611257185; cv=none; d=google.com; s=arc-20160816; b=NxbCAKwfBHR18wXuAPCms2DtUo9BI/vA2jJ1HXT3KtnQi6xYQdYujoYt6zBsLQQr/f Upq0HTVC5tdzWENSkO+wBD/7mkrq4hNxhtWRI+GtCLZlobK1q+BTWZftOEzAdnAEqvhB 82YtQz85I2cwgLOa2ds2/A3wFYALN7/QsfpYZfKxUE3HtzfDTJEx9ByN3YKA7lDk7Zgw duHFwVQJ6WU3K6Z3vKXaPzyZZj46wS4VoGA+m5ZFofARqp2kREg+z50fB2Apc8wKjnKB 8CDguJcbsIkErX0ZtSeQoYL+7iD1g/pKfANhaH6TInIy+fi0UzF10sh7lYn7swF57O5q PiEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8qYEJ7vFQTOhZhRO/AtRAFtnFxVNIz2T8FPyZBXE8CU=; b=ZmCveal24nDl/czxeMhnqB/UNIzd4QBUh2/IjsYyEroyE/sDhi4tXeN10JHMJE0NYI sOwVSQgh/XZkflm46LbgQ4e1Xdg6AqUHhOXu29AZaEDiZ/RMrLUsXNgg7mDHrUdIP40l 894A5U5EBDKHb/m3es6YE49gZTytEfjjMRVMGi7GfLdxhX+//OMf/wfA4S7c4CLAFcHN CFe7ZCzxWqhpjAwozmes4SSHqRb5kAGeeof2ORVfIExaGLMf1I27ngZurm8uUV/n+/Ox 8boNzSPX+2fadfOaHRooNyNqyFzVQ88TSORpLa/y6pbSrletT+cIDLKAotBJ5hxwRujo phRw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rq2x7PKz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 186si5769352ybl.414.2021.01.21.11.26.24 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jan 2021 11:26:25 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rq2x7PKz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41158 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2fb5-0003aj-LQ for patch@linaro.org; Thu, 21 Jan 2021 14:26:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55792) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIN-0002Oy-FV for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:03 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:52013) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI1-0005od-2Q for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:03 -0500 Received: by mail-wm1-x32c.google.com with SMTP id m2so2404787wmm.1 for ; Thu, 21 Jan 2021 11:06:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8qYEJ7vFQTOhZhRO/AtRAFtnFxVNIz2T8FPyZBXE8CU=; b=rq2x7PKzCDz83IUDc0edd0kgJTuBpexH0TnVe/OCkjZzPAqY9WrnD4/IuGCGFuVXJE Xj7ei0j7aPYJMKijAp9pldq0MvQvokHMWI8GrdgDFXMV+cQCF1bKtMu98QSJ/VrFB0PY vnXJBbUHWXpJyryN0xv1Ej896E75b+uR7ZDTov3ZiquH7+ShKwC17jb/+QwG8nrzyALS RqtaMlHhx3ka6UieK7Kz27HiTM4zQwA6WL6CzkPoW75K54OBk/QoYAGNz7STL04ux3vi blTglX95MhCZGeGQUHs8KSVR1SW+KDK8rWMb58MxpYHe5C8xNy31cAFIbvx4x0MR86Eb 26ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8qYEJ7vFQTOhZhRO/AtRAFtnFxVNIz2T8FPyZBXE8CU=; b=PplaooVjK69DE2orvsZTUGGzuZKpWHRkfAhUJnThDkwTJltDG4BgLWTjOttLGd3XOf l0Wld2NVrgI8fkwByKJh1FEDGmOkZdmziXbi8I3IaEWXtpQYxPEy2UOtEDe/0dfkmWIF wlsxeRA8zC8NTt7SCu6KQ/VMMQQ4r7vbf64voINqtvoe8aL17m2IAXbKtjFcij8HmCTy 0nwry3tmziGcMH6+uCnKFCB2PaWTfG8OEJQmkBPClI4LiPGXlY1cru/GEY0DYpPI+5B0 3iwZsHnBI5i38UKf1PvW6RYRyVFz0CNavR2fpxHoW0RHD/atLn+vdxOWd+vQduwOfbW2 RDNw== X-Gm-Message-State: AOAM530BIckRIe7vds/OC7KK6jGKqX7FT4CPnQtvFJ2tNqOwwVlIBBkX q6BbOTZlI4tuiQpi8ORapnj6gQ== X-Received: by 2002:a1c:e902:: with SMTP id q2mr690920wmc.143.1611255995115; Thu, 21 Jan 2021 11:06:35 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:34 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 10/25] hw/arm/armsse: Rename "MAINCLK" property to "MAINCLK_FRQ" Date: Thu, 21 Jan 2021 19:06:07 +0000 Message-Id: <20210121190622.22000-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While we transition the ARMSSE code from integer properties specifying clock frequencies to Clock objects, we want to have the device provide both at once. We want the final name of the main input Clock to be "MAINCLK", following the hardware name. Unfortunately creating an input Clock with a name X creates an under-the-hood QOM property X; for "MAINCLK" this clashes with the existing UINT32 property of that name. Rename the UINT32 property to MAINCLK_FRQ so it can coexist with the MAINCLK Clock; once the transition is complete MAINCLK_FRQ will be deleted. Commit created with: perl -p -i -e 's/MAINCLK/MAINCLK_FRQ/g' hw/arm/{armsse,mps2-tz,musca}.c include/hw/arm/armsse.h Signed-off-by: Peter Maydell --- include/hw/arm/armsse.h | 2 +- hw/arm/armsse.c | 6 +++--- hw/arm/mps2-tz.c | 2 +- hw/arm/musca.c | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 83f5e28c16e..4860a793f4b 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -39,7 +39,7 @@ * QEMU interface: * + QOM property "memory" is a MemoryRegion containing the devices provided * by the board model. - * + QOM property "MAINCLK" is the frequency of the main system clock + * + QOM property "MAINCLK_FRQ" is the frequency of the main system clock * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts. * (In hardware, the SSE-200 permits the number of expansion interrupts * for the two CPUs to be configured separately, but we restrict it to diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index baac027659d..d2ba0459c44 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -47,7 +47,7 @@ static Property iotkit_properties[] = { DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), - DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), + DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0), DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), @@ -59,7 +59,7 @@ static Property armsse_properties[] = { DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), - DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), + DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0), DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false), @@ -448,7 +448,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) } if (!s->mainclk_frq) { - error_setg(errp, "MAINCLK property was not set"); + error_setg(errp, "MAINCLK_FRQ property was not set"); return; } diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 3707876d6d4..6a9eed9022a 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -402,7 +402,7 @@ static void mps2tz_common_init(MachineState *machine) object_property_set_link(OBJECT(&mms->iotkit), "memory", OBJECT(system_memory), &error_abort); qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ); - qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ); + qdev_prop_set_uint32(iotkitdev, "MAINCLK_FRQ", SYSCLK_FRQ); sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); /* diff --git a/hw/arm/musca.c b/hw/arm/musca.c index b50157f63a6..d82bef11cf2 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -375,7 +375,7 @@ static void musca_init(MachineState *machine) qdev_prop_set_uint32(ssedev, "EXP_NUMIRQ", mmc->num_irqs); qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor); qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); - qdev_prop_set_uint32(ssedev, "MAINCLK", SYSCLK_FRQ); + qdev_prop_set_uint32(ssedev, "MAINCLK_FRQ", SYSCLK_FRQ); /* * Musca-A takes the default SSE-200 FPU/DSP settings (ie no for * CPU0 and yes for CPU1); Musca-B1 explicitly enables them for CPU0. From patchwork Thu Jan 21 19:06:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 367860 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp845322jam; Thu, 21 Jan 2021 11:18:04 -0800 (PST) X-Google-Smtp-Source: ABdhPJzQb1XmdMH4SzMag4mYhz8bCaQD/2VQtpfJ0+udWQ95nWn6TCvctFpAgcxVl/LMAX0wtL3C X-Received: by 2002:a25:5c44:: with SMTP id q65mr1154772ybb.394.1611256684914; Thu, 21 Jan 2021 11:18:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611256684; cv=none; d=google.com; s=arc-20160816; b=PCsEm8WSSOu/hev71u8KuVIlK+QaJDbvPuv4e3YfhkjLMIBN0qNff/fjgqpsvt21x+ z/ZY9kwqqTbtL+ly/iiQphKVydHxqrxjGGsPBMryAjQVW+XzzqfBjEg4Sy2oPdhcO1uv eCqwu0Vq2NvCUl99IraJvrqwLocQdGPjKXOv5hBthzZQZ8TUAy9wU1hla0UyZh1mZx8l +TtsqqZHWyl91RCusxXCvgD9RVSWznRCGuUAGRRqsKL0qm+ZU0U+JDrQV+htuHaFucLG RIyBCIKW4DxtFGHvnEKzDoPnJ0YqBoy5DVUG1MbuevkUwr1NfrUOj9aeiudU1U+NvfAP 1e7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NEZ5U7Po5BeujzVL1PMxzLMD8dogU0kUTKX4d32S7Mw=; b=z0BHPtCABNbjS1Xnjz0/GE23clx1jEeVqXu23cUiqO+l5CuEZC0hHtrkJEl5K7h+ON WXBHNLMCwKs5HCjLvR5qUqzfhJhUHOFmgKgKSulrGWjfnsZnG/0yBQkFQnUq4m5jdDRe GKWQTvf2pxrLz46GvOHTsPysRpjXmqr//lw3ZhlfMplrFCEpJxCpNfZyhbIHjXoDcno9 QczDU8NJh+zGqT/mIASTgcxcicY3K6in3VcUcBrRp2DjupInLHv1KRRXUU1tRcgFZdma 5TgL3m3ag5VAoDnI8xIFjk0TRHIMi43qa13WwHw6DbLLxuykOXHRTn6qEAjDa0MzA234 okgQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yae5CO8P; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id i195si5828442yba.91.2021.01.21.11.18.04 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jan 2021 11:18:04 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yae5CO8P; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51670 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2fT2-0004Sm-9G for patch@linaro.org; Thu, 21 Jan 2021 14:18:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55660) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIB-0002H6-1N for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:06:52 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:36708) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fHz-0005pM-Gg for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:06:49 -0500 Received: by mail-wr1-x430.google.com with SMTP id 6so2824931wri.3 for ; Thu, 21 Jan 2021 11:06:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NEZ5U7Po5BeujzVL1PMxzLMD8dogU0kUTKX4d32S7Mw=; b=yae5CO8Pdpe1iCQd1WZYhi23ZllqMFL4g+A/13mTrfun9hlfzhyBy9VEID5WM+0bch z5dZrEquwThQ8AMai651EEcttcY8H5VpXgGklpP/Xm+Y8hEL2b6LYnhHruluNcGbjp0o 0Bzc5efxuTDU3gjZzlNDXBD5JMfwUl0ZkWKLhUqPxCdfDkyzp986+1B8EPupdOIW6HSd 85ack7jonZnobQ0reN+jFjzZubW7ZZbZ+oyKJIechoCaFfC5dO2pz0u9NszdGutg63dx uHSThFO+kPVbt6B9KbXE+x31/QFC1sCo1rhvFSTKK0bq7MhHtmuxgcTaHM+nS4uENQ5g riNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NEZ5U7Po5BeujzVL1PMxzLMD8dogU0kUTKX4d32S7Mw=; b=bpaGJ57aFSryszjHAKvg22sCGQy8nkrh/p+akdPqEbxYM67H8tzopebW9vTY16HIvk 2WrgIXJ0TRtpM0b8l1TL2gxtOIMJvy99lqQ5vHkBXhvqfjdw11k8CatNXHMF83nLagZZ QdbwrOCeXrVWS6V+aFBo5jQF3begIvLLiJOQ+xENftkevVrxKh40TOjO3LPX8SS1oIsc KcDeUykoSSQsET1Aq4N9Fy0mOVMQCVra/gGS/4qKE26wNDpXUg8q6myJh0z+RHZK2216 IJp79eTmghxNhUfrrU7uLadZ8XnM4OuVLNJggZ34G0LNkTsecyT29L7BDkrSK3sUCvk4 xslw== X-Gm-Message-State: AOAM531QZwqFvzK7lpl5Io4FhNrjYraTAoGykOcammY5lQ10pkmw177m +jOoAvQ1Uc6QnskOIxfLKBFFJg== X-Received: by 2002:adf:8285:: with SMTP id 5mr847952wrc.289.1611255996081; Thu, 21 Jan 2021 11:06:36 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:35 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 11/25] hw/arm/armsse: Wire up clocks Date: Thu, 21 Jan 2021 19:06:08 +0000 Message-Id: <20210121190622.22000-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create two input clocks on the ARMSSE devices, one for the normal MAINCLK, and one for the 32KHz S32KCLK, and wire these up to the appropriate devices. The old property-based clock frequency setting will remain in place until conversion is complete. This is a migration compatibility break for machines mps2-an505, mps2-an521, musca-a, musca-b1. Signed-off-by: Peter Maydell --- include/hw/arm/armsse.h | 6 ++++++ hw/arm/armsse.c | 17 +++++++++++++++-- 2 files changed, 21 insertions(+), 2 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 4860a793f4b..bfa1e79c4fe 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -37,6 +37,8 @@ * per-CPU identity and control register blocks * * QEMU interface: + * + Clock input "MAINCLK": clock for CPUs and most peripherals + * + Clock input "S32KCLK": slow 32KHz clock used for a few peripherals * + QOM property "memory" is a MemoryRegion containing the devices provided * by the board model. * + QOM property "MAINCLK_FRQ" is the frequency of the main system clock @@ -103,6 +105,7 @@ #include "hw/misc/armsse-mhu.h" #include "hw/misc/unimp.h" #include "hw/or-irq.h" +#include "hw/clock.h" #include "hw/core/split-irq.h" #include "hw/cpu/cluster.h" #include "qom/object.h" @@ -209,6 +212,9 @@ struct ARMSSE { uint32_t nsccfg; + Clock *mainclk; + Clock *s32kclk; + /* Properties */ MemoryRegion *board_memory; uint32_t exp_numirq; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index d2ba0459c44..4349ce9bfdb 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -21,6 +21,7 @@ #include "hw/arm/armsse.h" #include "hw/arm/boot.h" #include "hw/irq.h" +#include "hw/qdev-clock.h" /* Format of the System Information block SYS_CONFIG register */ typedef enum SysConfigFormat { @@ -241,6 +242,9 @@ static void armsse_init(Object *obj) assert(info->sram_banks <= MAX_SRAM_BANKS); assert(info->num_cpus <= SSE_MAX_CPUS); + s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", NULL, NULL); + s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL); + memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); for (i = 0; i < info->num_cpus; i++) { @@ -711,6 +715,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) * map its upstream ends to the right place in the container. */ qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq); + qdev_connect_clock_in(DEVICE(&s->timer0), "pclk", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer0), errp)) { return; } @@ -721,6 +726,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) &error_abort); qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq); + qdev_connect_clock_in(DEVICE(&s->timer1), "pclk", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer1), errp)) { return; } @@ -731,6 +737,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) &error_abort); qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq); + qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) { return; } @@ -889,6 +896,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) * 0x4002f000: S32K timer */ qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK); + qdev_connect_clock_in(DEVICE(&s->s32ktimer), "pclk", s->s32kclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) { return; } @@ -982,6 +990,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK); + qdev_connect_clock_in(DEVICE(&s->s32kwatchdog), "WDOGCLK", s->s32kclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), errp)) { return; } @@ -992,6 +1001,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */ qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq); + qdev_connect_clock_in(DEVICE(&s->nswatchdog), "WDOGCLK", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), errp)) { return; } @@ -1000,6 +1010,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000); qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_frq); + qdev_connect_clock_in(DEVICE(&s->swatchdog), "WDOGCLK", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), errp)) { return; } @@ -1127,9 +1138,11 @@ static void armsse_idau_check(IDAUInterface *ii, uint32_t address, static const VMStateDescription armsse_vmstate = { .name = "iotkit", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { + VMSTATE_CLOCK(mainclk, ARMSSE), + VMSTATE_CLOCK(s32kclk, ARMSSE), VMSTATE_UINT32(nsccfg, ARMSSE), VMSTATE_END_OF_LIST() } From patchwork Thu Jan 21 19:06:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 367873 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp853991jam; Thu, 21 Jan 2021 11:31:41 -0800 (PST) X-Google-Smtp-Source: ABdhPJyTx35GznKzaamI1WwWbguZHCaiCHDp4pZtlMOTYpVn4l3qBs4xPHWNVOrEwkvtdh3TPNQk X-Received: by 2002:a25:5f12:: with SMTP id t18mr1347640ybb.308.1611257500846; Thu, 21 Jan 2021 11:31:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611257500; cv=none; d=google.com; s=arc-20160816; b=Y4VUYsg+E09dbN5dv/Lj4vQXRkV9rYYQN7CDrLP1pMmg9BcfHmteJXMhI+aIuVihRF OMbkalt6yQ0unoiRd0jcelUGE5GG5irxCpksRANYUlT+DTSz956fEi7RC39nJE6+rczs fdXffuJdG6vVpjf3+day8m0Fdl7MoZzALKOY3J6mxqTfUjPSH+MRpfSI6m9xFRubK98n GM6S/OmayAJpRoi+5tr1imreUUCh8JpFV9+qcBsgJY9XB6NTaoQ5t0Xt7LOQ9lJu/df/ 277C7Hd4hAfWuyoIMaW3atufK1v2PWHT8BPWfh8hKhManNAbOMcP9zC9e26M94k8qDjN 7fHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=71fXmSxG4SGO/lxGONnTuENMy4+MVUOt7YwIy8LfeBo=; b=TLNue/M+aNFNm4z5EwsufQQ7jBP9JGJrgcesRkxOshtkxSKGHtGSbTTW321EEH8PZr 5ie/FnVO3Z0yp12g6gbQpOT5SBxjKJjL0iTsxvsmS29Mg6LlmHYjMrmmZbe0GW7j2kRb wlcl8KzXMoy81f6AeNI6W/ZVHP6LjFPx97o40LSiNV6BzdgHT3UFPlC921/QMHbcP0PY qA7jrHbdcavBvS0GZVXIwmkl18O0ae2N6wmrmlhxeX973TZ1k69KR628OBEqsZasCger l7u8sa3WU9kxKBARxD1ntydY4Xi281djT1oZHRzcCeT/EB5st3oFrvIny6AANPhzciGL lbPQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gye4933k; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n4si6412642ybc.282.2021.01.21.11.31.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jan 2021 11:31:40 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gye4933k; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52894 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2fgC-0000DP-6V for patch@linaro.org; Thu, 21 Jan 2021 14:31:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55790) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIN-0002Om-Eg for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:03 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:40588) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI1-0005pU-0e for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:03 -0500 Received: by mail-wm1-x32e.google.com with SMTP id c127so2435204wmf.5 for ; Thu, 21 Jan 2021 11:06:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=71fXmSxG4SGO/lxGONnTuENMy4+MVUOt7YwIy8LfeBo=; b=gye4933kAc2ne7YO71GYHXD59s2FPYqiDoWpqU3dzr5tETDWrm5S+CVr75TOFVOsJC rLHf1+fV/40Fbh35e3dI2rQH51mk9grziKBKVaZmPQgnwvXbw2HDPek9KadtEEVpcZwL vfyJGzQCABdjOiX+gc96aM/7bNuYR4a2SyNaibKB/YDeThJiMrKvbeZQKls9vN/H5EiZ 4UyTxSHdiHL8sXnlQEO8zkEtiYQGkpBmg47muvvervCcaykQYfFpV737Bg06UXlHKeMC 1xP08o24dZKDu466+vQXsZylv+i1ktZrDsfomuiAj2SkYunsV29yIjo9OMVCvc0SqUaW tZIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=71fXmSxG4SGO/lxGONnTuENMy4+MVUOt7YwIy8LfeBo=; b=TPc2htyiIvynHkh2SqPmIy8zA7uIwsQ5fFtPBntiILBP1Wey2MkFQ1arVuX+M9+Y3q eCjphkjzL2iyfWgLr4UxfS1MS0uAvB4pBFYG07RZv5G2TgleAmiSG0wdXEQCcFPzMb6v VwwttDKKg6Hp7JvwEOqP14VcDbc1ek6WDySmS9pYduK29kk7Cu0QYAYcidWa9mquPr1w IEUFJAuwnVeW16V4wDAsS8Jajw5rDRR4QXf1NW4Y++usPDl6VdTKp/y+Dvf0jFdjQ/UK iBhkHkaBEJuzz+RJvxRkPxV0MeI6IEy2G7eMPH73q8Jr+DkSgiTJ8Ar6yhz8VdCMtZIo 2FBA== X-Gm-Message-State: AOAM533p+9gsSMwLu7ju8pek3OnfBwpgC2U58YgRPdOAeX3sUqLqUpyJ 5qsQaiogSYya2XAC8DX0+YJCeA== X-Received: by 2002:a1c:7f94:: with SMTP id a142mr690186wmd.145.1611255996983; Thu, 21 Jan 2021 11:06:36 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:36 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 12/25] hw/arm/mps2: Inline CMSDK_APB_TIMER creation Date: Thu, 21 Jan 2021 19:06:09 +0000 Message-Id: <20210121190622.22000-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The old-style convenience function cmsdk_apb_timer_create() for creating CMSDK_APB_TIMER objects is used in only two places in mps2.c. Most of the rest of the code in that file uses the new "initialize in place" coding style. We want to connect up a Clock object which should be done between the object creation and realization; rather than adding a Clock* argument to the convenience function, convert the timer creation code in mps2.c to the same style as is used already for the watchdog, dualtimer and other devices, and delete the now-unused convenience function. Signed-off-by: Peter Maydell --- include/hw/timer/cmsdk-apb-timer.h | 21 --------------------- hw/arm/mps2.c | 18 ++++++++++++++++-- 2 files changed, 16 insertions(+), 23 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h index fc2aa97acac..54f7ec8c502 100644 --- a/include/hw/timer/cmsdk-apb-timer.h +++ b/include/hw/timer/cmsdk-apb-timer.h @@ -45,25 +45,4 @@ struct CMSDKAPBTimer { uint32_t intstatus; }; -/** - * cmsdk_apb_timer_create - convenience function to create TYPE_CMSDK_APB_TIMER - * @addr: location in system memory to map registers - * @pclk_frq: frequency in Hz of the PCLK clock (used for calculating baud rate) - */ -static inline DeviceState *cmsdk_apb_timer_create(hwaddr addr, - qemu_irq timerint, - uint32_t pclk_frq) -{ - DeviceState *dev; - SysBusDevice *s; - - dev = qdev_new(TYPE_CMSDK_APB_TIMER); - s = SYS_BUS_DEVICE(dev); - qdev_prop_set_uint32(dev, "pclk-frq", pclk_frq); - sysbus_realize_and_unref(s, &error_fatal); - sysbus_mmio_map(s, 0, addr); - sysbus_connect_irq(s, 0, timerint); - return dev; -} - #endif diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 9a8b23c64ce..f762d1b46af 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -83,6 +83,7 @@ struct MPS2MachineState { /* CMSDK APB subsystem */ CMSDKAPBDualTimer dualtimer; CMSDKAPBWatchdog watchdog; + CMSDKAPBTimer timer[2]; }; #define TYPE_MPS2_MACHINE "mps2" @@ -330,8 +331,21 @@ static void mps2_common_init(MachineState *machine) } /* CMSDK APB subsystem */ - cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ); - cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ); + for (i = 0; i < ARRAY_SIZE(mms->timer); i++) { + g_autofree char *name = g_strdup_printf("timer%d", i); + hwaddr base = 0x40000000 + i * 0x1000; + int irqno = 8 + i; + SysBusDevice *sbd; + + object_initialize_child(OBJECT(mms), name, &mms->timer[i], + TYPE_CMSDK_APB_TIMER); + sbd = SYS_BUS_DEVICE(&mms->timer[i]); + qdev_prop_set_uint32(DEVICE(&mms->timer[i]), "pclk-frq", SYSCLK_FRQ); + sysbus_realize_and_unref(sbd, &error_fatal); + sysbus_mmio_map(sbd, 0, base); + sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(armv7m, irqno)); + } + object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer, TYPE_CMSDK_APB_DUALTIMER); qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ); From patchwork Thu Jan 21 19:06:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 367872 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp852571jam; Thu, 21 Jan 2021 11:30:03 -0800 (PST) X-Google-Smtp-Source: ABdhPJx3sTLsIhrg0GQS+J9mC4t2MYJtswpKy66z+1i2cHEkYq3Yy28dq59WfPAtiSTYa/RB7taM X-Received: by 2002:a25:40c5:: with SMTP id n188mr1450842yba.398.1611257403605; Thu, 21 Jan 2021 11:30:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611257403; cv=none; d=google.com; s=arc-20160816; b=faDhXawhu1kDAlLX0u9nO+lZEDA9wghRjcJbbPdG7Q+Bd8iQTVayDk2Kw0b0WzJCV+ cg4lmA6MFGAoVf/jMsFXAEDan1wiJOJucF3LRVdL4PcTm4ldK4A4oD2kSqUUwKc49GGp fz/qOKx0IKG7gkoOFIOKHTkFcWNQJ7wcD4S7uzG0ggH5O1Qd+0tUHQskAA5BZP8hAGTb 3HaRlwsiQ+CjKk8/SCiJUuhgaIELyQOR9rbB7e6hiCTE26HzrukOiTPJvM26a/XCnrVH lCm8aMrwyaUJrFIN8ymxgw7x5d8jFpJh9f1cmAlThps+MY968pYSuPoFW1afPwEIMZqR Y4tA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=HsBmuYHOmkArh8+q9PdOyKcEeylmhF/poYkrDZaJKS8=; b=uhdFaCjDJJ/89wORSbfWHBwnkJUMUqWLKz3uMalNoZqYDMGiYrKDYp9Ng13DvrpK0d yflqmauDStCi4GmEAY8CK0rW3D82JM9ffk28aI9w6CduvQO8w99NJQB2gStUqG0bzM9N wk6vNXavWIIODBb6zGBwoTMStkvHn6eWR4117yV7gpySPU6FA2s7rwHzKYEvndMuInJ4 gbG80OPGDoaDn9AS5+Ux9CsslRB7/Y4PAweYBwEzDw7/wd3dRTrIjwDdOo5csCZFmptj dC9/M2r2tS+ygfiFFcvxujCKSaFOpnxw2t8R9enHloTCzyUqOWPyUm8gubtsnWIr0QHp Cq+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yisn4cUG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w5si5509796ybo.210.2021.01.21.11.30.03 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jan 2021 11:30:03 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yisn4cUG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50742 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2fed-0007Zb-19 for patch@linaro.org; Thu, 21 Jan 2021 14:30:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55824) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIO-0002QL-BU for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:04 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:32901) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI1-0005pe-3G for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:04 -0500 Received: by mail-wr1-x436.google.com with SMTP id 7so2831345wrz.0 for ; Thu, 21 Jan 2021 11:06:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HsBmuYHOmkArh8+q9PdOyKcEeylmhF/poYkrDZaJKS8=; b=yisn4cUGdww2SlwDR5c54nQMqTTYh8EOQhrsJdfyPmvpyRwCE4n9L7WBTuUtLtCA3C WOYyIvqlt49QfbiliXLikJBY8lUhhUi/1TPb98YY5RYpUUXHg39iN4RgC8ZuuQoYzwS1 8E4yWg5nDiapQt03a3FT35rlSoWzWIVpL7xut+bnmMs+/tDyeOUhEe7lq1t2XZKyNwTu P3amsZQnvd6TFsZPQXZ5ht9fmyFYuQtDlmdzPicSkT8s6qZS4lWElGFNDUOYj+WQsoq9 4V1rqC/6OgbVHtBm+OJtevMXKPxxFXz+WjlN99igzXoo5Bthw1EstlGNvFmvqsqowCq/ RZWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HsBmuYHOmkArh8+q9PdOyKcEeylmhF/poYkrDZaJKS8=; b=FCxpzEJTAzwWBMrCqkO2v6pBR/MrX+3J3NMMjLIHhRtwAdS5lVy4Oxv+WtnG9uiCxF SrWEt+IdvVQIemY/XQgOz0vJqAd+zt4hiQQC1KHPPVC5YxOMY3jg2LK4VImZWvnu29q8 nvQaZ9urxojV/sNaUYxGwwLdYi4vkKhMIddP2iFGBN7Ki0AQgsO9FDAcn2+M+BtU92ix DHaM7TsbVUKhxoAlzIHRMwKraqgpAgMezXjjmj6z8LrqbYov8ldsnvhG/8w2+0xs0avh GGPUoRUutEDskRCBF/xNwhDIFB/Phrqn7E+psumz+Hy0OS5OcUEy/iSWx7tQ5T3g9IJd BeCA== X-Gm-Message-State: AOAM532iLBh1x/+uBgd6cFK3Yk0+M01kKGYvqFfcUeWxduTaFG94rrxS fPJ3dcC5c1lNkr1TZQ9VGHWqwg== X-Received: by 2002:adf:f512:: with SMTP id q18mr900026wro.55.1611255997892; Thu, 21 Jan 2021 11:06:37 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:37 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 13/25] hw/arm/mps2: Create and connect SYSCLK Clock Date: Thu, 21 Jan 2021 19:06:10 +0000 Message-Id: <20210121190622.22000-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a fixed-frequency Clock object to be the SYSCLK, and wire it up to the devices that require it. Signed-off-by: Peter Maydell --- hw/arm/mps2.c | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index f762d1b46af..cd1c215f941 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -46,6 +46,7 @@ #include "hw/net/lan9118.h" #include "net/net.h" #include "hw/watchdog/cmsdk-apb-watchdog.h" +#include "hw/qdev-clock.h" #include "qom/object.h" typedef enum MPS2FPGAType { @@ -84,6 +85,7 @@ struct MPS2MachineState { CMSDKAPBDualTimer dualtimer; CMSDKAPBWatchdog watchdog; CMSDKAPBTimer timer[2]; + Clock *sysclk; }; #define TYPE_MPS2_MACHINE "mps2" @@ -140,6 +142,10 @@ static void mps2_common_init(MachineState *machine) exit(EXIT_FAILURE); } + /* This clock doesn't need migration because it is fixed-frequency */ + mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); + clock_set_hz(mms->sysclk, SYSCLK_FRQ); + /* The FPGA images have an odd combination of different RAMs, * because in hardware they are different implementations and * connected to different buses, giving varying performance/size @@ -341,6 +347,7 @@ static void mps2_common_init(MachineState *machine) TYPE_CMSDK_APB_TIMER); sbd = SYS_BUS_DEVICE(&mms->timer[i]); qdev_prop_set_uint32(DEVICE(&mms->timer[i]), "pclk-frq", SYSCLK_FRQ); + qdev_connect_clock_in(DEVICE(&mms->timer[i]), "pclk", mms->sysclk); sysbus_realize_and_unref(sbd, &error_fatal); sysbus_mmio_map(sbd, 0, base); sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(armv7m, irqno)); @@ -349,6 +356,7 @@ static void mps2_common_init(MachineState *machine) object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer, TYPE_CMSDK_APB_DUALTIMER); qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ); + qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->sysclk); sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal); sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0, qdev_get_gpio_in(armv7m, 10)); @@ -356,6 +364,7 @@ static void mps2_common_init(MachineState *machine) object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog, TYPE_CMSDK_APB_WATCHDOG); qdev_prop_set_uint32(DEVICE(&mms->watchdog), "wdogclk-frq", SYSCLK_FRQ); + qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->sysclk); sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal); sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0, qdev_get_gpio_in_named(armv7m, "NMI", 0)); From patchwork Thu Jan 21 19:06:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 367865 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp849093jam; Thu, 21 Jan 2021 11:24:01 -0800 (PST) X-Google-Smtp-Source: ABdhPJytpeUceKOfE/1WFCV1QUajlwoG7triaWb/JoLHrtJyBPfEQJdBteCDDliNOizNBrTYP28g X-Received: by 2002:a25:af50:: with SMTP id c16mr1312601ybj.10.1611257041037; Thu, 21 Jan 2021 11:24:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611257041; cv=none; d=google.com; s=arc-20160816; b=Xf0y8MufWto+P669ewv8Z9ohrPx8tvJBRC9kRb8XBGouLJMuOBJfe2fHuf8kcnkMKZ pvgpTf+ywPVQVpcTu78fZ6CvjRGmfSCqMIS2LGdRaYeVGh1v5d6dOaPkFjaVf8BPfi9L cvddExHZZ9tRSJllRazj/yh0pIp4HkYbggHPk8OoNd695b4ehd3x/rasvsCtWax4jEqh 02yZoVXhsRM4Ey9mCoEuphgnqm6pJr36xNBL50qVh9UO7Y6VDhI6W7OSYCISQ/HPWhbd G7a9POOhc8INIsEd9vRlQov0NuSwYrdiOjNHkM/WzDXdQCopjrTeS+boDAmqLzcKAkTv Zmag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Z/cipOte9qBYkDz6GvPRQ6o8HFNldLG8VuXdickyLI0=; b=Rx51vfiBkZXxf5I2r0AyxzDKwDyskM44TAEdwG/mj2mDDXjJSTeulG0P2O7pjka2wy /C93BxG4VZuB5tloIS3b8WwzXZ5jn6OCfBlCJWLEF8cPw2QnYkGaflPajzI17+PMX9Uc F8jSkjVGL30Nq218LITiX0DGHDTkJ0nGnwbxLXh81Jt1yzYhMqLnY6OZNhBHLefCKoNr JmIXKLygAdB66t97prWHlOgK6EzTm8Qh5eLawH2llS+2wEupSMMfGSxfmNKcfRtpUwjH kD2PdPYfq8xtzr7JOkPrMDd5V8En3WYPOs61Zl4ilysFx0v3RLRC1KiaRIb4qjzHPhMB FfUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=oWQf5mXQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z5si6668812ybh.293.2021.01.21.11.24.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jan 2021 11:24:01 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=oWQf5mXQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35198 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2fYm-000115-Hj for patch@linaro.org; Thu, 21 Jan 2021 14:24:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55786) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIN-0002Nt-33 for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:03 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:36223) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI1-0005qK-2g for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:02 -0500 Received: by mail-wm1-x332.google.com with SMTP id v184so2445481wma.1 for ; Thu, 21 Jan 2021 11:06:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z/cipOte9qBYkDz6GvPRQ6o8HFNldLG8VuXdickyLI0=; b=oWQf5mXQjxxvNIvb4Vaxap6AVWNDVlMKT+WWVO2mo9tc1gY0eby3GoYw3X8XfVN74Y nQ6fuO4uAV7UsGcYnXNLQposNWFbqizkA9je55Eq/4hNS0qukhUp7XjGxqP/adIK5yhQ 4zYpvbQ1jPkqV73THeoIkWrMVM6O0ab7hADHX8zeHgZrFHCtZqQ83np4KlnpvEthekil IZ5P3/xlhHZN2WxKhJQCs0Veh7dgu1HLg4SNq0U4Iy9WTYNl1CSxnEACe0HFGTNHSG5O 1H+mp0Mj5e6T5Wg5h0fpJv7D5pUuNyUhRU1TRrs0MSNv3LWbZsL0toT4/0acnWtY7r/l Pypg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z/cipOte9qBYkDz6GvPRQ6o8HFNldLG8VuXdickyLI0=; b=uDQ0WZkxkyyxQ3R+3IE9PhQTsCN+v5PY02UA1IifRbYSEC9NSFYOCb9nUbwJNI8png 7rXAG1xlvRuUEmMPu1Nx+ZPN9zoo3SkuPtcSIT72vQu65XTfGN7M5s3fzL3833vtCvEU cjqV+fTTW1HqLWr5VMfu81UR2sn2f4TmV8h6edy5URdHb3kSHJDuP+1arlT3DHNAvQ1g g8rHkrAHLMDd7mZXxAnYE4LPHpnF2PKNYo7RRTRsw8m7psVOWD3XypsGhVEm26oQpcwJ Oc3nsODjtmLbQ2wjfIV75Am6OGNWsaDRp85m8f1Zsq84CsRfjWV3vvbACwlkKXFgKwmA snpw== X-Gm-Message-State: AOAM530fR23yz4BBvyABhIcZnzX+WMX+AJ+4r+86WNkNk/9mmxr47VHJ xtq2ouOfQWRDiL2cuQEzTI+odw== X-Received: by 2002:a1c:de09:: with SMTP id v9mr790569wmg.0.1611255998800; Thu, 21 Jan 2021 11:06:38 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:38 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 14/25] hw/arm/mps2-tz: Create and connect ARMSSE Clocks Date: Thu, 21 Jan 2021 19:06:11 +0000 Message-Id: <20210121190622.22000-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create and connect the two clocks needed by the ARMSSE. Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 6a9eed9022a..7acdf490f28 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -62,6 +62,7 @@ #include "hw/net/lan9118.h" #include "net/net.h" #include "hw/core/split-irq.h" +#include "hw/qdev-clock.h" #include "qom/object.h" #define MPS2TZ_NUMIRQ 92 @@ -100,6 +101,8 @@ struct MPS2TZMachineState { qemu_or_irq uart_irq_orgate; DeviceState *lan9118; SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ]; + Clock *sysclk; + Clock *s32kclk; }; #define TYPE_MPS2TZ_MACHINE "mps2tz" @@ -110,6 +113,8 @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) /* Main SYSCLK frequency in Hz */ #define SYSCLK_FRQ 20000000 +/* Slow 32Khz S32KCLK frequency in Hz */ +#define S32KCLK_FRQ (32 * 1000) /* Create an alias of an entire original MemoryRegion @orig * located at @base in the memory map. @@ -396,6 +401,12 @@ static void mps2tz_common_init(MachineState *machine) exit(EXIT_FAILURE); } + /* These clocks don't need migration because they are fixed-frequency */ + mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); + clock_set_hz(mms->sysclk, SYSCLK_FRQ); + mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK"); + clock_set_hz(mms->s32kclk, S32KCLK_FRQ); + object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit, mmc->armsse_type); iotkitdev = DEVICE(&mms->iotkit); @@ -403,6 +414,8 @@ static void mps2tz_common_init(MachineState *machine) OBJECT(system_memory), &error_abort); qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ); qdev_prop_set_uint32(iotkitdev, "MAINCLK_FRQ", SYSCLK_FRQ); + qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); + qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); /* From patchwork Thu Jan 21 19:06:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 367857 Delivered-To: patch@linaro.org Received: by 2002:a17:906:24d5:0:0:0:0 with SMTP id f21csp753092ejb; Thu, 21 Jan 2021 11:12:13 -0800 (PST) X-Google-Smtp-Source: ABdhPJyEYQBgDlATgGDQ1Xx/fSAnN5N1GLKqeSbxwoqYXBgBbZvfd1edmd+LbYK3y45W2u/9TjEp X-Received: by 2002:a5b:38c:: with SMTP id k12mr1145585ybp.441.1611256333052; Thu, 21 Jan 2021 11:12:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611256333; cv=none; d=google.com; s=arc-20160816; b=sIapG88WCvYPxH4MIshuzRdVdkCXuw4XOr9Clp+hOG2M5of6atinDvseo7fZa/UYvZ pzmBsZ2Fsm5HAAyboOpQ8Ho/sQeiASpeH1M2tWgK5BA4PRZVRnmPWY8A9mH5+OmU8YGI wZGxhHUxC4VXIUj+uXrnqYsq4AToJHaGXcMTKIUiWuJcP5Z2/isWM9ytMEkZh8pICOBB 5yfNWc6ZCsrssCghi2jR0PcamCh7tihNy2OhjRu142JMNskePTztg9jM3rmmFZ8T+CCg yrNam/KT7AVczVVYxrekapkPkpCJ1nd1tp0tukTCn+qgAyzID0qyZU+1ArO76l+8xKk9 +k4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=KBXfwM4T9Rp9h29Xxm0HwwLnhBuBHTwg/UkEmxOGyBA=; b=OdOOYc3x95HARdhikT9x3pKQIK9dLzMDq+/5egyh03wqgoGA8BYst/wCeScx/NrCwi lneOX4CS35q89D9Y7kI9df7Apd7CDbBLuoVN4hU34nSLbSwSlVKQ4G0SyKpTl8qYXuNf F0XjSKFwGFMUB4NWB5Aqg4TKILYoB953KQ1jFCcZRi0rhBRprcQTvV5A73rLnJiYOddH bzSKI09z+cT8AY2xk17343dYRN1DfeaKim3A0GwOXuQ4+GWzZuP4t20fbY8Y1xfVLCtt BapM/V0ewWw05ktMmsA+xX31XUMv1dNbzAzfdE1H+ZcTAyY9RMIpLiRqFUNijVxfOxyX VODw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HbQ+RJT+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t12si6303784ybq.423.2021.01.21.11.12.12 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jan 2021 11:12:13 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HbQ+RJT+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41238 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2fNM-0008D4-Dr for patch@linaro.org; Thu, 21 Jan 2021 14:12:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55774) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIL-0002MQ-4j for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:02 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:36225) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI1-0005rv-0t for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:06:58 -0500 Received: by mail-wm1-x334.google.com with SMTP id v184so2445513wma.1 for ; Thu, 21 Jan 2021 11:06:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KBXfwM4T9Rp9h29Xxm0HwwLnhBuBHTwg/UkEmxOGyBA=; b=HbQ+RJT+9V0Kaew+eV+iz8pVd8lP/UKHrSmfNy1iwMRa6CoHQdj4DXCeFfV25GpQ10 flNoPhrMhLBQeC/wIypvM22vfONFPftnK7jVduecv9WsEcpQ5nCNoqq4U8XeqWmwz45Q B5OdBtR8Du7sBUx0C7ZhgIIzbK/dkpFxzHAZWF1guIU6i18DdsS1FxPvB2Ed8raYLzry xywU7jVHAFFJz7otfgUQR3V2aUzzjXgw217H8uepnVWWJh1HRW7OEGOfEdDcHX90EeKj Kl06i3vv1bwHTt/RhFFNGrlHarW+uKVuUauKusOtbubpXuSp6Zj0xTIQwFc4uen2UC1L luvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KBXfwM4T9Rp9h29Xxm0HwwLnhBuBHTwg/UkEmxOGyBA=; b=jT3mdNt71rMtUjWhJklcFtsF1TbF9UPXK5Wh9+BzM4EWjBAkWWhOilXTYzwzem7ARX dgnRlsrrE/DXoD/81vuXV47l8qPMaIE2e5iMACDoEyStQJGYE8Q6PFGTm7b0bAzzHjFb vi2blKgFz51aemMMon6F3rj2iVDvR1CYHjVJtJnP/4YX3nqAEdRFLxjqk3HPTkT1IbLE 4f1OgAZIXBb8GxOdCYcAJUZpNOtg5N3cnOi/vX4K53uqijt7ipcquUmyiTFKgqS1Va2S JneNWde2rQkgnKwvcSbIvcUameNdIID+CMJ1cO+OA/c/SeP+Tk8u3m1Q4v2uKnYVeCXX JecA== X-Gm-Message-State: AOAM532paaLGng6XNsgRenorFsPMtGd09kq+bfvH/lGBPopZGs0JqglU nFv/hg2RoobJry/OwavVuB52nDz1CFrwTA== X-Received: by 2002:a05:600c:29cc:: with SMTP id s12mr736043wmd.180.1611255999681; Thu, 21 Jan 2021 11:06:39 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:39 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 15/25] hw/arm/musca: Create and connect ARMSSE Clocks Date: Thu, 21 Jan 2021 19:06:12 +0000 Message-Id: <20210121190622.22000-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create and connect the two clocks needed by the ARMSSE. Signed-off-by: Peter Maydell --- hw/arm/musca.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel diff --git a/hw/arm/musca.c b/hw/arm/musca.c index d82bef11cf2..a9292482a06 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -33,6 +33,7 @@ #include "hw/misc/tz-ppc.h" #include "hw/misc/unimp.h" #include "hw/rtc/pl031.h" +#include "hw/qdev-clock.h" #include "qom/object.h" #define MUSCA_NUMIRQ_MAX 96 @@ -82,6 +83,8 @@ struct MuscaMachineState { UnimplementedDeviceState sdio; UnimplementedDeviceState gpio; UnimplementedDeviceState cryptoisland; + Clock *sysclk; + Clock *s32kclk; }; #define TYPE_MUSCA_MACHINE "musca" @@ -96,6 +99,8 @@ OBJECT_DECLARE_TYPE(MuscaMachineState, MuscaMachineClass, MUSCA_MACHINE) * don't model that in our SSE-200 model yet. */ #define SYSCLK_FRQ 40000000 +/* Slow 32Khz S32KCLK frequency in Hz */ +#define S32KCLK_FRQ (32 * 1000) static qemu_irq get_sse_irq_in(MuscaMachineState *mms, int irqno) { @@ -367,6 +372,11 @@ static void musca_init(MachineState *machine) exit(1); } + mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); + clock_set_hz(mms->sysclk, SYSCLK_FRQ); + mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK"); + clock_set_hz(mms->s32kclk, S32KCLK_FRQ); + object_initialize_child(OBJECT(machine), "sse-200", &mms->sse, TYPE_SSE200); ssedev = DEVICE(&mms->sse); @@ -376,6 +386,8 @@ static void musca_init(MachineState *machine) qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor); qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); qdev_prop_set_uint32(ssedev, "MAINCLK_FRQ", SYSCLK_FRQ); + qdev_connect_clock_in(ssedev, "MAINCLK", mms->sysclk); + qdev_connect_clock_in(ssedev, "S32KCLK", mms->s32kclk); /* * Musca-A takes the default SSE-200 FPU/DSP settings (ie no for * CPU0 and yes for CPU1); Musca-B1 explicitly enables them for CPU0. From patchwork Thu Jan 21 19:06:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 367876 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp856784jam; Thu, 21 Jan 2021 11:35:41 -0800 (PST) X-Google-Smtp-Source: ABdhPJyGsLeL+sVCNJhDHlnRViHoyhU0gYi3CDWazXarM1huCvhQOXpXpvdNIWXKh38U0FI6tjx3 X-Received: by 2002:a25:b9c7:: with SMTP id y7mr1436852ybj.458.1611257740957; Thu, 21 Jan 2021 11:35:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611257740; cv=none; d=google.com; s=arc-20160816; b=i5BAZgb6f7dGvLlJyStr3n9k5CDxz+I4RxXYoZ4GGugKJTw8BXOpibJ82qhlcU4bpi 8rCgWsY8tZ5Q3OBH896ZcrxS6EQ/6yCb4h/q5aS55iRCYBDzW0ltCGNBa7LPOdxPeu76 wSMCuAeov8u/tUzxH7OfvGIjG0GdIQCAHulx87nc0+0/+1MphcVBj9Qd7Le6uOaaPmJH aE5TR49zAQM5i0BmM8zC2XXgd2Oa73FK+hTleXSMFunxeZe0DKCzb7l6kxqahqVnAXuO ZqHr9y4byKnRt0oce37ADgWppNZx02CXM56SPV3X0BSkG+AbpPAMwDHDIRKRLLzanlwj 6GCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MiFenp3CTLxpN6lolh3gSxciXNqVPXpodSUN7WzBpGQ=; b=Mtdq93clunez8HeA3RNs4KsLzN54uHVCNxkEKsUHtReu3yH9N6JUQinNq9c+qpWUPM f0qqCY9u3xCM+p8vWd0PimylXsgRgWGSwMmNpot2Ek1ljrDEmjEFW42q/AzjOy1Q9afy Sb01EgijMBnvCXkmK2FrVVRQZ1wWo25ASIpvFFFszjkyKeAp+SbvC9o/C5skgQxCk3hs k88FWGSJpZ9+4WdQPAOcUHBiDtcxn88fbxmJnDKHEACscdFEcSxRnxNtQnOKyul6pRZC x7OZF8pQqStgvFyQ3/B3GeV+YCWF818McVkFYbNaI36pC87DFbf/w0d8dpb6020D0Ijh 054Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=evqG7XgG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x15si3193720ybr.318.2021.01.21.11.35.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jan 2021 11:35:40 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=evqG7XgG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38914 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2fk4-0006Cz-Cn for patch@linaro.org; Thu, 21 Jan 2021 14:35:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55930) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIU-0002WA-7Y for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:10 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:35048) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI2-0005sQ-08 for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:09 -0500 Received: by mail-wr1-x431.google.com with SMTP id l12so2831431wry.2 for ; Thu, 21 Jan 2021 11:06:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MiFenp3CTLxpN6lolh3gSxciXNqVPXpodSUN7WzBpGQ=; b=evqG7XgGnF/4rZ1NIMbnAkakksPu8/fvQlfTIa4gl9JpkueLvfGkvgIOhmPQRUw08q KJWeDYF3uFJ1ftpLoWlBAmhtO+hdvo6BOLElmqNgetWROJ3rYIYV9YR8UGk8TLITEahD Y6dz/HXKH7GXn0p303pjGlQwhSht32yo4OWknsO1nopoSB1INCvT+Q4fvSLkjbGk/t79 ChMwrZZnHmUVZ9voDZTYx/wiPXM8bdtJkwl6ZWYgOlpe8nr90XIibOgrUWuLlnrp+wtT DmJMUpUX4dyu0Q1GqJrtBceIp3sPEuTnQ2ZCM5pgijcLYDNPh3cpx2YPlYcsICnZ6aaN qI2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MiFenp3CTLxpN6lolh3gSxciXNqVPXpodSUN7WzBpGQ=; b=IBN1lrS6EiCu8J+SXogJdB16R8UYyIF2kTFIwuliw/LgyR0+PRG2379TSWCu1qT/P+ or7jqjDPku1+TAY0ekrbcWTv4ez5YpFHJQjAEvItvjZPFPrqNPbHGraj3YuSm5SIm0zA bSDBwvjT1iME+yGa/N7lSrzmzJ/g2xE10utLczcynYcrI34ct7wIf8ZsrOYqSdR8jnUd 1UkWlWAP2HWr+PAoQYBaiDUntInI2KASN12n/f3Y1P7ib1pPXRI6Es6V19UyaD1+aG1S hhWolcqmsBzigezZ8ENrBkla/PBXjR1Qw+jGCW0a0RsaVnHGGtVQekYPwgJoaAKOyI/K kStw== X-Gm-Message-State: AOAM530wrYboAdTO2623IhwDfGmWMrdvLgL6paYymkWz38+SNZqXjn57 ZjtWqwtD3ffI00GYtf6mSj+HjQ== X-Received: by 2002:a5d:4987:: with SMTP id r7mr928148wrq.352.1611256000789; Thu, 21 Jan 2021 11:06:40 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:40 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 16/25] hw/arm/stellaris: Convert SSYS to QOM device Date: Thu, 21 Jan 2021 19:06:13 +0000 Message-Id: <20210121190622.22000-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the SSYS code in the Stellaris boards (which encapsulates the system registers) to a proper QOM device. This will provide us with somewhere to put the output Clock whose frequency depends on the setting of the PLL configuration registers. This is a migration compatibility break for lm3s811evb, lm3s6965evb. We use 3-phase reset here because the Clock will need to propagate its value in the hold phase. For the moment we reset the device during the board creation so that the system_clock_scale global gets set; this will be removed in a subsequent commit. Signed-off-by: Peter Maydell --- hw/arm/stellaris.c | 132 ++++++++++++++++++++++++++++++++++++--------- 1 file changed, 107 insertions(+), 25 deletions(-) -- 2.20.1 Reviewed-by: Luc Michel Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 652823195b1..0194ede2fe0 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -357,7 +357,12 @@ static void stellaris_gptm_realize(DeviceState *dev, Error **errp) /* System controller. */ -typedef struct { +#define TYPE_STELLARIS_SYS "stellaris-sys" +OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS) + +struct ssys_state { + SysBusDevice parent_obj; + MemoryRegion iomem; uint32_t pborctl; uint32_t ldopctl; @@ -371,11 +376,18 @@ typedef struct { uint32_t dcgc[3]; uint32_t clkvclr; uint32_t ldoarst; + qemu_irq irq; + /* Properties (all read-only registers) */ uint32_t user0; uint32_t user1; - qemu_irq irq; - stellaris_board_info *board; -} ssys_state; + uint32_t did0; + uint32_t did1; + uint32_t dc0; + uint32_t dc1; + uint32_t dc2; + uint32_t dc3; + uint32_t dc4; +}; static void ssys_update(ssys_state *s) { @@ -430,7 +442,7 @@ static uint32_t pllcfg_fury[16] = { static int ssys_board_class(const ssys_state *s) { - uint32_t did0 = s->board->did0; + uint32_t did0 = s->did0; switch (did0 & DID0_VER_MASK) { case DID0_VER_0: return DID0_CLASS_SANDSTORM; @@ -456,19 +468,19 @@ static uint64_t ssys_read(void *opaque, hwaddr offset, switch (offset) { case 0x000: /* DID0 */ - return s->board->did0; + return s->did0; case 0x004: /* DID1 */ - return s->board->did1; + return s->did1; case 0x008: /* DC0 */ - return s->board->dc0; + return s->dc0; case 0x010: /* DC1 */ - return s->board->dc1; + return s->dc1; case 0x014: /* DC2 */ - return s->board->dc2; + return s->dc2; case 0x018: /* DC3 */ - return s->board->dc3; + return s->dc3; case 0x01c: /* DC4 */ - return s->board->dc4; + return s->dc4; case 0x030: /* PBORCTL */ return s->pborctl; case 0x034: /* LDOPCTL */ @@ -646,9 +658,9 @@ static const MemoryRegionOps ssys_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static void ssys_reset(void *opaque) +static void stellaris_sys_reset_enter(Object *obj, ResetType type) { - ssys_state *s = (ssys_state *)opaque; + ssys_state *s = STELLARIS_SYS(obj); s->pborctl = 0x7ffd; s->rcc = 0x078e3ac0; @@ -661,9 +673,19 @@ static void ssys_reset(void *opaque) s->rcgc[0] = 1; s->scgc[0] = 1; s->dcgc[0] = 1; +} + +static void stellaris_sys_reset_hold(Object *obj) +{ + ssys_state *s = STELLARIS_SYS(obj); + ssys_calculate_system_clock(s); } +static void stellaris_sys_reset_exit(Object *obj) +{ +} + static int stellaris_sys_post_load(void *opaque, int version_id) { ssys_state *s = opaque; @@ -695,27 +717,66 @@ static const VMStateDescription vmstate_stellaris_sys = { } }; +static Property stellaris_sys_properties[] = { + DEFINE_PROP_UINT32("user0", ssys_state, user0, 0), + DEFINE_PROP_UINT32("user1", ssys_state, user1, 0), + DEFINE_PROP_UINT32("did0", ssys_state, did0, 0), + DEFINE_PROP_UINT32("did1", ssys_state, did1, 0), + DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0), + DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0), + DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0), + DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0), + DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0), + DEFINE_PROP_END_OF_LIST() +}; + +static void stellaris_sys_instance_init(Object *obj) +{ + ssys_state *s = STELLARIS_SYS(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(s); + + memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq); +} + static int stellaris_sys_init(uint32_t base, qemu_irq irq, stellaris_board_info * board, uint8_t *macaddr) { - ssys_state *s; + DeviceState *dev = qdev_new(TYPE_STELLARIS_SYS); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); - s = g_new0(ssys_state, 1); - s->irq = irq; - s->board = board; /* Most devices come preprogrammed with a MAC address in the user data. */ - s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16); - s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16); + qdev_prop_set_uint32(dev, "user0", + macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16)); + qdev_prop_set_uint32(dev, "user1", + macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16)); + qdev_prop_set_uint32(dev, "did0", board->did0); + qdev_prop_set_uint32(dev, "did1", board->did1); + qdev_prop_set_uint32(dev, "dc0", board->dc0); + qdev_prop_set_uint32(dev, "dc1", board->dc1); + qdev_prop_set_uint32(dev, "dc2", board->dc2); + qdev_prop_set_uint32(dev, "dc3", board->dc3); + qdev_prop_set_uint32(dev, "dc4", board->dc4); + + sysbus_realize_and_unref(sbd, &error_fatal); + sysbus_mmio_map(sbd, 0, base); + sysbus_connect_irq(sbd, 0, irq); + + /* + * Normally we should not be resetting devices like this during + * board creation. For the moment we need to do so, because + * system_clock_scale will only get set when the STELLARIS_SYS + * device is reset, and we need its initial value to pass to + * the watchdog device. This hack can be removed once the + * watchdog has been converted to use a Clock input instead. + */ + device_cold_reset(dev); - memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000); - memory_region_add_subregion(get_system_memory(), base, &s->iomem); - ssys_reset(s); - vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_stellaris_sys, s); return 0; } - /* I2C controller. */ #define TYPE_STELLARIS_I2C "stellaris-i2c" @@ -1553,11 +1614,32 @@ static const TypeInfo stellaris_adc_info = { .class_init = stellaris_adc_class_init, }; +static void stellaris_sys_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); + + dc->vmsd = &vmstate_stellaris_sys; + rc->phases.enter = stellaris_sys_reset_enter; + rc->phases.hold = stellaris_sys_reset_hold; + rc->phases.exit = stellaris_sys_reset_exit; + device_class_set_props(dc, stellaris_sys_properties); +} + +static const TypeInfo stellaris_sys_info = { + .name = TYPE_STELLARIS_SYS, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(ssys_state), + .instance_init = stellaris_sys_instance_init, + .class_init = stellaris_sys_class_init, +}; + static void stellaris_register_types(void) { type_register_static(&stellaris_i2c_info); type_register_static(&stellaris_gptm_info); type_register_static(&stellaris_adc_info); + type_register_static(&stellaris_sys_info); } type_init(stellaris_register_types) From patchwork Thu Jan 21 19:06:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 367868 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp850567jam; Thu, 21 Jan 2021 11:26:43 -0800 (PST) X-Google-Smtp-Source: ABdhPJy2SiX4tvZnziKA5HUxToLo1A5oRlelo5qF/2p7/jDtMyN3xq1+Vs22p1uJZSANvjpoSfZy X-Received: by 2002:a25:3d84:: with SMTP id k126mr1170181yba.162.1611257203719; Thu, 21 Jan 2021 11:26:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611257203; cv=none; d=google.com; s=arc-20160816; b=SF8qKKQ/QYT7NZ5ei7PKqoUXTfKxqchnIbYFEcSmptDr5GdO3dfd99yfXyrXiaYz/4 0QKp6a9+4Em3oMhKNxiaokUhcReKqNaHPCG7jIYLnxBtbCXaAB/wBCynT3HL4CwZGdgN wpT/6cafp7gn7Np9kimuVyK3PUcNFTSPb9ShVvEaFQGQhazhJzzrV6Wg34F44yEgYbYs S8xdg55wh+POic4eQIha8dospVkXgSLpDxViGp7jASB1a7lRVZ8jBS3g/fH5gSiPVOHO 8IR+RbeJ2aAj7aoP7EMozCRtooPRSLuiuyHV9IW/WgMHy9RKbHcqhoBu6Tifel2BvRSV 9WIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MnpjFP3ps33JvLWa6qS6ae0tBST2dCJ7w+wCFqGW/AY=; b=UewxWflRTOXgG94O4da4CxUQrlUnNSWwPrKDmM7goamLGCqdXJRVJP8hT+hSLghj7p tBIbS0I9NVd+kL0zSHUkYGL9v+qaS7D9+dOWRmbQV1PoBHPAC8NWYq2ylaqFyjsdmcE3 A8fzIHBkqggvPKhnVY3RYVeIZpIoBYJDBns7lDHOaWFBGKyFHvoTeHUM2KoVdi/snCz9 Vk0NFQpIzUuvUEMhVaHBGJo2OW+8w1efrSrpPOp5oehW1g/5hhdTwC/5joJbRQiz3ohS +PxG3SuUGAZaUeo7Y0ye1ZxW1ZRZmurGTw1MiaZPmwVz0NFxbTacilk2JyHnFuz+DXWZ WC8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Wag0SSdr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p197si6149613ybc.155.2021.01.21.11.26.43 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jan 2021 11:26:43 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Wag0SSdr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43832 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2fbP-0004ei-4q for patch@linaro.org; Thu, 21 Jan 2021 14:26:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55882) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIQ-0002TB-WB for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:07 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:52022) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI3-0005t3-EL for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:06 -0500 Received: by mail-wm1-x335.google.com with SMTP id m2so2405029wmm.1 for ; Thu, 21 Jan 2021 11:06:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MnpjFP3ps33JvLWa6qS6ae0tBST2dCJ7w+wCFqGW/AY=; b=Wag0SSdrcMiEPLYPyl0mMDvSadxhITLWfdxIl9cR+2zvXqIpILOD8BOY98hXMZ1Dw3 uUb94vRzzld8HaF+DlY/PmHlLlKaP0Mem7gL+uqYDQqK3U+Qdux8c5ik3LGuFoMTpNgQ We+UGJz+57cvimuqwrZ7jG6zTokQpD/LgQya6c4F/VoaQSqrDvS5FQaJgnFjXGXwz/rz 0ch4G6dMERxGVy/27PsCfiPQoyQVCGDzsjp36O4Xz+OI8Qsc2K9iAhSkm0sf+xcHu2iq TctxS2tTssFoIDubJT/C6MG3ZiuBwJ020AgRoBjiqQi9vdmM/kpyPtumiqVLr7AVYtn3 9ZAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MnpjFP3ps33JvLWa6qS6ae0tBST2dCJ7w+wCFqGW/AY=; b=iAmJJGlq0PUor6zRYiQlElRFgmIOUWQa064FBgtlFAqSL7Z+2TjwoBnp35yP7FbFlv 31uuphzitUh/ON/ygP4eTohb/wc8nozVCI1g3Rtj6D2x1XTVPPWrk2imm0eM89IPXl6l er5a8664trWirPJJDnm1M3SxAFOwputdbDyA6j0ijuSfVF32g+XKxO6fraqnj6ndN2pG sJd+cYBn+g5LymiJhcZI5QykhIC+RjzH7LviSjWoQRZmhPsCN2LiTvOzisFnlwkryaOg PyshJmim9bJTF2wstUcaNYk8PbXwrL7GMDjUckap1vvSkUlhCqIRh3RmjMg5xG/A+t9M 0CFQ== X-Gm-Message-State: AOAM532n7S4CHuPbtHv0dv0wG/5WpfcP1ZooFuq5SaBrNdb16rgp7HW8 zPejy5owmQS1AJMqFXwMGEInuw== X-Received: by 2002:a1c:cb:: with SMTP id 194mr779126wma.30.1611256001728; Thu, 21 Jan 2021 11:06:41 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:41 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 17/25] hw/arm/stellaris: Create Clock input for watchdog Date: Thu, 21 Jan 2021 19:06:14 +0000 Message-Id: <20210121190622.22000-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create and connect the Clock input for the watchdog device on the Stellaris boards. Because the Stellaris boards model the ability to change the clock rate by programming PLL registers, we have to create an output Clock on the ssys_state device and wire it up to the watchdog. Note that the old comment on ssys_calculate_system_clock() got the units wrong -- system_clock_scale is in nanoseconds, not milliseconds. Improve the commentary to clarify how we are calculating the period. Signed-off-by: Peter Maydell --- hw/arm/stellaris.c | 43 +++++++++++++++++++++++++++++++------------ 1 file changed, 31 insertions(+), 12 deletions(-) -- 2.20.1 Reviewed-by: Luc Michel Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 0194ede2fe0..9b67c739ef2 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -26,6 +26,7 @@ #include "hw/watchdog/cmsdk-apb-watchdog.h" #include "migration/vmstate.h" #include "hw/misc/unimp.h" +#include "hw/qdev-clock.h" #include "cpu.h" #include "qom/object.h" @@ -377,6 +378,7 @@ struct ssys_state { uint32_t clkvclr; uint32_t ldoarst; qemu_irq irq; + Clock *sysclk; /* Properties (all read-only registers) */ uint32_t user0; uint32_t user1; @@ -555,15 +557,26 @@ static bool ssys_use_rcc2(ssys_state *s) } /* - * Caculate the sys. clock period in ms. + * Calculate the system clock period. We only want to propagate + * this change to the rest of the system if we're not being called + * from migration post-load. */ -static void ssys_calculate_system_clock(ssys_state *s) +static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock) { + /* + * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input + * clock is 200MHz, which is a period of 5 ns. Dividing the clock + * frequency by X is the same as multiplying the period by X. + */ if (ssys_use_rcc2(s)) { system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); } else { system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); } + clock_set_ns(s->sysclk, system_clock_scale); + if (propagate_clock) { + clock_propagate(s->sysclk); + } } static void ssys_write(void *opaque, hwaddr offset, @@ -598,7 +611,7 @@ static void ssys_write(void *opaque, hwaddr offset, s->int_status |= (1 << 6); } s->rcc = value; - ssys_calculate_system_clock(s); + ssys_calculate_system_clock(s, true); break; case 0x070: /* RCC2 */ if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { @@ -610,7 +623,7 @@ static void ssys_write(void *opaque, hwaddr offset, s->int_status |= (1 << 6); } s->rcc2 = value; - ssys_calculate_system_clock(s); + ssys_calculate_system_clock(s, true); break; case 0x100: /* RCGC0 */ s->rcgc[0] = value; @@ -679,7 +692,8 @@ static void stellaris_sys_reset_hold(Object *obj) { ssys_state *s = STELLARIS_SYS(obj); - ssys_calculate_system_clock(s); + /* OK to propagate clocks from the hold phase */ + ssys_calculate_system_clock(s, true); } static void stellaris_sys_reset_exit(Object *obj) @@ -690,7 +704,7 @@ static int stellaris_sys_post_load(void *opaque, int version_id) { ssys_state *s = opaque; - ssys_calculate_system_clock(s); + ssys_calculate_system_clock(s, false); return 0; } @@ -713,6 +727,7 @@ static const VMStateDescription vmstate_stellaris_sys = { VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), VMSTATE_UINT32(clkvclr, ssys_state), VMSTATE_UINT32(ldoarst, ssys_state), + /* No field for sysclk -- handled in post-load instead */ VMSTATE_END_OF_LIST() } }; @@ -738,11 +753,12 @@ static void stellaris_sys_instance_init(Object *obj) memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000); sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->irq); + s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK"); } -static int stellaris_sys_init(uint32_t base, qemu_irq irq, - stellaris_board_info * board, - uint8_t *macaddr) +static DeviceState *stellaris_sys_init(uint32_t base, qemu_irq irq, + stellaris_board_info *board, + uint8_t *macaddr) { DeviceState *dev = qdev_new(TYPE_STELLARIS_SYS); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); @@ -774,7 +790,7 @@ static int stellaris_sys_init(uint32_t base, qemu_irq irq, */ device_cold_reset(dev); - return 0; + return dev; } /* I2C controller. */ @@ -1341,6 +1357,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) int flash_size; I2CBus *i2c; DeviceState *dev; + DeviceState *ssys_dev; int i; int j; @@ -1391,8 +1408,8 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) } } - stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28), - board, nd_table[0].macaddr.a); + ssys_dev = stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28), + board, nd_table[0].macaddr.a); if (board->dc1 & (1 << 3)) { /* watchdog present */ @@ -1401,6 +1418,8 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) /* system_clock_scale is valid now */ uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale; qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk); + qdev_connect_clock_in(dev, "WDOGCLK", + qdev_get_clock_out(ssys_dev, "SYSCLK")); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), From patchwork Thu Jan 21 19:06:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 367869 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp850782jam; Thu, 21 Jan 2021 11:27:08 -0800 (PST) X-Google-Smtp-Source: ABdhPJwVoM34MogBXk0MRr966sS3Yvp0TTsSoZjJef4nf1HQAyErCMTRSrp2tLf35s8kUmsD7ipI X-Received: by 2002:a25:9b45:: with SMTP id u5mr1180841ybo.331.1611257228023; Thu, 21 Jan 2021 11:27:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611257228; cv=none; d=google.com; s=arc-20160816; b=nD/2zZkpRM4KUzBo74YTKcSuX3NZJT6Cc0nXMc2lc1FZv3yTHG/jejdlWtoemnskRT zDas/CNHK77iUryAehtQMI/c2sfg4LAArnYgfqVPxI46mVYBxFeLtoc/c50SgLeKozej rRv8n8mgfp0qDDznwxnSMi2YOGkIvfnxeog3Y0400wWQZwgmdkeMw9yhhkAEtF+j7XMD lQkRvSgdWEeV+6TdBj3bld2mjTNwX7AzMbMf56EjmnOYGdkTjE3RdP9U+YKtBqgJbeQY KVatxvojUHSO5ZvUaXH3cZ3lpCVNz/rtEynOMMYzvEwGuCRH3GIe2qwItwrGm2gUz3/4 4d7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rsYESJD/HWuRtywCiQ4FwoIx9DBv3ZNqK0aUaHfGa/I=; b=uPxt/I73f76QufoK0BNZLMwQ4UoTnG7eUFdfbIB4EihhuPVkCCjWQQrqd5AeO+KwMa OuSUCwsFw/lwnTLDLeFQZNDNpSGSfM/cx+3Nltodwo1Z7yo5iB7BsYXregb8Sf0DDnLG if4NsVXkwKw34fRJ14G3IzCs5aHS6A+6JL+3CUpzywaWwOxLvMKfL0ZCQ8qdf6pyXGH5 IYZlpISc1VYNpprzZ2QyVYLmsUHEnPOYUG9X8tG/9Lx3uf9iF/OQTxkEwOG3U0JcQzq8 M8+bKmf+sEQix+h0QIoSJx2zlqJXGFKV8dE05b/oKdq8kk8eLid7bhtdzmvm+MyxT3+g sDiw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ffRZg1u6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k36si6351766ybj.315.2021.01.21.11.27.07 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jan 2021 11:27:08 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ffRZg1u6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44398 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2fbn-0004sb-F9 for patch@linaro.org; Thu, 21 Jan 2021 14:27:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55906) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIS-0002VC-O2 for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:09 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:55686) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI3-0005uV-Se for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:08 -0500 Received: by mail-wm1-x32c.google.com with SMTP id c124so2397279wma.5 for ; Thu, 21 Jan 2021 11:06:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rsYESJD/HWuRtywCiQ4FwoIx9DBv3ZNqK0aUaHfGa/I=; b=ffRZg1u6TLr3hUxuwv9QXO7tKTN9RmBUpy2Zsu+fbrbXUD5RZQ0ITOn9wEM1HhbPOn TEzIwrdVtsnAFnxDR3cJabvYoY+88bUNst306fglgNxT9E1pDycU1TCcE8MXaXNRex2C UAlMN6iNdi/nrAsoAEvRO8zsrlfNHvhKt7WF1p+zzG79tA2aGTFnaxFcTQhCmhSKw0Rd 4UiEFXhlgcIQJJIkNseCLZlRa6qICIPVwDLl0BEzcqpqA0GkRE/oZO4BLTUDfGIW5Yvg c8eQQuLBZq5Z10S6BZdMzOeh4gE7HlncCRur1bBJCp3Cxcsxn3G8GopTMM4uSXxt3Nym pJiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rsYESJD/HWuRtywCiQ4FwoIx9DBv3ZNqK0aUaHfGa/I=; b=Cmte8y4596tZwLS1Y4g0VFTyOxsZFEwbr3IiiOOg8UPfyfOkc6CpqEJ+AF77EdE2cm Nj2WzNoZzJsD4OPcXi20GTJwJxDJ1oueNsQzvhmkWCnBNxt6B6gDoK0IddhbvRCv3HOS TwP5YyAmvcnNjogvHK94X+/WQqvdCxGSAXCK8YtHIH1cx905P/L2LvU3PNxDBomYbG/N 7ns5/OBsyddWUetOIGaRWkd+nxDTc3o9Gd5qqmN8dS05EI6p/br1an1sXYWYRUT1VlU3 3InyD06YaIWbQcLfF6ruKD9P0J3I4voTki9GNvFh9HCe/F+Up97eBUoGVJA8M9IFIxQ3 zBIA== X-Gm-Message-State: AOAM531ucawAQwVSVDKTaULpI8aMAM37+jcsG7Tj5AyvpvM1//TQAPKX KSxilAx7HG0TXWYLrpWhhk0YWw== X-Received: by 2002:a7b:ca4c:: with SMTP id m12mr713127wml.115.1611256002611; Thu, 21 Jan 2021 11:06:42 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:42 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 18/25] hw/timer/cmsdk-apb-timer: Convert to use Clock input Date: Thu, 21 Jan 2021 19:06:15 +0000 Message-Id: <20210121190622.22000-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Switch the CMSDK APB timer device over to using its Clock input; the pclk-frq property is now ignored. Signed-off-by: Peter Maydell --- hw/timer/cmsdk-apb-timer.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c index c63145ff553..f053146d88f 100644 --- a/hw/timer/cmsdk-apb-timer.c +++ b/hw/timer/cmsdk-apb-timer.c @@ -204,6 +204,15 @@ static void cmsdk_apb_timer_reset(DeviceState *dev) ptimer_transaction_commit(s->timer); } +static void cmsdk_apb_timer_clk_update(void *opaque) +{ + CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque); + + ptimer_transaction_begin(s->timer); + ptimer_set_period_from_clock(s->timer, s->pclk, 1); + ptimer_transaction_commit(s->timer); +} + static void cmsdk_apb_timer_init(Object *obj) { SysBusDevice *sbd = SYS_BUS_DEVICE(obj); @@ -213,15 +222,16 @@ static void cmsdk_apb_timer_init(Object *obj) s, "cmsdk-apb-timer", 0x1000); sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->timerint); - s->pclk = qdev_init_clock_in(DEVICE(s), "pclk", NULL, NULL); + s->pclk = qdev_init_clock_in(DEVICE(s), "pclk", + cmsdk_apb_timer_clk_update, s); } static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) { CMSDKAPBTimer *s = CMSDK_APB_TIMER(dev); - if (s->pclk_frq == 0) { - error_setg(errp, "CMSDK APB timer: pclk-frq property must be set"); + if (!clock_has_source(s->pclk)) { + error_setg(errp, "CMSDK APB timer: pclk clock must be connected"); return; } @@ -232,7 +242,7 @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp) PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); ptimer_transaction_begin(s->timer); - ptimer_set_freq(s->timer, s->pclk_frq); + ptimer_set_period_from_clock(s->timer, s->pclk, 1); ptimer_transaction_commit(s->timer); } From patchwork Thu Jan 21 19:06:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 367861 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp847565jam; Thu, 21 Jan 2021 11:21:25 -0800 (PST) X-Google-Smtp-Source: ABdhPJxt9jpTjlPoB9BbIEaXnAI12xJRKl9fgEB09BNlHVEMjCortemmEKFKMR9bKLSmr3v7FdIm X-Received: by 2002:a25:76d2:: with SMTP id r201mr1209230ybc.107.1611256885161; Thu, 21 Jan 2021 11:21:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611256885; cv=none; d=google.com; s=arc-20160816; b=zTu2KpOBHDrbVetc2njWpSvwK0cKhiPIawdw5IoRVmKfK5RAzDx0CQnDiK9ldFcfE3 SXtK8IdMI9yj+JulYdvCE+Os3NDKRbMHzeswASEepJ6p44c8EyUMrsouPPZ1G+XnlxnH 6oeu+XvbjqQmxgAFzmBqkhvm6IHzjQShC4rCufcLEEaN8wQVPzfQzdt9eB674J4nAMnN JH2FAfIapzwGtXjLcYHtllr1+fIJQfx/cwE8j0/YYIMHCFwOiwspFR4aiHi02LeXAyYL 2FuRz8SDPSO3r45NwFGdTdCmUr48i0HM4ct/izcwcqW+I3UkROYG/gQYp2w6gLElEOCp ixcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=l+C2gTVos115dMvtdyIN+AXfuTec5f/EcGemGRxkJo4=; b=IVwPNKIT6z9NKrzj6v3lAGEhP93FKOIoeZNYiAsXlQGThP+FpYrrrUbqQVortkr0eU 1Yj/u2o8on+mQAqJUZS73TmPEcUmhTgYoZX7vXMk/13m8eEgcie3RpvDCUcwGaksePDU VH9dCjfQTl2YN9LDkOdWeQQP41ByPdJusFDa1FtsNA6e48RGTF8ouBT0xzQMbiy1oEwG 25pvLfY2rP4YX8LB1dOfDaUp2F//1Uua/xY8Qrbp+/R0QdleGIDqcml2M/JhReC8rluQ TuknXieT2Tg8ypKn0/6PCc1bPGd2j8Rm7HqqfoT7OxdRFXPyqXVexF2dj28iIWEkIyS+ Q7tw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vadlG+WX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 23si6649201ybc.452.2021.01.21.11.21.25 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jan 2021 11:21:25 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vadlG+WX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:58638 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2fWG-0007S4-Id for patch@linaro.org; Thu, 21 Jan 2021 14:21:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55926) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIU-0002W7-3X for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:10 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:52014) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI5-0005un-1C for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:09 -0500 Received: by mail-wm1-x32c.google.com with SMTP id m2so2405099wmm.1 for ; Thu, 21 Jan 2021 11:06:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=l+C2gTVos115dMvtdyIN+AXfuTec5f/EcGemGRxkJo4=; b=vadlG+WXak4otfF4yCJv1/Wzh3To5b4qBkBVhGiDSjUUjQPxo26gOMK5vZlnQx1+Lt ygQahyaanc9Lpp9w0bzOZlY72EhPksbX0QihXx56BkbSIr69F4lcu4spWMqzuvz56DT9 dOEK44cS008YLgKf/yyToiZNtUw94biV3bhXiLmXjPrwKclFrWD1t2KDG5zuRVcEUzdP /w+J54TtldYuFV+eC0px/EzWGKLxAka/iSLL3uvbO0Dw7vozAxbc9SZoeaQXZkfTZxp0 KCfzfd4fL9ZKo4r9SCl8w72KpDVqexQTLej5NbLlVzrm0miJ2eUpqmEb7xXSk83hsGI0 jdVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=l+C2gTVos115dMvtdyIN+AXfuTec5f/EcGemGRxkJo4=; b=Iq8JQFOc6Z6k8OthwZ30x3RZ/sR0YI6bJ7VG8AmKTSDRpRDvCfPkFrukl6rFlr7HBq h/UksGj5Dniadks+jAS0Rds6CW/u8Y9LmOTTzf+hKBHCdvGVy3FYYlA5ZEb7ObnhSgPD saCjbYFz19FQ4btWnlvSa1VCU+GTirmYfJqW0PNy7YrvMzTDPD4KrUQNMH663lO4zId5 sXACerijp+dElyleF7EzXeAgEfphBrwDXUxDk0N7iEQz0HZMDCU51AjfY775DNO05SlJ cNH9MW1CDoDVg86lY0RdYGgqL+w9LAkbBhTrcE+FRygH/rwmafj69swrETbaqzNPmpPg DBGQ== X-Gm-Message-State: AOAM5324FZWYL82/hw24FdpjL9Vc2lr5TTMgL/BaxaPx1O7znYHkMTgZ mlXVWQkWYRn4v+oDCNyTUL81Yg== X-Received: by 2002:a1c:9609:: with SMTP id y9mr703365wmd.75.1611256003595; Thu, 21 Jan 2021 11:06:43 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:43 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 19/25] hw/timer/cmsdk-apb-dualtimer: Convert to use Clock input Date: Thu, 21 Jan 2021 19:06:16 +0000 Message-Id: <20210121190622.22000-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Switch the CMSDK APB dualtimer device over to using its Clock input; the pclk-frq property is now ignored. Signed-off-by: Peter Maydell --- hw/timer/cmsdk-apb-dualtimer.c | 42 ++++++++++++++++++++++++++++++---- 1 file changed, 37 insertions(+), 5 deletions(-) -- 2.20.1 Reviewed-by: Luc Michel Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c index 781b496037b..828127b366f 100644 --- a/hw/timer/cmsdk-apb-dualtimer.c +++ b/hw/timer/cmsdk-apb-dualtimer.c @@ -106,6 +106,22 @@ static void cmsdk_apb_dualtimer_update(CMSDKAPBDualTimer *s) qemu_set_irq(s->timerintc, timintc); } +static int cmsdk_dualtimermod_divisor(CMSDKAPBDualTimerModule *m) +{ + /* Return the divisor set by the current CONTROL.PRESCALE value */ + switch (FIELD_EX32(m->control, CONTROL, PRESCALE)) { + case 0: + return 1; + case 1: + return 16; + case 2: + case 3: /* UNDEFINED, we treat like 2 (and complained when it was set) */ + return 256; + default: + g_assert_not_reached(); + } +} + static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m, uint32_t newctrl) { @@ -146,7 +162,7 @@ static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m, default: g_assert_not_reached(); } - ptimer_set_freq(m->timer, m->parent->pclk_frq / divisor); + ptimer_set_period_from_clock(m->timer, m->parent->timclk, divisor); } if (changed & R_CONTROL_MODE_MASK) { @@ -414,7 +430,8 @@ static void cmsdk_dualtimermod_reset(CMSDKAPBDualTimerModule *m) * limit must both be set to 0xffff, so we wrap at 16 bits. */ ptimer_set_limit(m->timer, 0xffff, 1); - ptimer_set_freq(m->timer, m->parent->pclk_frq); + ptimer_set_period_from_clock(m->timer, m->parent->timclk, + cmsdk_dualtimermod_divisor(m)); ptimer_transaction_commit(m->timer); } @@ -432,6 +449,20 @@ static void cmsdk_apb_dualtimer_reset(DeviceState *dev) s->timeritop = 0; } +static void cmsdk_apb_dualtimer_clk_update(void *opaque) +{ + CMSDKAPBDualTimer *s = CMSDK_APB_DUALTIMER(opaque); + int i; + + for (i = 0; i < ARRAY_SIZE(s->timermod); i++) { + CMSDKAPBDualTimerModule *m = &s->timermod[i]; + ptimer_transaction_begin(m->timer); + ptimer_set_period_from_clock(m->timer, m->parent->timclk, + cmsdk_dualtimermod_divisor(m)); + ptimer_transaction_commit(m->timer); + } +} + static void cmsdk_apb_dualtimer_init(Object *obj) { SysBusDevice *sbd = SYS_BUS_DEVICE(obj); @@ -446,7 +477,8 @@ static void cmsdk_apb_dualtimer_init(Object *obj) for (i = 0; i < ARRAY_SIZE(s->timermod); i++) { sysbus_init_irq(sbd, &s->timermod[i].timerint); } - s->timclk = qdev_init_clock_in(DEVICE(s), "TIMCLK", NULL, NULL); + s->timclk = qdev_init_clock_in(DEVICE(s), "TIMCLK", + cmsdk_apb_dualtimer_clk_update, s); } static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp) @@ -454,8 +486,8 @@ static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp) CMSDKAPBDualTimer *s = CMSDK_APB_DUALTIMER(dev); int i; - if (s->pclk_frq == 0) { - error_setg(errp, "CMSDK APB timer: pclk-frq property must be set"); + if (!clock_has_source(s->timclk)) { + error_setg(errp, "CMSDK APB dualtimer: TIMCLK clock must be connected"); return; } From patchwork Thu Jan 21 19:06:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 367875 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp856176jam; Thu, 21 Jan 2021 11:34:46 -0800 (PST) X-Google-Smtp-Source: ABdhPJzkozbbq+9CAzLMjWKvARTkeT2LtR6S96xydApMCP6QXi9AJ0aXvioe4/ok1Cwn4fOiYu/j X-Received: by 2002:a25:b320:: with SMTP id l32mr1383086ybj.104.1611257685938; Thu, 21 Jan 2021 11:34:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611257685; cv=none; d=google.com; s=arc-20160816; b=WkvaPhgLmYceVsEbqu2ynqyWaP+tr+F5qCVG3uUMymMriSgxnbeBSlWmtaEexvx2Pa 3NBsFkisFP3KPJxSRMXxPDi5Te5fKXTp2+Szkq5wkVzl+4EFSTbnxuGc0MqK/rl+jyZ0 wMjfj1FqTABdxZELOb0X2D7DNGFb3PnbGoFL06L2jkORd6SMcVm+vaPs8a45VxQoXPNb m26EoFjgA7qB12+H8eI4UmKMd8B4fH6Rrw1UvUciIDq3+53ASWpu0F4L8nAY+lZaDYPO jDek2MocPyWqJ3TbMXAvhdhLg2YaGBLhlrJM/3xFzk3clt6N+xOpkhxP2JfoClTt72kP 2t1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=uDxVLnL9xv9QeWzNKaXg1U1KaegZzyNUwA1UoAWaXas=; b=TCygOZzGaXU+Erg1tcRLv3eg4XMkNCLOR+K2xHg9I02NGMA2ccWMje7qqbujkgOi3a 3S89gsW4LiCXxDeqgRsT8c2dbWSz10RfrA2qgl5hmgEs+5G5y2Hv4RNuL1WW+9EB6sEX JjhcMSFUaevXQ0MN5xw9sKmBGKuZfZO5Fl6rzblaf3VKoBxoxwYytoUTG1r2/1QCqMnH Xvi1uD5uN3Ny8kBCGmjhi32xqwDU6BM0F8G1JCqpOgHbzbrR6W/z9fV9lKtBFawqCEXU KkROLjVNA6BMbnRmvNDbRmEJW7llWxEkyXOd36kuuwP5PEtOMseO098/+s8Xa1UVS/tX XWlg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XZhC+Xrx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a3si4078480ybp.221.2021.01.21.11.34.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jan 2021 11:34:45 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XZhC+Xrx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34742 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2fj9-0004Tq-Mw for patch@linaro.org; Thu, 21 Jan 2021 14:34:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55958) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIV-0002Yf-2n for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:11 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:38002) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI7-0005v6-2E for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:10 -0500 Received: by mail-wm1-x32b.google.com with SMTP id y187so2436665wmd.3 for ; Thu, 21 Jan 2021 11:06:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uDxVLnL9xv9QeWzNKaXg1U1KaegZzyNUwA1UoAWaXas=; b=XZhC+Xrx9Ww1AlqhNOlETwxevwiCnjLdAIp1pjcgbcGVsD92fuKCGyiUz3TBe92YZn sTog1D1Fay1tTvbP2YBT31aqr/rnKy+OjqLty4wKss8KagBRAvNarGbCpBCC3CwFz6sL 26pWQBVzXQcWXn9wwDDuMQctqKac76px5OglnGulWMUSej2YwQrr4p/dumOgY+8zSmVy Bq2uNk1pyzuT81BHRHC9H2DoWlMk/8irKrT+i8i4GwP0amtV0/UdN7qyFEAw30Y9ZhRt +rYPAXvW6gXz/PWLFnCHnfVLuvv4rfWkutr1sIJ+lH9nooNEJo6+vtjeVRJDK+GrY0pE sSUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uDxVLnL9xv9QeWzNKaXg1U1KaegZzyNUwA1UoAWaXas=; b=nVic41AOzdq7mbs90D04I9qRXctOIT1IA0QG3bvYHJ/A5fQEwctSvlRt4dZmGM8zi+ z+I5+RgILO6KXGiPwhNr/19lNKWsRAVZny7pOrxKOkZ7drCsMafn8FHGFwj7Re6qKLgM jIshu5Gtva8YGA7Q1703SqSNUmWn3HTBdklbjr9uTqyEYorfpwGQklJUnE6J2G+NOVXb kePs/f2ZeA0Aq/fYYf+5rQJiNiYGvosI6phv+3bT21sVtZICp/5OrJ3ZYUQJSBywyu86 /fhEWav4rZIWkK4DdqlbAr7mgc6ul8qRTs8Aze3z0lZb/r2zkOY4jeTOc9FJS7Lw+Seh QsIQ== X-Gm-Message-State: AOAM533zbxs2H5AQ5gvQp7SCBithvpnouVxAtsKwCpkA1NO/RxHsDFk7 rL8p53QhJDfLV7584QZlp9NLoA== X-Received: by 2002:a1c:9cc5:: with SMTP id f188mr674223wme.171.1611256004490; Thu, 21 Jan 2021 11:06:44 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:44 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 20/25] hw/watchdog/cmsdk-apb-watchdog: Convert to use Clock input Date: Thu, 21 Jan 2021 19:06:17 +0000 Message-Id: <20210121190622.22000-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Switch the CMSDK APB watchdog device over to using its Clock input; the wdogclk_frq property is now ignored. Signed-off-by: Peter Maydell --- hw/watchdog/cmsdk-apb-watchdog.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c index b03bcb73628..9cad0c67da4 100644 --- a/hw/watchdog/cmsdk-apb-watchdog.c +++ b/hw/watchdog/cmsdk-apb-watchdog.c @@ -310,6 +310,15 @@ static void cmsdk_apb_watchdog_reset(DeviceState *dev) ptimer_transaction_commit(s->timer); } +static void cmsdk_apb_watchdog_clk_update(void *opaque) +{ + CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque); + + ptimer_transaction_begin(s->timer); + ptimer_set_period_from_clock(s->timer, s->wdogclk, 1); + ptimer_transaction_commit(s->timer); +} + static void cmsdk_apb_watchdog_init(Object *obj) { SysBusDevice *sbd = SYS_BUS_DEVICE(obj); @@ -319,7 +328,8 @@ static void cmsdk_apb_watchdog_init(Object *obj) s, "cmsdk-apb-watchdog", 0x1000); sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->wdogint); - s->wdogclk = qdev_init_clock_in(DEVICE(s), "WDOGCLK", NULL, NULL); + s->wdogclk = qdev_init_clock_in(DEVICE(s), "WDOGCLK", + cmsdk_apb_watchdog_clk_update, s); s->is_luminary = false; s->id = cmsdk_apb_watchdog_id; @@ -329,9 +339,9 @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp) { CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev); - if (s->wdogclk_frq == 0) { + if (!clock_has_source(s->wdogclk)) { error_setg(errp, - "CMSDK APB watchdog: wdogclk-frq property must be set"); + "CMSDK APB watchdog: WDOGCLK clock must be connected"); return; } @@ -342,7 +352,7 @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp) PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); ptimer_transaction_begin(s->timer); - ptimer_set_freq(s->timer, s->wdogclk_frq); + ptimer_set_period_from_clock(s->timer, s->wdogclk, 1); ptimer_transaction_commit(s->timer); } From patchwork Thu Jan 21 19:06:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 367862 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp847901jam; Thu, 21 Jan 2021 11:21:56 -0800 (PST) X-Google-Smtp-Source: ABdhPJwDQIif41BJCtcZgvqLJYTMVhyQ7cP4L1TyawaUBqaMQn5H6Ec4OR/LtIvfw/xRM6yPmGJV X-Received: by 2002:a25:ba08:: with SMTP id t8mr1190911ybg.316.1611256916522; Thu, 21 Jan 2021 11:21:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611256916; cv=none; d=google.com; s=arc-20160816; b=Oj4kEWjxhE43M2TbTOiPq8ygXojef+fbPIaUe54NkeZ72xa3AQBnG76ni4ke752rEW sW6Giv7efjv3azzNXI3+x3sJtRw/9hKBhq3vWyKQtNvsE+lKMGV+AID1tMaFkfqWRJcO +DcpgvqAjfnqUiILazD+ehBVfp907U72+XBN3xEYAY76rHBo1WwV8ZaxZr7Amn/WfLI9 WtfOc5E39f8DnF+ZzMjiVnDBNRwy9s1OLysl2WHavABFoj0g0KU46hu21UBqIic/ijUY q4e7iZNJiCQlbHqp9QmiTvKYsN/rH0IkJnPY1GQACl0r7kM12LZu2jeOBZ6+M6dt9iKa 3Vig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=drkjv5Dr4fNxDyNRqjV5mGa+nW4Kje9Rbck6xlQDEzo=; b=T1mkJKRgzknqLFlkJWM8V0HsGDJZHn1PQIFGqMsOGQ6iowaPbC64wym4NcY+LtT8UI XURu7Zo3Hf3/7l+p14I53rRjpYMg+ZiJ5CATJ1PhDN+X7xjDyVKUQ1LqMVgADltKfbzO SBnQ2IYxIGxCFPIA7sNZyNenLohB3cNgpGLg8gqYU6SxOKg/F1bCyhS9+b+nQ+ytsi4A OIw1qBkFumA7XNEDvVsMBM0O9ZaM0FpE9oqYCqISgFY4+kucclo6EoE/aaMKEEA0S3oL nMYBwFgA+FIc9Ft6tAoLdtZB2xFpomEYy7f3FQ3/u1qs4sW01tn9W+tjO+PyqTrUMj7c +o8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YHf0cUWq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r12si5683574ybp.197.2021.01.21.11.21.56 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jan 2021 11:21:56 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YHf0cUWq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59204 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2fWl-0007g2-At for patch@linaro.org; Thu, 21 Jan 2021 14:21:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56004) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIX-0002fb-Lf for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:13 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:42879) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI7-0005wf-2t for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:13 -0500 Received: by mail-wr1-x42a.google.com with SMTP id m4so2809967wrx.9 for ; Thu, 21 Jan 2021 11:06:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=drkjv5Dr4fNxDyNRqjV5mGa+nW4Kje9Rbck6xlQDEzo=; b=YHf0cUWqP75ModYpAPc8KsC8hT4kMqRKyGlWW9/za7CxJLWzpPZWtgsmH4nraxh6l7 cSEJv6v/joGmXITlKI6RKW92Mpxko0Jrmipncc9MX2UcEJFF5rN1rz4sCdr5mlnW1OuL 8w3FBu7AMx42+MV4315utqfjdZk20tulI7QsZGAwGfNwtmIgrLjQ5gTrepqwTY5jfaMS 3M6/7PruEd8btc1aNZuM2f0SYAUSpJEa0m1eCfCMigRwc6uvFpccNSEBmGsu25en1A6Q 7dYicb01BEBDeQMGMEb1C0vXNoBatu4jcCWpaapo2w4oBMWEarlQTsuMLeB7rMmee5YS bEAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=drkjv5Dr4fNxDyNRqjV5mGa+nW4Kje9Rbck6xlQDEzo=; b=m0SWbBahG8wLBHEdcKZewmtYxRVYpL5DrUj9IAiYDZfm1bhljg9eVnbJaGJ9ADcP8d qQfg3cREnxp4vjpsMcHvNAaxIckr5XZ31CP8ozIpCjTYIoT6LoMzKSlwsfcbU/MEVks7 OjdrGJtl75xOYCHnEIZIqEbqqebb7wG5hFENEyNBqz3dX8l3M6pC40S268uRgmDdg+w7 fZkBbHSrHgEIFtF7YR7He6jM6xFTq/kcrSds2+RS+5PdHhN7+H4cO5Ykzt/gFyCYfY05 Z2OvbwzMCT++rJpzhlvfLZxdL/ZmMqgnlKwkO2bOeaILachiU8ojbplvZLS2rvytPZJU SN0A== X-Gm-Message-State: AOAM5331JUUQKsfyVnkiqSbJvtGcN//lTCD0FnwNCwJaGztU52fR2WBt QaXdtiGTRSiNuyk2SKUWxGT85A== X-Received: by 2002:adf:dc89:: with SMTP id r9mr933062wrj.52.1611256005478; Thu, 21 Jan 2021 11:06:45 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:44 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 21/25] tests/qtest/cmsdk-apb-watchdog-test: Test clock changes Date: Thu, 21 Jan 2021 19:06:18 +0000 Message-Id: <20210121190622.22000-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that the CMSDK APB watchdog uses its Clock input, it will correctly respond when the system clock frequency is changed using the RCC register on in the Stellaris board system registers. Test that when the RCC register is written it causes the watchdog timer to change speed. Signed-off-by: Peter Maydell --- tests/qtest/cmsdk-apb-watchdog-test.c | 52 +++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel diff --git a/tests/qtest/cmsdk-apb-watchdog-test.c b/tests/qtest/cmsdk-apb-watchdog-test.c index c6add1fee85..9a4873a8314 100644 --- a/tests/qtest/cmsdk-apb-watchdog-test.c +++ b/tests/qtest/cmsdk-apb-watchdog-test.c @@ -15,6 +15,7 @@ */ #include "qemu/osdep.h" +#include "qemu/bitops.h" #include "libqtest-single.h" /* @@ -31,6 +32,11 @@ #define WDOGMIS 0x14 #define WDOGLOCK 0xc00 +#define SSYS_BASE 0x400fe000 +#define RCC 0x60 +#define SYSDIV_SHIFT 23 +#define SYSDIV_LENGTH 4 + static void test_watchdog(void) { g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); @@ -61,6 +67,50 @@ static void test_watchdog(void) g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); } +static void test_clock_change(void) +{ + uint32_t rcc; + + /* + * Test that writing to the stellaris board's RCC register to + * change the system clock frequency causes the watchdog + * to change the speed it counts at. + */ + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); + + writel(WDOG_BASE + WDOGCONTROL, 1); + writel(WDOG_BASE + WDOGLOAD, 1000); + + /* Step to just past the 500th tick */ + clock_step(80 * 500 + 1); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500); + + /* Rewrite RCC.SYSDIV from 16 to 8, so the clock is now 40ns per tick */ + rcc = readl(SSYS_BASE + RCC); + g_assert_cmpuint(extract32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH), ==, 0xf); + rcc = deposit32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH, 7); + writel(SSYS_BASE + RCC, rcc); + + /* Just past the 1000th tick: timer should have fired */ + clock_step(40 * 500); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1); + + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 0); + + /* VALUE reloads at following tick */ + clock_step(41); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000); + + /* Writing any value to WDOGINTCLR clears the interrupt and reloads */ + clock_step(40 * 500); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1); + writel(WDOG_BASE + WDOGINTCLR, 0); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); +} + int main(int argc, char **argv) { QTestState *s; @@ -71,6 +121,8 @@ int main(int argc, char **argv) s = qtest_start("-machine lm3s811evb"); qtest_add_func("/cmsdk-apb-watchdog/watchdog", test_watchdog); + qtest_add_func("/cmsdk-apb-watchdog/watchdog_clock_change", + test_clock_change); r = g_test_run(); From patchwork Thu Jan 21 19:06:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 367874 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp854699jam; Thu, 21 Jan 2021 11:32:39 -0800 (PST) X-Google-Smtp-Source: ABdhPJxxe43zx4cLR+R8ZMUYOOhyuo1KyfkXqTYA+bU9/hNe+zXWE9iR1a7WISowC3NN1wlGOfsI X-Received: by 2002:a25:1086:: with SMTP id 128mr1233469ybq.375.1611257559131; Thu, 21 Jan 2021 11:32:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611257559; cv=none; d=google.com; s=arc-20160816; b=Fd6t+h+iR3BafjY7nNWUI7aChIInbMdYObYUSo6w0cqm1E6Sj54Y2jngrsb8xwrrm5 YG3a+5Y1HTtmerh1f4wcodesSX0h/rwDf8MeugO7Jp2/D2qBiYdQoO+JIskijk4+XUzl iHd5biydpvHtnTYDQs9VJXbClIXt9wiIqNGGK2iU5B+yK6aeawwtTccD9Ov1FI1rgGCS aXr2IvEaZ0nGy5m4HX+1WHZ6I2kTqS9jRdVxL9afFXAKfiYEOpiMQwm+DB6rxcqSCEcZ YefRTJaLRJKjjTjwhyek8S4z+0+TSyPtA6i1UVjWfDtuqs7SZlDLwBpBTUQ1c8OPhbbq atng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=o6QQiJy5R4qmIV1z0aGnCLcQYm3mM8qRJ5jTAs1T+H8=; b=l4IGfmuBhDX+mGd/9wgW2QUZwXbF4VODr6rXASfwrA1eVHdUWGdMrnU2ky6CMV+D/5 g65p/WDBX+fX9FP/D7gydzXFpkiUmuNI9sT34mCWX8BbEV92HPSCmoppXE8vavwbXetS EI9hC9cwdQmwMLlBj/gBmRG2OKuNTy2kAnXzqyh1spJcxG/s2LPWzxw6tnXkVpFsve6c qJRnAwJIldQeVPMv2a22w9lPl0eFCsBeoPjOuUhMQrPT+vFmum0urEcUC2W1GML9D4hR r9kvCVqsRu7n8htzoyPqSHX8MFFNw4p99H3hDTN3xDd2uctnK6U/VZsmHG5RzYSWiQjq N4hA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZIts7p2S; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t15si5956741ybl.204.2021.01.21.11.32.39 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jan 2021 11:32:39 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZIts7p2S; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55330 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2fh8-0001FN-Iv for patch@linaro.org; Thu, 21 Jan 2021 14:32:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55990) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIW-0002dV-UC for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:12 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:40575) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI8-0005ww-Mc for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:12 -0500 Received: by mail-wr1-x42a.google.com with SMTP id c12so2816479wrc.7 for ; Thu, 21 Jan 2021 11:06:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=o6QQiJy5R4qmIV1z0aGnCLcQYm3mM8qRJ5jTAs1T+H8=; b=ZIts7p2SirGlVpgj+pmUABXAwdDoIRnny+XuuK8dCw7Oj7KL/umjn2C7T/UKu+qgal ZT2o4cpO0L55LtHBgOxX5qkFLrEd9/bJjkOzUzvZIuPv1CbN6LelHBLwX+gfOPaOsWCu YfI8Thho5dRD3GM24zPrJVh0At82R4bstvG2zvnDBCc4KiE8MMa8Uvr0G5fezNagRa2v 4ddl4ooHQX6PlVt3GdSobGFUd0xQZEPcAaSYsq7N4owfe2glYhCvGf7WAs+1meSTF0pW IpJxs8Zho3c3ZM00PARP1LVjxSoJpSetBhHye5ELdEFbUq/XjbPYAOhCnfInSL9CLT2V V7yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=o6QQiJy5R4qmIV1z0aGnCLcQYm3mM8qRJ5jTAs1T+H8=; b=o77vDIlyeLA5WrLs6leko3d3laz2v85j6jyHCh+gxSIBDNNLFl0yYQwynG53bZIG7u 6HF/jEdUhO/Gv5NCnA0+yq45AZupxPO0hOeKOuVq9ObqVe6qZqajSenmvfyusRKUtxaT 0DvNrEDWPvRMH+nYn58QnvSk7YSlGfA4pawmv9abwP/MdUcTtyR3zIycZqGXpRbI+rjz w+Nd42xe/LOlGnga4VAUGgY1GwC4tCnfQLX5a7qU1SRKmWkWsrdMs3HHJA8Z6UHMUFIn 12QMMnsm6vYkyTfCQnYod1hMuNZqmHU9/EwI0T6HwZKpH7EqtN93j5C5kNPLD1EX6JP1 VXHg== X-Gm-Message-State: AOAM530hPYIeSyJ32l4mCDP1G/3pizg0XIDU3McrPTjjHQCH8LPAWntr bm0bqvdKkbdPVzgb7dubjFsTqg== X-Received: by 2002:a5d:6204:: with SMTP id y4mr941451wru.48.1611256006367; Thu, 21 Jan 2021 11:06:46 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:45 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 22/25] hw/arm/armsse: Use Clock to set system_clock_scale Date: Thu, 21 Jan 2021 19:06:19 +0000 Message-Id: <20210121190622.22000-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use the MAINCLK Clock input to set the system_clock_scale variable rather than using the mainclk_frq property. Signed-off-by: Peter Maydell --- At some point we should make the SysTick take a Clock itself so that we can get rid of the system_clock_scale global entirely. (In fact we want two Clocks: one that is the CPU clock and one for the 'external reference clock' whose period is currently hardcoded at 1000ns in systick_scale()...) --- hw/arm/armsse.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 4349ce9bfdb..1da0c1be4c7 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -232,6 +232,16 @@ static void armsse_forward_sec_resp_cfg(ARMSSE *s) qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); } +static void armsse_mainclk_update(void *opaque) +{ + ARMSSE *s = ARM_SSE(opaque); + /* + * Set system_clock_scale from our Clock input; this is what + * controls the tick rate of the CPU SysTick timer. + */ + system_clock_scale = clock_ticks_to_ns(s->mainclk, 1); +} + static void armsse_init(Object *obj) { ARMSSE *s = ARM_SSE(obj); @@ -451,9 +461,11 @@ static void armsse_realize(DeviceState *dev, Error **errp) return; } - if (!s->mainclk_frq) { - error_setg(errp, "MAINCLK_FRQ property was not set"); - return; + if (!clock_has_source(s->mainclk)) { + error_setg(errp, "MAINCLK clock was not connected"); + } + if (!clock_has_source(s->s32kclk)) { + error_setg(errp, "S32KCLK clock was not connected"); } assert(info->num_cpus <= SSE_MAX_CPUS); @@ -1115,7 +1127,8 @@ static void armsse_realize(DeviceState *dev, Error **errp) */ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container); - system_clock_scale = NANOSECONDS_PER_SECOND / s->mainclk_frq; + /* Set initial system_clock_scale from MAINCLK */ + armsse_mainclk_update(s); } static void armsse_idau_check(IDAUInterface *ii, uint32_t address, From patchwork Thu Jan 21 19:06:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 367870 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp851402jam; Thu, 21 Jan 2021 11:28:17 -0800 (PST) X-Google-Smtp-Source: ABdhPJw+3t/P/cWlzK7/U6CeROfVDdqqG4LHk6l90IlyknMCha50wHxC82cz70SSU30CvYjDec85 X-Received: by 2002:a25:41c3:: with SMTP id o186mr1194796yba.503.1611257296908; Thu, 21 Jan 2021 11:28:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611257296; cv=none; d=google.com; s=arc-20160816; b=Olt/5kS1CamQUDkSuv45yUwRJ4kMxWi4tj7WtPjO4nXRgmoTrNw+gzdamFhR74ypfN vcvCoy8coBR/+H0IxhFi9xgTib6NhzGpGTRltjWfeoFhtMcOvIMDaBcrAz7CXTkUf4Mi WFfAdx27Y2ToLNQx25X18WjP1+2XW2wX5ydRLFqhlCozPVqF9F3rWoh0lxeubnIqeon1 dOwZN2WwIl7AV5nCjif7HYbsfnRB1vvSlaBp9LPvHttxJMFMWrdce/3biW/J47YIQ3sV JKmK49NtmBjp9pwFdb1OKP6Wf0pDeUPhv86UoVRvtPEprcXZ8X2cg7L4pxbfAUDeG3vu lgDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=YCoEevXZLQxxQgAERiSPZQlFXrrGQIKv0sEF5uZH6HM=; b=eixKKv5lMsl8PMgsPAohbEdfoog0qoin1fyqwr65EtnarBiZv/A32vYIb1Dl+3PXWu b2w84cwbQX0lWEEd19BwTBzM0KonxQ2NPxD76qYAVUa4ZDbwqp7iTZ3q8pxAC8gjlvyN Elz5+CWNa0wyDBFExtOziNO6wrjSxKJRo5jADQdD/5b5cZpRCPY0YN10NvQLyXW8vAPo HwPDucrbFjclUhxTaCJQG45ULonQA99BYLEn5j2lg/amILIXPWalvKIZ9XS1IeLCulq5 yY8yyffmHNZBlIawIZ6smcw/xIjv4UYgi0hDvYj0/2iG+RzixUVgPxveQQY/vqq5wVNS U/eA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=h5Wza61K; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d12si4564372ybq.304.2021.01.21.11.28.16 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jan 2021 11:28:16 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=h5Wza61K; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47732 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2fcu-0006H3-Dw for patch@linaro.org; Thu, 21 Jan 2021 14:28:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56000) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIX-0002f1-Ju for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:13 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:41149) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fI8-0005x5-T6 for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:13 -0500 Received: by mail-wr1-x434.google.com with SMTP id a12so2816945wrv.8 for ; Thu, 21 Jan 2021 11:06:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YCoEevXZLQxxQgAERiSPZQlFXrrGQIKv0sEF5uZH6HM=; b=h5Wza61KoGm9iDnKB7703GCM/t5IJ/EW2sCh1Mny+TLUdq8RJBDeH4qn59br2K65oc 3oDNvM3MaQ2kQkxCJI2jFcU3F/e1CxhzU5LA2+wOucxKe3Hshuwm59p2uuVVEDSjts68 z+igabGujM/LKnvm8Q8UTL91x04vVJcs7h66N4F24BNuyPS1gqLtaAkrbXyaom7Vw4M8 I8NGi+oYYhfWdVrx70u7jumAsLiS1ZV8pZcy/8ALqIIvTec0Z7Cf9UHfNbFzllzBdmBX KxmJ6oGD5c/aMgKb+tCNPNTBRaen7omeeA57TAZ/F5Sti4hT7kxYEL2YNDyVZs+WXTxB iM5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YCoEevXZLQxxQgAERiSPZQlFXrrGQIKv0sEF5uZH6HM=; b=RNzoj1W5ZHqWhUJ9S07R9+VNpliKTn1LnlZk5Kaxk6PwnEcbIvDcecgBMAyi0070Mm jNEBvhbLLpypExUwioJ+ySMQzWd44fkpo+a6YtkTQcYYyYSfHZydemaon+7re1MMxMUC 5mBs8BoUM8No7r4hRalP8VySRSkr8n+G9l9iBa6F34jOmhbibOB6ePsOB83kBiVWWN8n lrZ3lQ1mYtjhbbG16W0jabD6cIBosk2ZaZH6IEPp5gxun911BNidj+GRSrEFMhmXkoqe pzuK+8R4/TBabqvVxSVN99SKy5Ll58SqEgTotCrgiQmqkSPB2XV4gtiFxszJlJtGg1CZ SHSA== X-Gm-Message-State: AOAM530eIaY1MXK6zPOTrbjeAsMBzgDGNlSGj3s1QwTL9zoUhPIvBXnx jZnu8IGHk8DPjf8EY+fxWysKuQ== X-Received: by 2002:adf:d20b:: with SMTP id j11mr890437wrh.318.1611256007320; Thu, 21 Jan 2021 11:06:47 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:46 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 23/25] arm: Don't set freq properties on CMSDK timer, dualtimer, watchdog, ARMSSE Date: Thu, 21 Jan 2021 19:06:20 +0000 Message-Id: <20210121190622.22000-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove all the code that sets frequency properties on the CMSDK timer, dualtimer and watchdog devices and on the ARMSSE SoC device: these properties are unused now that the devices rely on their Clock inputs instead. Signed-off-by: Peter Maydell --- hw/arm/armsse.c | 7 ------- hw/arm/mps2-tz.c | 1 - hw/arm/mps2.c | 3 --- hw/arm/musca.c | 1 - hw/arm/stellaris.c | 3 --- 5 files changed, 15 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 1da0c1be4c7..7494afc630e 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -726,7 +726,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) * it to the appropriate PPC port; then we can realize the PPC and * map its upstream ends to the right place in the container. */ - qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq); qdev_connect_clock_in(DEVICE(&s->timer0), "pclk", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer0), errp)) { return; @@ -737,7 +736,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) object_property_set_link(OBJECT(&s->apb_ppc0), "port[0]", OBJECT(mr), &error_abort); - qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq); qdev_connect_clock_in(DEVICE(&s->timer1), "pclk", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer1), errp)) { return; @@ -748,7 +746,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) object_property_set_link(OBJECT(&s->apb_ppc0), "port[1]", OBJECT(mr), &error_abort); - qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq); qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) { return; @@ -907,7 +904,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) /* Devices behind APB PPC1: * 0x4002f000: S32K timer */ - qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK); qdev_connect_clock_in(DEVICE(&s->s32ktimer), "pclk", s->s32kclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) { return; @@ -1001,7 +997,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0, qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); - qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK); qdev_connect_clock_in(DEVICE(&s->s32kwatchdog), "WDOGCLK", s->s32kclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), errp)) { return; @@ -1012,7 +1007,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */ - qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq); qdev_connect_clock_in(DEVICE(&s->nswatchdog), "WDOGCLK", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), errp)) { return; @@ -1021,7 +1015,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) armsse_get_common_irq_in(s, 1)); sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000); - qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_frq); qdev_connect_clock_in(DEVICE(&s->swatchdog), "WDOGCLK", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), errp)) { return; diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 7acdf490f28..90caa914934 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -413,7 +413,6 @@ static void mps2tz_common_init(MachineState *machine) object_property_set_link(OBJECT(&mms->iotkit), "memory", OBJECT(system_memory), &error_abort); qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ); - qdev_prop_set_uint32(iotkitdev, "MAINCLK_FRQ", SYSCLK_FRQ); qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index cd1c215f941..39add416db5 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -346,7 +346,6 @@ static void mps2_common_init(MachineState *machine) object_initialize_child(OBJECT(mms), name, &mms->timer[i], TYPE_CMSDK_APB_TIMER); sbd = SYS_BUS_DEVICE(&mms->timer[i]); - qdev_prop_set_uint32(DEVICE(&mms->timer[i]), "pclk-frq", SYSCLK_FRQ); qdev_connect_clock_in(DEVICE(&mms->timer[i]), "pclk", mms->sysclk); sysbus_realize_and_unref(sbd, &error_fatal); sysbus_mmio_map(sbd, 0, base); @@ -355,7 +354,6 @@ static void mps2_common_init(MachineState *machine) object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer, TYPE_CMSDK_APB_DUALTIMER); - qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ); qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->sysclk); sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal); sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0, @@ -363,7 +361,6 @@ static void mps2_common_init(MachineState *machine) sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000); object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog, TYPE_CMSDK_APB_WATCHDOG); - qdev_prop_set_uint32(DEVICE(&mms->watchdog), "wdogclk-frq", SYSCLK_FRQ); qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->sysclk); sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal); sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0, diff --git a/hw/arm/musca.c b/hw/arm/musca.c index a9292482a06..945643c3cd7 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -385,7 +385,6 @@ static void musca_init(MachineState *machine) qdev_prop_set_uint32(ssedev, "EXP_NUMIRQ", mmc->num_irqs); qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor); qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); - qdev_prop_set_uint32(ssedev, "MAINCLK_FRQ", SYSCLK_FRQ); qdev_connect_clock_in(ssedev, "MAINCLK", mms->sysclk); qdev_connect_clock_in(ssedev, "S32KCLK", mms->s32kclk); /* diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 9b67c739ef2..5acb043a07e 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1415,9 +1415,6 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) if (board->dc1 & (1 << 3)) { /* watchdog present */ dev = qdev_new(TYPE_LUMINARY_WATCHDOG); - /* system_clock_scale is valid now */ - uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale; - qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk); qdev_connect_clock_in(dev, "WDOGCLK", qdev_get_clock_out(ssys_dev, "SYSCLK")); From patchwork Thu Jan 21 19:06:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 367877 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp857342jam; Thu, 21 Jan 2021 11:36:37 -0800 (PST) X-Google-Smtp-Source: ABdhPJz3mo0/qqLwTWoRBbmQrQqFBe2EpdX62qwYLi+vSY3GdutCPCjlyin4CGnezCMqzHlM6ZW/ X-Received: by 2002:a25:5842:: with SMTP id m63mr1481957ybb.148.1611257797908; Thu, 21 Jan 2021 11:36:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611257797; cv=none; d=google.com; s=arc-20160816; b=BK8tEIUY1dVsmwTtIK7z6/N37DbrnVDDfhnzAD+i9HrbijXqdVrbBo2P7bFMQnqCNb 1RxOVgdcfPxFmz0B1Lz1A6MJK4hYKL4eA9WbLX+eDeKmHiakV/P082TJqYtyvytg5q+8 IbFNleXO6JccY+4Re1IlPS7fnfa3xfrcXb7Zvb+3PRzq4I7d1Tvs6eVz9TTVhRVxIFQw oLDAKbeu92MySLXMDhIpc28mcuOk2YbIe1+d0jAKYRjR8VkHcEebI4ZA0+JbX0BATrkM 8OZOez58bZhfTz6RffLaBsJQ1qw5YH71xUtBHImKi0KPCeaSrFvHFQVYfNcNIrbZWMKJ 5GJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=M450OYz/GBhndtZoAmfzOIX2VnGdSC4wd81hH65n+S0=; b=ZgK+ynYM1OfxlModUxdVmy5mdH0vpHioL+n5NTWQ42ffVeNUNqMF4IlFP4JmL+5qkG 4mTx6rOKCCi3r2AiRzfIF/oERJ00GmxvZWGv7DT6w4mY6WXo2yaqG6EXxoFGwmiiLGbq finokGJ8mO7vxJXJfELsEGPB2jMOyKd1Du87Wdwg/OaaOiic3HK9Bhi0Cqjsfrlkfp5t HjCWkjbHPqWSlDfaCv7gRSJEQ7JyfUYZpL9FCmdEGLUJrdi880SgrzuhzuyeGB6d4T+K kNTtAnQg9XERakFFlu9cMrMmdvVoUy75cyY06x0CWl2LalZjReOCzjkTLbKWv2SBI6RH H1Xw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WXQ++Bmx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v1si4592410ybm.428.2021.01.21.11.36.37 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jan 2021 11:36:37 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WXQ++Bmx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41702 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2fkz-0007Ni-Ap for patch@linaro.org; Thu, 21 Jan 2021 14:36:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56082) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIa-0002me-B2 for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:16 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:44046) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fIC-0005xG-Kl for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:16 -0500 Received: by mail-wr1-x434.google.com with SMTP id d16so2145371wro.11 for ; Thu, 21 Jan 2021 11:06:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M450OYz/GBhndtZoAmfzOIX2VnGdSC4wd81hH65n+S0=; b=WXQ++Bmxm8z8NcWPFu3TTCoatxxvtPU7MtoIBY2yHLaCUX9aXqpB2Bm6P4LSjS59qz twq++8yV+YkJGo+8ndUSHPT/2YwhfYp5RMml/4OYpnXOEcG1+Mxf6BUkJKugES7GITcE RjwVaeMlJBegSzZ4dfGAn++AB5N9nwMCS8V43UX0fGjJlVSbMo9dBUYarbc3ip8fzZDT wTLV+U9XF6ZWka7z9KzAMtLFKcADhl7T09F3+SEgZT54JdW2jPKKxoeB5jJN9c0Y28Wf A6yYyKJPNyFID1WU8rV9x8bD8DjLYZGZc9gPphUBwV44XBZXE4p1c7TMg5uqaeCZBt66 jtbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M450OYz/GBhndtZoAmfzOIX2VnGdSC4wd81hH65n+S0=; b=FSAzIXdbLGpmCCpskz4Bz/UmMzFsd0RBhuXLXlKumIgBGSk+hCZcyU4c+BBuhXm9bk w445+rHpg76PqKDuhrs3q12vwLY+d9qtwRiPArLHUjI8PkdZ/XWltxWAfpmj2m+WPxH1 I+hzCNTW+MwaEEVNcj3fjX0oKrgYNotYLSZudhhtDy2Zg7FynxikYhn3G3cDiXknd5p+ ZQrA7R3aAzTkoiJqBrvKDhPsg+8ai2/WOpqTw4QhsYoHuu/+2e9QvuGWEdG2+hRN0W/3 mW4gMzWrDbiB4MKcboG0l/3Ith8IKs/7qaS/B9WvUFyMjfYjUr9CwbDhpJqIB3ZiMYHX WrYg== X-Gm-Message-State: AOAM533Cz6SpOQebc7J+YEB99R99ctOJcd1fk7Hz7JoDAZplo4ui1FO6 zfxEIjPDcLkRnsmzTOFdu23pyNgcZXj4fw== X-Received: by 2002:adf:ea0c:: with SMTP id q12mr926859wrm.126.1611256008326; Thu, 21 Jan 2021 11:06:48 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:47 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 24/25] arm: Remove frq properties on CMSDK timer, dualtimer, watchdog, ARMSSE Date: Thu, 21 Jan 2021 19:06:21 +0000 Message-Id: <20210121190622.22000-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now no users are setting the frq properties on the CMSDK timer, dualtimer, watchdog or ARMSSE SoC devices, we can remove the properties and the struct fields that back them. Signed-off-by: Peter Maydell --- include/hw/arm/armsse.h | 2 -- include/hw/timer/cmsdk-apb-dualtimer.h | 2 -- include/hw/timer/cmsdk-apb-timer.h | 2 -- include/hw/watchdog/cmsdk-apb-watchdog.h | 2 -- hw/arm/armsse.c | 2 -- hw/timer/cmsdk-apb-dualtimer.c | 6 ------ hw/timer/cmsdk-apb-timer.c | 6 ------ hw/watchdog/cmsdk-apb-watchdog.c | 6 ------ 8 files changed, 28 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index bfa1e79c4fe..676cd4f36b0 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -41,7 +41,6 @@ * + Clock input "S32KCLK": slow 32KHz clock used for a few peripherals * + QOM property "memory" is a MemoryRegion containing the devices provided * by the board model. - * + QOM property "MAINCLK_FRQ" is the frequency of the main system clock * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts. * (In hardware, the SSE-200 permits the number of expansion interrupts * for the two CPUs to be configured separately, but we restrict it to @@ -218,7 +217,6 @@ struct ARMSSE { /* Properties */ MemoryRegion *board_memory; uint32_t exp_numirq; - uint32_t mainclk_frq; uint32_t sram_addr_width; uint32_t init_svtor; bool cpu_fpu[SSE_MAX_CPUS]; diff --git a/include/hw/timer/cmsdk-apb-dualtimer.h b/include/hw/timer/cmsdk-apb-dualtimer.h index 3adbb01dd34..f3ec86c00b5 100644 --- a/include/hw/timer/cmsdk-apb-dualtimer.h +++ b/include/hw/timer/cmsdk-apb-dualtimer.h @@ -16,7 +16,6 @@ * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit * * QEMU interface: - * + QOM property "pclk-frq": frequency at which the timer is clocked * + Clock input "TIMCLK": clock (for both timers) * + sysbus MMIO region 0: the register bank * + sysbus IRQ 0: combined timer interrupt TIMINTC @@ -63,7 +62,6 @@ struct CMSDKAPBDualTimer { /*< public >*/ MemoryRegion iomem; qemu_irq timerintc; - uint32_t pclk_frq; Clock *timclk; CMSDKAPBDualTimerModule timermod[CMSDK_APB_DUALTIMER_NUM_MODULES]; diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h index 54f7ec8c502..c4c7eae8499 100644 --- a/include/hw/timer/cmsdk-apb-timer.h +++ b/include/hw/timer/cmsdk-apb-timer.h @@ -23,7 +23,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER) /* * QEMU interface: - * + QOM property "pclk-frq": frequency at which the timer is clocked * + Clock input "pclk": clock for the timer * + sysbus MMIO region 0: the register bank * + sysbus IRQ 0: timer interrupt TIMERINT @@ -35,7 +34,6 @@ struct CMSDKAPBTimer { /*< public >*/ MemoryRegion iomem; qemu_irq timerint; - uint32_t pclk_frq; struct ptimer_state *timer; Clock *pclk; diff --git a/include/hw/watchdog/cmsdk-apb-watchdog.h b/include/hw/watchdog/cmsdk-apb-watchdog.h index 34069ca6969..c6b3e78731e 100644 --- a/include/hw/watchdog/cmsdk-apb-watchdog.h +++ b/include/hw/watchdog/cmsdk-apb-watchdog.h @@ -16,7 +16,6 @@ * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit * * QEMU interface: - * + QOM property "wdogclk-frq": frequency at which the watchdog is clocked * + Clock input "WDOGCLK": clock for the watchdog's timer * + sysbus MMIO region 0: the register bank * + sysbus IRQ 0: watchdog interrupt @@ -53,7 +52,6 @@ struct CMSDKAPBWatchdog { /*< public >*/ MemoryRegion iomem; qemu_irq wdogint; - uint32_t wdogclk_frq; bool is_luminary; struct ptimer_state *timer; Clock *wdogclk; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 7494afc630e..513caa33a9a 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -48,7 +48,6 @@ static Property iotkit_properties[] = { DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), - DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0), DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), @@ -60,7 +59,6 @@ static Property armsse_properties[] = { DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), - DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0), DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false), diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c index 828127b366f..ef49f5852d3 100644 --- a/hw/timer/cmsdk-apb-dualtimer.c +++ b/hw/timer/cmsdk-apb-dualtimer.c @@ -533,11 +533,6 @@ static const VMStateDescription cmsdk_apb_dualtimer_vmstate = { } }; -static Property cmsdk_apb_dualtimer_properties[] = { - DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBDualTimer, pclk_frq, 0), - DEFINE_PROP_END_OF_LIST(), -}; - static void cmsdk_apb_dualtimer_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -545,7 +540,6 @@ static void cmsdk_apb_dualtimer_class_init(ObjectClass *klass, void *data) dc->realize = cmsdk_apb_dualtimer_realize; dc->vmsd = &cmsdk_apb_dualtimer_vmstate; dc->reset = cmsdk_apb_dualtimer_reset; - device_class_set_props(dc, cmsdk_apb_dualtimer_properties); } static const TypeInfo cmsdk_apb_dualtimer_info = { diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c index f053146d88f..ee51ce3369c 100644 --- a/hw/timer/cmsdk-apb-timer.c +++ b/hw/timer/cmsdk-apb-timer.c @@ -261,11 +261,6 @@ static const VMStateDescription cmsdk_apb_timer_vmstate = { } }; -static Property cmsdk_apb_timer_properties[] = { - DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTimer, pclk_frq, 0), - DEFINE_PROP_END_OF_LIST(), -}; - static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -273,7 +268,6 @@ static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data) dc->realize = cmsdk_apb_timer_realize; dc->vmsd = &cmsdk_apb_timer_vmstate; dc->reset = cmsdk_apb_timer_reset; - device_class_set_props(dc, cmsdk_apb_timer_properties); } static const TypeInfo cmsdk_apb_timer_info = { diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c index 9cad0c67da4..302f1711738 100644 --- a/hw/watchdog/cmsdk-apb-watchdog.c +++ b/hw/watchdog/cmsdk-apb-watchdog.c @@ -373,11 +373,6 @@ static const VMStateDescription cmsdk_apb_watchdog_vmstate = { } }; -static Property cmsdk_apb_watchdog_properties[] = { - DEFINE_PROP_UINT32("wdogclk-frq", CMSDKAPBWatchdog, wdogclk_frq, 0), - DEFINE_PROP_END_OF_LIST(), -}; - static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -385,7 +380,6 @@ static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data) dc->realize = cmsdk_apb_watchdog_realize; dc->vmsd = &cmsdk_apb_watchdog_vmstate; dc->reset = cmsdk_apb_watchdog_reset; - device_class_set_props(dc, cmsdk_apb_watchdog_properties); } static const TypeInfo cmsdk_apb_watchdog_info = { From patchwork Thu Jan 21 19:06:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 367871 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp851889jam; Thu, 21 Jan 2021 11:29:00 -0800 (PST) X-Google-Smtp-Source: ABdhPJyZyKhWOAdEv6sfXhYL79sZKA5A0MSOpVirtwImZSmGJmJQ5wZdE3ExnJZMDT+YYL/X2O/d X-Received: by 2002:a25:4b02:: with SMTP id y2mr1271486yba.353.1611257340816; Thu, 21 Jan 2021 11:29:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611257340; cv=none; d=google.com; s=arc-20160816; b=HYcx7nASBOYhtnxyxEcPcQ48jzTtx5Y50eFWaKAnawP4VkC2wsMYImlw/dBQttdmnm 7asGsPHqW1f3tA7kKqYjOMU+woZ8ZLyvmG0DTJKI9iZO4+5arUJ89r1XYeYJmmBILDAf +GTKkj4qh6fbUUh/8XcyobKQDHkZ2JdSx798rh56DWbzSTeFdLGxydbhvqnpyW75OI/l Is6H9m9u/BeIfxtm3iooFmG+zLR+6rd/ZhKEqLNehLR4HSWZVxSHXghWuLugliJWiubv RjCRYCIOEvwcaglwcOjC57iRXzKkKWgFoc6N2hClEjYayEFbJjx43sTwP4mfYKYz0crO ouhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vc7QCR7u1Td4e270u3SS7Eub90Z6eM3TU4b3gXUJds8=; b=JWHYT2Zyc+RY14g7rmozYA+YkLRFL71BKtv98881csa2A4SBeuaGcSUn96c9QAE3CL TIOnKCZd/jwnVNGeOuDpnQl53XQ7+Cb5kkwZlE3l6qBRReg57EEy9pHVh7gk1v85yqDE BdaPbrqHNfibAyz4ot2J4LwZGtwbgBywbbAG/8GQP8coNNJ/JmAE0tkqY1GyHZs641kX ctTp/J9X+iiYr4nW0UIk5M57fTJQQGEC0SHZA1bZqwWSYm9YSeWihIR9tVNmYpGkYXG7 AjZYRD762TaV5XosoSFZIQdRJrdsYm+UKI2v1lbh1OIP6J/tMboQmeymwdCEwlSfLeNJ eJRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ri8eI31u; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x2si5470702ybk.43.2021.01.21.11.29.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jan 2021 11:29:00 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ri8eI31u; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48266 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2fdc-0006WS-9m for patch@linaro.org; Thu, 21 Jan 2021 14:29:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56032) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2fIZ-0002j2-2w for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:15 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:38245) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2fIA-0005xU-R4 for qemu-devel@nongnu.org; Thu, 21 Jan 2021 14:07:14 -0500 Received: by mail-wr1-x42d.google.com with SMTP id a9so2813821wrt.5 for ; Thu, 21 Jan 2021 11:06:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vc7QCR7u1Td4e270u3SS7Eub90Z6eM3TU4b3gXUJds8=; b=ri8eI31uQ5rvNcDOJ0/bfBik8Or1KfvjxEdtCY36LpprRFRoZu8bxaCD9oC4Fq3drl 65FbTUe8/ZKJNygoUdZ4V+x77TBA57qmSknLvBi/R9y4TltwwmCIVcW7+WdU6AVereaS zKzfWx2o9AT+ykI9szphBo+EsbN9dlB8Yma4/Ms65jxo5fBjdc7/2cs2gcgSOuk1eWPm w4IWRYaPKkERVc5ulZx5xMXS8j46s/KpwdiFH/dmuV9JY7sDJ4ds44GEGYmVouXmVKBJ 8XQ5z5ExM+JOzaeX8bSZC8yafoLYcEjG4ZYU0lhWkfvgqVUVZWljHcHZ7RP722Eczub1 TVzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vc7QCR7u1Td4e270u3SS7Eub90Z6eM3TU4b3gXUJds8=; b=jbXqfa0yjoPwIMjMzbyU9lGDJ54wWKyRbzhgAYMgFA/o2uaepaC57mJrJq9RizJjWj G4u1HdfnrtmWsldKyC/iNZZaiSadFFWUiiKsVLlRLnEnhodaY+4drEMtuRHZfxOaWtqm nYzfnLVElb1isPucMGFgqO/ZUo7CvhZxiOcFbFzxGtbnxC9QcylWzrivrwoVuc2HcQSD ubRbQfOxo/RgFGFz6WvQ84goXPQyz61yBDd25UA+rX2nFHH0Y5HsOlsTI/fE1McLVvql ajqxuVgRlAV3+lID+WzQV8xcoF1VMvd6Acsa7YyPfVFxxfdaBaMdPprSSv0OpN0P3IXy MLBw== X-Gm-Message-State: AOAM532VFD60PYbq+ulMkwTSyx6islnhRCnEBBK1sEdPX/JlPQYnCcWT v5HLDNH0h1opjTytdT7fY2Xprg== X-Received: by 2002:adf:d085:: with SMTP id y5mr916110wrh.41.1611256009272; Thu, 21 Jan 2021 11:06:49 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m18sm9820686wrw.43.2021.01.21.11.06.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jan 2021 11:06:48 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 25/25] hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS Date: Thu, 21 Jan 2021 19:06:22 +0000 Message-Id: <20210121190622.22000-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210121190622.22000-1-peter.maydell@linaro.org> References: <20210121190622.22000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that the watchdog device uses its Clock input rather than being passed the value of system_clock_scale at creation time, we can remove the hack where we reset the STELLARIS_SYS at board creation time to force it to set system_clock_scale. Instead it will be reset at the usual point in startup and will inform the watchdog of the clock frequency at that point. Signed-off-by: Peter Maydell --- hw/arm/stellaris.c | 10 ---------- 1 file changed, 10 deletions(-) -- 2.20.1 Reviewed-by: Luc Michel Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 5acb043a07e..ad72c0959f1 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -780,16 +780,6 @@ static DeviceState *stellaris_sys_init(uint32_t base, qemu_irq irq, sysbus_mmio_map(sbd, 0, base); sysbus_connect_irq(sbd, 0, irq); - /* - * Normally we should not be resetting devices like this during - * board creation. For the moment we need to do so, because - * system_clock_scale will only get set when the STELLARIS_SYS - * device is reset, and we need its initial value to pass to - * the watchdog device. This hack can be removed once the - * watchdog has been converted to use a Clock input instead. - */ - device_cold_reset(dev); - return dev; }