From patchwork Mon Jan 25 10:09:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 370741 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07AD3C433E0 for ; Tue, 26 Jan 2021 05:22:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C77F922795 for ; Tue, 26 Jan 2021 05:21:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729889AbhAZFVt (ORCPT ); Tue, 26 Jan 2021 00:21:49 -0500 Received: from mail.kernel.org ([198.145.29.99]:44462 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727339AbhAYKLh (ORCPT ); Mon, 25 Jan 2021 05:11:37 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 45DBE225A9; Mon, 25 Jan 2021 10:09:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1611569365; bh=/caSJlOzi9QwZYCHXZhLX4f0JgFeqHckEpX4/pNTF1c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jIb89LY/RphhYgJMIj8DSE0x9sKFQnKTMasNpMzLiZJlXQ4gXjCoPVV/0ZcO8F1db +NcRsq4f8PDU95GKM8iLSQoG34eu+47I0iEcSHjVLkEpDNq1Yp7+yPx3Y/JbFw3FvS 9DUxaxD7MdehfLVjQGO+p8NdAJfNxwgWpnaZEKCTtUif3bXdNLWNPTQZOY/Dl/MWJe 5vmIaFk1+FjT5ZzJ6p4QByYbyhggwrb9iQKgpc9OABiQtf2Fgq/ApbaHemnIvdUCj6 DpNBjvzfK5gDyLQacny6OXy6DCx0lbwPTisgdUmg1XCUuO5oFy76mXUKMAyvCU7fah MsoqWvn16iGjg== From: Vinod Koul To: "Martin K . Petersen" Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , "James E . J . Bottomley" , Asutosh Das , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] scsi: dt-bindings: ufs: Add sm8250, sm8350 compatible strings Date: Mon, 25 Jan 2021 15:39:03 +0530 Message-Id: <20210125100906.4004908-2-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210125100906.4004908-1-vkoul@kernel.org> References: <20210125100906.4004908-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document "qcom,sm8250-ufshc" and "qcom,sm8350-ufshc" compatible string. Use of "qcom,sm8250-ufshc" is already present upstream, so add misiing documentation. "qcom,sm8350-ufshc" is for UFS HC found in SM8350 SoC. Signed-off-by: Vinod Koul Reviewed-by: Bjorn Andersson --- Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt index 415ccdd7442d..d8fd4df81743 100644 --- a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt +++ b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt @@ -14,6 +14,8 @@ Required properties: "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0" "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0" "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0" + "qcom,sm8250-ufshc", "qcom,ufshc", "jedec,ufs-2.0" + "qcom,sm8350-ufshc", "qcom,ufshc", "jedec,ufs-2.0" - interrupts : - reg : From patchwork Mon Jan 25 10:09:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 370290 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4969C433DB for ; Mon, 25 Jan 2021 10:13:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7CE1D2251D for ; Mon, 25 Jan 2021 10:13:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727359AbhAYKMW (ORCPT ); Mon, 25 Jan 2021 05:12:22 -0500 Received: from mail.kernel.org ([198.145.29.99]:44480 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727340AbhAYKLh (ORCPT ); Mon, 25 Jan 2021 05:11:37 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 4982A22512; Mon, 25 Jan 2021 10:09:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1611569369; bh=q5VWWPzg4C4SUHCK+RykuznWauwMATDOUvYvmNmEm1k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=A6GpUSnHC44x1/0BB5hRB699hn4GLDV5+HLXYe3ujy5l8moQ2B/PwZCLcNQofxjY/ FQQ5J4m9FiKdj3L+Fkm7Lwj8LRNQtQVSTIFnNXQIKBpSZkALs35r3j4fYCGPvl6m9K ysZJkS50sgX3hACbEdRmA/vLFRSIsxMcHSh54IXrYryEYmCFEU+KPq7MEMAGkCWaJy 5f/pQeuzEYumoi9Yhwqt5xv6VfGaFYNhty/7CWIkc7Bp8qarwUghLWfCB9EUCaqP+j tUGOKvoiN5zBCAa+1zOHjqssHb7MQuYxyt2kWU8i1nR6kppPCM+nZohnzYdQK2hFWT PWp3I/thJMduw== From: Vinod Koul To: Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , Andy Gross , Rob Herring , Manu Gautam , Asutosh Das , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 2/4] dt-bindings: phy: qcom, qmp: Add SM8350 UFS PHY bindings Date: Mon, 25 Jan 2021 15:39:04 +0530 Message-Id: <20210125100906.4004908-3-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210125100906.4004908-1-vkoul@kernel.org> References: <20210125100906.4004908-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the compatible strings for the UFS PHY found on SM8350 SoC. Signed-off-by: Vinod Koul Reviewed-by: Bjorn Andersson --- Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index 62c4f2ba5b9f..bf804c12fa5f 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -38,6 +38,7 @@ properties: - qcom,sm8250-qmp-modem-pcie-phy - qcom,sm8250-qmp-usb3-phy - qcom,sm8250-qmp-usb3-uni-phy + - qcom,sm8350-qmp-ufs-phy - qcom,sm8350-qmp-usb3-phy - qcom,sm8350-qmp-usb3-uni-phy - qcom,sdx55-qmp-usb3-uni-phy From patchwork Mon Jan 25 10:09:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 370183 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp3841831jam; Mon, 25 Jan 2021 02:14:26 -0800 (PST) X-Google-Smtp-Source: ABdhPJzlyGMJatmI6ugy3Jjgy3JrhzWK93TkhVaM/ms/1qlkd8MN+foe90kIl2g8y+dR39cfC/aZ X-Received: by 2002:aa7:d39a:: with SMTP id x26mr297333edq.51.1611569666276; Mon, 25 Jan 2021 02:14:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611569666; cv=none; d=google.com; s=arc-20160816; b=cUzUTnJwLu62XkBtLAc7mJcKhlDox6p5d7sPHqjX+lkwmM3JefL/deed1o1SIzXk+M 8KUwL+Ga0mSxGvFzOjrxv0nt3zKVyNsPjqzu+sFwGDb596sV4ub0z3o4vTuL4JKMrvhB oi1tQUIeMlsALi59TcMgBZDbgmlfO015s6p+OSTQwlFoaOdt1bFcE6ZMXoQjIbD/3C2y T7LVIsygCq6eAP1uCFx5TfFHegxpZI4iv2nkIx5DAFP4Ktvi5noXuZkc8pfQCHNWCf2A QdOj343lXk2z2/3eqxopp/BbIs5yTkxPq6VCEHYEEU94NPBkhPPwUmuqDd0Ki5NKy3ck ilxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=iVDOo2HSHBkvcQNmxe3s43I03rIuTNktEX+q5CmH0SI=; b=d7kuNF7Xc9v/3zJiVhQUK8VcVmG9BUgHb7qSOOl4AhvpeAYzW404kGtYI6jWw7j1R3 +S5tv6VNER9Z9BgZ46KyAasYxAFwFiRMzADN9BqRs9UyHVFILfhAzijKyGCIt+PORSSz jjZ3LLf+gJpamvY2XG30xMLvWh9Nid27Gv8/BT2jJ3jPV3euMkWrPxZOQgyOz1+UlOYb qM2kq0SAOiV2OxpbW9XPHD0ZBwHglXTK0Hr1tMO4otta2LQ33FJNq6x/H6y7DmVX20XU jRqRa0wlFUumPxl8KTZBM3tXTp+aqTYqj1LnFpGtix7fFGfHFq6UdAC/cqTE2/1bVhWG lxxQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=mNdiut+U; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id n2si7191617edi.25.2021.01.25.02.14.26; Mon, 25 Jan 2021 02:14:26 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=mNdiut+U; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727349AbhAYKMG (ORCPT + 15 others); Mon, 25 Jan 2021 05:12:06 -0500 Received: from mail.kernel.org ([198.145.29.99]:44506 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727343AbhAYKLU (ORCPT ); Mon, 25 Jan 2021 05:11:20 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 93AC22251D; Mon, 25 Jan 2021 10:09:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1611569373; bh=nba0Jv8m1xcS4I4Px7Vw3yzw2X5S8XBHwCaDESso34w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mNdiut+UDIZlWL4YI1aKoRUSyXyLsGrXAvSVH8AfDSG5LVXT4gvep0j/ZDe8/Vl8w FzzohcS8o55BCTg/f6oWO6udoX2CaGKsFz1uaZdJcu/r13WAwlW7dOJoAy7oiqLoPF h67L2qiTbGDt+le3cf2zlUQaanNXj8vAzI0Wg0OjBFskYfixmn/lSqtMUuZha/wWTF WX7yCDoUgO5F5Y1uWLY2F3YHIpUkBiBsPh8xaOKp/9bCrFnVHTH6OJyrhikJ0kZpTj so0gn25qwSN5KO5h75QV0NowoEh1uqhPLcvPQ2Y7FwYmD+kVPpdOkLbhImMK2T/wL4 Y4o/E41b0pN0Q== From: Vinod Koul To: Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , Andy Gross , Asutosh Das , linux-kernel@vger.kernel.org Subject: [PATCH 3/4] phy: qcom-qmp: Add UFS v4 registers found in SM8350 Date: Mon, 25 Jan 2021 15:39:05 +0530 Message-Id: <20210125100906.4004908-4-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210125100906.4004908-1-vkoul@kernel.org> References: <20210125100906.4004908-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the registers for few new registers found in SM8350. Also the UFS phy used in SM8350 seems to have different offsets than V4 phy, although it claims it is v4 phy, so add the new offsets with SM8350 tag instead of V4 tag. Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) -- 2.26.2 Reviewed-by: Bjorn Andersson diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index dff7be5a1cc1..bba1d5e3eb73 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -451,6 +451,7 @@ #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x40 #define QSERDES_V4_TX_LANE_MODE_1 0x84 #define QSERDES_V4_TX_LANE_MODE_2 0x88 +#define QSERDES_V4_TX_LANE_MODE_3 0x8C #define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x9c #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8 #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdC @@ -459,6 +460,13 @@ #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8 #define QSERDES_V4_TX_PI_QEC_CTRL 0x104 +/* Only for SM8350 QMP V4 Phy TX offsets different from V4 */ +#define QSERDES_SM8350_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178 +#define QSERDES_SM8350_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c +#define QSERDES_SM8350_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180 +#define QSERDES_SM8350_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184 +#define QSERDES_SM8350_TX_TRAN_DRVR_EMP_EN 0xc0 + /* Only for QMP V4 PHY - RX registers */ #define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 #define QSERDES_V4_RX_UCDR_SO_GAIN 0x014 @@ -514,6 +522,24 @@ #define QSERDES_V4_RX_DCC_CTRL1 0x1bc #define QSERDES_V4_RX_VTH_CODE 0x1c4 +/* Only for SM8350 QMP V4 Phy RX offsets different from V4 */ +#define QSERDES_SM8350_RX_RX_MODE_00_LOW 0x15c +#define QSERDES_SM8350_RX_RX_MODE_00_HIGH 0x160 +#define QSERDES_SM8350_RX_RX_MODE_00_HIGH2 0x164 +#define QSERDES_SM8350_RX_RX_MODE_00_HIGH3 0x168 +#define QSERDES_SM8350_RX_RX_MODE_00_HIGH4 0x16c +#define QSERDES_SM8350_RX_RX_MODE_01_LOW 0x170 +#define QSERDES_SM8350_RX_RX_MODE_01_HIGH 0x174 +#define QSERDES_SM8350_RX_RX_MODE_01_HIGH2 0x178 +#define QSERDES_SM8350_RX_RX_MODE_01_HIGH3 0x17c +#define QSERDES_SM8350_RX_RX_MODE_01_HIGH4 0x180 +#define QSERDES_SM8350_RX_RX_MODE_10_LOW 0x184 +#define QSERDES_SM8350_RX_RX_MODE_10_HIGH 0x188 +#define QSERDES_SM8350_RX_RX_MODE_10_HIGH2 0x18c +#define QSERDES_SM8350_RX_RX_MODE_10_HIGH3 0x190 +#define QSERDES_SM8350_RX_RX_MODE_10_HIGH4 0x194 +#define QSERDES_SM8350_RX_DCC_CTRL1 0x1a8 + /* Only for QMP V4 PHY - UFS PCS registers */ #define QPHY_V4_PCS_UFS_PHY_START 0x000 #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004 @@ -529,6 +555,7 @@ #define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 #define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148 #define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 +#define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL1 0x154 #define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158 #define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160 #define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168 From patchwork Mon Jan 25 10:09:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 370582 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp4634044jam; Mon, 25 Jan 2021 21:21:51 -0800 (PST) X-Google-Smtp-Source: ABdhPJxdK6jbwFAPtvc+IPymsxv3EId1reyuyh5dChwhYkDErJtizI6XVg4OtQYHEuYgJmEZXBuV X-Received: by 2002:a50:fd84:: with SMTP id o4mr3212839edt.340.1611638511138; Mon, 25 Jan 2021 21:21:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611638511; cv=none; d=google.com; s=arc-20160816; b=Sn2eES9o9zTybeC3Mnng6ZTwUYAYbvcWnQ94jsy6b37jknGpmgMm4uqOn9voRt4gU6 ry4bZLtTtP9xcmV3g6egAK2cwWkRL94mgOUmRsV2jlxjirg9LSxdzHDWwxWUdVKAby1u b6Z4ehJfuqUAZQph6gXBzWZtWNp60/DwDkLBWo/b5eeb+kDR/wB/j9vwzoLFQS8/w0Sm mQnOV1tiItLUO2kDgEcip+DW9Z3Lhc4nb3Ekx2ZRNa95Tn+pkptmAjTJaxVgmLs15kWv hiESWd0ORbsla0yY9hcjys2jR62kSJ15tcetB5ui2D8D2KF/f/yOgt7IQYbvBmr7jfQi 2g5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=j9R8ZH2L6uMD3kd0CZNfisi49TzCsCctqzeu7Etm+bU=; b=0rynZZ8BxDGK+gwYdKgvcusb0f2okNRRDMWJ18FDpmVQ+r6Kew3w24x6Mg7wC/kXbP LkqYq/bszvFGqMdPkI3oWCq3fniwsvdE4dfRGFJewWuglKu+4l30b47vv3/WXrAvT2so bcDuno8AZU4F0afPrQ5zRow9uk9jVgKS7P+iuw+lC3ggTvvade7OJmbPGXuZPvD61KBk JjNpRbb8rKPBMN+jr0LRdV2EZBx2MAB7dRspOVldz29PFL/9uxx/ttoc4caAkzfnUNRZ jaWZWFiRciC23NjwIjMbd45f4lrVfXZOb3f66h3manVeOGYJK4+NsJsuKf6w5Bw31gvJ c7Fg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=EkE9ElAl; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id b7si8445655edr.115.2021.01.25.21.21.50; Mon, 25 Jan 2021 21:21:51 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=EkE9ElAl; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726367AbhAZFVo (ORCPT + 15 others); Tue, 26 Jan 2021 00:21:44 -0500 Received: from mail.kernel.org ([198.145.29.99]:44516 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727348AbhAYKLh (ORCPT ); Mon, 25 Jan 2021 05:11:37 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id DF8E022525; Mon, 25 Jan 2021 10:09:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1611569376; bh=csNRSDZq1lb3mLDS5YF7UHl31dWqeJVOzDzSz5Ix6Fg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EkE9ElAlUBQKAgYi38PIAQnrnnwBk2PiO+Ph7g25NnS3QfJojAOPXxtG3k6hp83mY n6hR9TvKBPh3XMMbzlP91ifvbknrlkUJCpxwsLDhfg4qVXk5q3MaA6n0uSCW8ipdjA It2Ci7+bcfGLM3JLryIQDTVPtl4KDSMvtOQHOxtHL8vo5XvyKmbE+vWwsP5qBZqCAE XywNwqEmQvwadUQ9XdKV2DnjHvGLw9J3MqU0r7WzX94gkEbGLrg3SLkrz4gwZuPUUf dh+cSzGq/1/d07HvnkHTEvTNi4BXUjLsq16k6QYlG44PH9GelRLppEoZwokWb/NBsO JnBykOSudMt/A== From: Vinod Koul To: Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , Andy Gross , Asutosh Das , linux-kernel@vger.kernel.org Subject: [PATCH 4/4] phy: qcom-qmp: Add support for SM8350 UFS phy Date: Mon, 25 Jan 2021 15:39:06 +0530 Message-Id: <20210125100906.4004908-5-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210125100906.4004908-1-vkoul@kernel.org> References: <20210125100906.4004908-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the tables for init sequences for UFS QMP phy found in SM8350 SoC. Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp.c | 127 ++++++++++++++++++++++++++++ 1 file changed, 127 insertions(+) -- 2.26.2 Reviewed-by: Bjorn Andersson diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index dbc12a19b702..4a9d1010910d 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -1983,6 +1983,106 @@ static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), }; +static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x19), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x65), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), + + /* Rate B */ + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), +}; + +static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_SM8350_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_SM8350_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_SM8350_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_SM8350_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xf5), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_3, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x09), + QMP_PHY_INIT_CFG(QSERDES_SM8350_TX_TRAN_DRVR_EMP_EN, 0x0c), +}; + +static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_00_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_00_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_00_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_00_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_00_HIGH4, 0x3c), + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_01_LOW, 0xe0), + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_01_HIGH, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_01_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_01_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_01_HIGH4, 0xb7), + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_10_LOW, 0xe0), + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_10_HIGH, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_10_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_10_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_10_HIGH4, 0xb7), + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_DCC_CTRL1, 0x0c), +}; + +static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_PLL_CNTL, 0x03), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND, 0x06), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL1, 0x0e), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), +}; + static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), @@ -2971,6 +3071,30 @@ static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, }; +static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { + .type = PHY_TYPE_UFS, + .nlanes = 2, + + .serdes_tbl = sm8350_ufsphy_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), + .tx_tbl = sm8350_ufsphy_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl), + .rx_tbl = sm8350_ufsphy_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl), + .pcs_tbl = sm8350_ufsphy_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), + .clk_list = sdm845_ufs_phy_clk_l, + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sm8150_ufsphy_regs_layout, + + .start_ctrl = SERDES_START, + .pwrdn_ctrl = SW_PWRDN, + + .is_dual_lane_phy = true, +}; + static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { .type = PHY_TYPE_USB3, .nlanes = 1, @@ -4379,6 +4503,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { }, { .compatible = "qcom,sm8250-qmp-modem-pcie-phy", .data = &sm8250_qmp_gen3x2_pciephy_cfg, + }, { + .compatible = "qcom,sm8350-qmp-ufs-phy", + .data = &sm8350_ufsphy_cfg, }, { .compatible = "qcom,sm8350-qmp-usb3-phy", .data = &sm8350_usb3phy_cfg,