From patchwork Wed Jan 27 12:30:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 371536 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp217702jam; Wed, 27 Jan 2021 04:36:41 -0800 (PST) X-Google-Smtp-Source: ABdhPJzYujxTGLnsa02RzQ9VF9Ow2cPGVHl6alzb2FnF+0WBYCfI7IueG8GT2g9Avn5H98QSVfeF X-Received: by 2002:aa7:da98:: with SMTP id q24mr6833725eds.370.1611751001718; Wed, 27 Jan 2021 04:36:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611751001; cv=none; d=google.com; s=arc-20160816; b=cyCot3dJaUPInPNqFCqUncE+aJe63Xx9oRs9z/g/GBT74mViGQnU2GAaAtdZjTVIHg VWHegqo3xN/9QF+CUFtimUbojMjbSP2sAL97JOrco6iWiEzgsIE4hITvUVHuuZ6RtFkL 6ReiFbMBG237ONhatzVyBkD2H5yL1HKE/4IOm+RtjLTJHGOmKw+wL3hOZv9cOUpJzCOX hIbMUXARXHr4RrITw/Jd83jONuEu8ohg0c5W+7bRRhCgDF89hRxuX6p+BvWMqQttu97k +2EyKetcvHC6+yVVdQKnylliPbSVuGMTicYkXvYA9Pn6/C3TLZjHMf6ye1roKN8ATiy8 bUSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=j0vS4BmSGyn4plJ00zeDdGZkOjySKyoJ+aoEOBb6jQE=; b=eo+hwNqkYAVErsxw0idaKfPAbrBYIACLQigloc6a9TKKaMHmH6IrovyFyUJ9YR8zbM PoptoFjR10S66eKS4tSVZHmagY7jR0nwyrwS+blsx6EyPStvrKXF6/20juAE55AZzkyD XiivA0YP6FdgnlQYoTn01VfrzotxndQmsjWZC34VFR/pTWDqCygl2r+WGShdL6J3rqqy CCgbprEeic+VUNjyK+GTyNFn+DvUj5cksMf3B5rBCrVAcldNgBC3SODtNsRrVqbmB4ul 2zlntdSHOqXIflKk6dAYZSNzDlqDIwXolXV+hqb60T6g26xp3t7EL5TvEMw1RH6MdL5A WiUw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=il2Ll244; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id p18si951098edx.541.2021.01.27.04.36.41; Wed, 27 Jan 2021 04:36:41 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=il2Ll244; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343529AbhA0Me4 (ORCPT + 15 others); Wed, 27 Jan 2021 07:34:56 -0500 Received: from mail.kernel.org ([198.145.29.99]:48416 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237981AbhA0McB (ORCPT ); Wed, 27 Jan 2021 07:32:01 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 8F99C20791; Wed, 27 Jan 2021 12:31:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1611750669; bh=PqbYn0GtD1KaVpQdsdfrygpTzurN/PmEZawMHpFS8eo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=il2Ll2444IAyVD3TkSPbooaNpHXqb8S+fz+e5FZDZ3MlZ8pdurqHqnrpfu7Omo6KV GPhs7BscWie2DT6qAO+xUmSzqN1H7kJYg+A0fuEw6NrDUmY/87UGlF4SD2mxodcwqw fWRgAkyoC63jxtqlk9gVSLFBG9OyabsdvazkO5NYmm+IShtLCUJTLcTvpMpNAzuLvl +ZbMs0/PhvENBcRXcEGoLBbGFrjVa779+sgPFB85SYob5clkqGpxbZ9DAopmzcXtvJ 4p3rTLcYElGKunsrKt5iai6pwzuJdY/tyIbB4bqJEYYfCCwUygPpfsMkGaEQsEcCCm 49DvONwcKJ4jw== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Andy Gross , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v2 2/6] soc: qcom: aoss: Add SM8350 compatible Date: Wed, 27 Jan 2021 18:00:50 +0530 Message-Id: <20210127123054.263231-3-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210127123054.263231-1-vkoul@kernel.org> References: <20210127123054.263231-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add SM8350 compatible to the qcom_aoss binding and driver. Acked-by: Rob Herring Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt | 1 + drivers/soc/qcom/qcom_aoss.c | 1 + 2 files changed, 2 insertions(+) -- 2.26.2 diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt index 953add19e937..19c059e44681 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt @@ -20,6 +20,7 @@ power-domains. "qcom,sdm845-aoss-qmp" "qcom,sm8150-aoss-qmp" "qcom,sm8250-aoss-qmp" + "qcom,sm8350-aoss-qmp" - reg: Usage: required diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c index b5840d624bc6..53acb9423bd6 100644 --- a/drivers/soc/qcom/qcom_aoss.c +++ b/drivers/soc/qcom/qcom_aoss.c @@ -600,6 +600,7 @@ static const struct of_device_id qmp_dt_match[] = { { .compatible = "qcom,sdm845-aoss-qmp", }, { .compatible = "qcom,sm8150-aoss-qmp", }, { .compatible = "qcom,sm8250-aoss-qmp", }, + { .compatible = "qcom,sm8350-aoss-qmp", }, {} }; MODULE_DEVICE_TABLE(of, qmp_dt_match); From patchwork Wed Jan 27 12:30:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 371535 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp217669jam; Wed, 27 Jan 2021 04:36:38 -0800 (PST) X-Google-Smtp-Source: ABdhPJwF6Gf9zoRgcHQ5icKjDvpJBqkwLjufjojfbKjmvhSnpje+fhHyAQ0JOXlT9ITpJWj/C3Rq X-Received: by 2002:a17:906:30cd:: with SMTP id b13mr6653861ejb.336.1611750998436; Wed, 27 Jan 2021 04:36:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611750998; cv=none; d=google.com; s=arc-20160816; b=sxTZMKc2DU/vSk3vdAb96vTpYp3meSk8Z11PqnwcOZEA7vsqqK9tLRzuv4V3QrLy1P dTsxnHnwgTnKEzAdVI/5YlMqKRKiRFo6DcND4tVI6n2K9jlVbq3kXaGJn6LlkTWfuOuC QawqE5JwjrSzgyZwgsph0c8OrAnijlZ7TWY1NVHzaTn4pb660yg55Xf9jWntEPR4YOH6 hSZa0ZGIkPl7qSg3LtTNa33s1qspH4gJ1dxdhHlpkLV+17ECWsU0UWX7MgOqBLXklcyP J6DEUHxdRej/aqY8128E+LFE6PDQU7Br9tgZiuIHpLvkH7stsGYUyh0a6GpV91k0wcVY Ninw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=/LXXhVG8F5HqQxZ9I9cy0chmWmKY7QgesJGLxMzbSmw=; b=WNqxBLmiX+VBolGn9bDKwQYlDQM52lzU42lgPqiXhe/rBY1QhI+kV9aYsRBqX5JvmA /OofGSUZlT0X2CEDvy6vxx/9neytwR8Pe5SjnqTTfdb6P45i5kn0ztbjhKTezoD13syo jhqkOi1gd2ZZd3zVl5/rhiPAZGFXHuuNIoTu2BiqMOG0G+USELWOYiy/c9X1UTNPbAMK S9NoI0iSopic/fiIqvyFnar861A5lhaPspoNq3viVQ6Wp3HabnyKEoSNElfUinyBTDYK m5rrDvNCKDMDdoK+AS2QIHYwYHPLpfvQe8l4U0RsFIqqfv6wcRtjDq6h3PmvQd6YoJIm yTjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=kgQAPp57; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id p18si951098edx.541.2021.01.27.04.36.38; Wed, 27 Jan 2021 04:36:38 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=kgQAPp57; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343533AbhA0MfI (ORCPT + 15 others); Wed, 27 Jan 2021 07:35:08 -0500 Received: from mail.kernel.org ([198.145.29.99]:48462 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237989AbhA0McF (ORCPT ); Wed, 27 Jan 2021 07:32:05 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 96E4C20795; Wed, 27 Jan 2021 12:31:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1611750676; bh=jmcfRNN25i2ohsqZwDtxcf2Xb7zyD6uyGntHaZ9vuHE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kgQAPp57Qbr33NJcFVXZ58Mb22Hnd4MK+G1+D7Q4O5knUHLM+XUzdJ8K5RxpPLken LN38h2e0VHuJMaxbNQmXrLwMyNKgLmR6VK/tTK32hcwBfmdsvlRL229cZFbD7ZYAFN cv4FfcmmkhTJCC/te/xi6QCS3BL946MyD6k0CzZ3Q1l20KmoglPfKuTijclkt1Oglf FsRQBmZ5OZRJ0IVM0Zb6xECG8goWnohPBgMg7wyWl0SbWLbJD50n32FXx+EoeY0Q7O PCL2AXNtvIjT10vW/Vc6JI4yclWuphyuTb3QPNcLexA3dyVFRbfeaeb7sn5CQmh7Rq YYEV1WE2QVYtQ== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Andy Gross , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/6] dt-bindings: firmware: scm: Add SM8250 and SM8350 compatible Date: Wed, 27 Jan 2021 18:00:52 +0530 Message-Id: <20210127123054.263231-5-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210127123054.263231-1-vkoul@kernel.org> References: <20210127123054.263231-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add compatible for SM8150 and SM8350 SoCs. Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/firmware/qcom,scm.txt | 2 ++ 1 file changed, 2 insertions(+) -- 2.26.2 diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt index 78456437df5f..a884955f861e 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt @@ -22,6 +22,8 @@ Required properties: * "qcom,scm-sc7180" * "qcom,scm-sdm845" * "qcom,scm-sm8150" + * "qcom,scm-sm8250" + * "qcom,scm-sm8350" and: * "qcom,scm" - clocks: Specifies clocks needed by the SCM interface, if any: From patchwork Wed Jan 27 12:30:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 371635 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC702C433E0 for ; Wed, 27 Jan 2021 12:36:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 824672074F for ; Wed, 27 Jan 2021 12:36:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232501AbhA0MfO (ORCPT ); Wed, 27 Jan 2021 07:35:14 -0500 Received: from mail.kernel.org ([198.145.29.99]:48484 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237980AbhA0McG (ORCPT ); Wed, 27 Jan 2021 07:32:06 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id F00722074F; Wed, 27 Jan 2021 12:31:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1611750679; bh=GmjgY426z/sS2GGhDxwZCGR9UwMivBtL2rvCNOwhS5Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Hb2oDPWk1Eg9lExTwO1I5fqbBqskl4BG4bfe6PeieWOmyFGFv/kjXho+5x96eaXC4 pcnJfgT7nsmXJ2xJmNBzBnBfQRpxlTXTAs+RbSel88T7JlCTrlQBy5dGa4IXSZnZyE KbnrXzhFgad7mpIj4rPMCA8d9PuOSA/IfZGXvww+gkAujD9MDdKMzX7SATKv5vpCvU rFHAJGVCMO+evKUE7KG0vg7lJ0r5Q4d3TqUBDmSVAoub82Mjee9kSBE5esF/JChKFg tEaNhs1X0cFtvOdh1y2zcCwLp3ycfwsFWuW58mN+/rwb6WEIIvwOWQSoG+tbDQzZMr CHSkYIzuMNABQ== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Andy Gross , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/6] arm64: dts: qcom: Add basic devicetree support for SM8350 SoC Date: Wed, 27 Jan 2021 18:00:53 +0530 Message-Id: <20210127123054.263231-6-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210127123054.263231-1-vkoul@kernel.org> References: <20210127123054.263231-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add basic devicetree support for Qualcomm Technologies, Inc SM8350 SoC. This adds gcc, pinctrl, reserved memory, uart, cpu nodes for this SoC. Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 499 +++++++++++++++++++++++++++ 1 file changed, 499 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8350.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi new file mode 100644 index 000000000000..29af0b931690 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -0,0 +1,499 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Linaro Limaited + */ + +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + clock-output-names = "xo_board"; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo685"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo685"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_100>; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo685"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_200>; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo685"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_300>; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo685"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_400>; + L2_400: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo685"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_500>; + L2_500: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo685"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_600>; + L2_600: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo685"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_700>; + L2_700: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sm8350", "qcom,scm"; + #reset-cells = <1>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: memory@80000000 { + reg = <0x0 0x80000000 0x0 0x600000>; + no-map; + }; + + xbl_aop_mem: memory@80700000 { + no-map; + reg = <0x0 0x80700000 0x0 0x160000>; + }; + + cmd_db: memory@80860000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x80860000 0x0 0x20000>; + no-map; + }; + + reserved_xbl_uefi_log: memory@80880000 { + reg = <0x0 0x80880000 0x0 0x14000>; + no-map; + }; + + smem_mem: memory@80900000 { + reg = <0x0 0x80900000 0x0 0x200000>; + no-map; + }; + + cpucp_fw_mem: memory@80b00000 { + reg = <0x0 0x80b00000 0x0 0x100000>; + no-map; + }; + + cdsp_secure_heap: memory@80c00000 { + reg = <0x0 0x80c00000 0x0 0x4600000>; + no-map; + }; + + pil_camera_mem: mmeory@85200000 { + reg = <0x0 0x85200000 0x0 0x500000>; + no-map; + }; + + pil_video_mem: memory@85700000 { + reg = <0x0 0x85700000 0x0 0x500000>; + no-map; + }; + + pil_cvp_mem: memory@85c00000 { + reg = <0x0 0x85c00000 0x0 0x500000>; + no-map; + }; + + pil_adsp_mem: memory@86100000 { + reg = <0x0 0x86100000 0x0 0x2100000>; + no-map; + }; + + pil_slpi_mem: memory@88200000 { + reg = <0x0 0x88200000 0x0 0x1500000>; + no-map; + }; + + pil_cdsp_mem: memory@89700000 { + reg = <0x0 0x89700000 0x0 0x1e00000>; + no-map; + }; + + pil_ipa_fw_mem: memory@8b500000 { + reg = <0x0 0x8b500000 0x0 0x10000>; + no-map; + }; + + pil_ipa_gsi_mem: memory@8b510000 { + reg = <0x0 0x8b510000 0x0 0xa000>; + no-map; + }; + + pil_gpu_mem: memory@8b51a000 { + reg = <0x0 0x8b51a000 0x0 0x2000>; + no-map; + }; + + pil_spss_mem: memory@8b600000 { + reg = <0x0 0x8b600000 0x0 0x100000>; + no-map; + }; + + pil_modem_mem: memory@8b800000 { + reg = <0x0 0x8b800000 0x0 0x10000000>; + no-map; + }; + + hyp_reserved_mem: memory@d0000000 { + reg = <0x0 0xd0000000 0x0 0x800000>; + no-map; + }; + + pil_trustedvm_mem: memory@d0800000 { + reg = <0x0 0xd0800000 0x0 0x76f7000>; + no-map; + }; + + qrtr_shbuf: memory@d7ef7000 { + reg = <0x0 0xd7ef7000 0x0 0x9000>; + no-map; + }; + + chan0_shbuf: memory@d7f00000 { + reg = <0x0 0xd7f00000 0x0 0x80000>; + no-map; + }; + + chan1_shbuf: memory@d7f80000 { + reg = <0x0 0xd7f80000 0x0 0x80000>; + no-map; + }; + + removed_mem: memory@d8800000 { + reg = <0x0 0xd8800000 0x0 0x6800000>; + no-map; + }; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + soc: soc@0 { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sm8350"; + reg = <0x0 0x00100000 0x0 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clock-names = "bi_tcxo", "sleep_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + }; + + ipcc: mailbox@408000 { + compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; + reg = <0 0x00408000 0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + qupv3_id_1: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x009c0000 0x0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc 121>, + <&gcc 122>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + uart2: serial@98c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0 0x0098c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc 83>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart3_default_state>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x40000>; + #hwlock-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm8350-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; + qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, + <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, + <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, + <156 716 12>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + aoss_qmp: qmp@c300000 { + compatible = "qcom,sm8350-aoss-qmp"; + reg = <0 0x0c300000 0 0x100000>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + #power-domain-cells = <1>; + }; + + tlmm: pinctrl@f100000 { + compatible = "qcom,sm8350-tlmm"; + reg = <0 0x0f100000 0 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 203>; + + qup_uart3_default_state: qup-uart3-default-state { + rx { + pins = "gpio18"; + function = "qup3"; + }; + tx { + pins = "gpio19"; + function = "qup3"; + }; + }; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupts = ; + }; + + timer@17c20000 { + compatible = "arm,armv7-timer-mem"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + reg = <0x0 0x17c20000 0x0 0x1000>; + clock-frequency = <19200000>; + + frame@17c21000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x0 0x17c21000 0x0 0x1000>, + <0x0 0x17c22000 0x0 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = ; + reg = <0x0 0x17c23000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = ; + reg = <0x0 0x17c25000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = ; + reg = <0x0 0x17c27000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = ; + reg = <0x0 0x17c29000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = ; + reg = <0x0 0x17c2b000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = ; + reg = <0x0 0x17c2d000 0x0 0x1000>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@18200000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , , + , ; + + rpmhcc: clock-controller { + compatible = "qcom,sm8350-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; From patchwork Wed Jan 27 12:30:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 371534 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp217528jam; 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[23.128.96.18]) by mx.google.com with ESMTP id p18si951098edx.541.2021.01.27.04.36.25; Wed, 27 Jan 2021 04:36:25 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=V13Gzbc6; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237729AbhA0MfP (ORCPT + 15 others); Wed, 27 Jan 2021 07:35:15 -0500 Received: from mail.kernel.org ([198.145.29.99]:48504 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237847AbhA0McG (ORCPT ); Wed, 27 Jan 2021 07:32:06 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 60210207A0; Wed, 27 Jan 2021 12:31:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1611750683; bh=GgmsYgRnqPem1diFVqgBfF6jWftAlLJThW/+Et9aoVs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=V13Gzbc6cr5l7CJcx1xJtajs6OLek3RBtod1GBQ4VQL7Ma6igq6/3+WBsuee8NYSV KD0gxH1rlzYyLyJWEvXVMalCVZeSzI/m0/4sLxXGJzMjdn9z3C1CXxzUOeAqJRghiw 4sz8egaHFW6zPYvS3ZVpXnAezNygRrJIqHNLqV9QA/SCK8tI/po3myNAeage+asNdt rFFWh1r8EfsqNBxed2dEhss4ciHWJQPJprYDdQ6w7Fs/vgRCPS3CtZGIusLB6K6usV GsAkEBOErMNwzAvyblIHLNLBgM+xGrWXtoo2DUKaKdW03x13BEocF1T3VTbZETGCFx +2rnYCDTzounA== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Andy Gross , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/6] arm64: dts: qcom: Add basic devicetree support for SM8350-MTP board Date: Wed, 27 Jan 2021 18:00:54 +0530 Message-Id: <20210127123054.263231-7-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210127123054.263231-1-vkoul@kernel.org> References: <20210127123054.263231-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add basic devicetree support for Qualcomm Technologies, Inc SM8350 SoC MTP board. This enabled uart node and adds rpmh-regulators present for this board. Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sm8350-mtp.dts | 250 ++++++++++++++++++++++++ 2 files changed, 251 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8350-mtp.dts -- 2.26.2 diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 5113fac80b7a..25f8a69ed530 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -49,3 +49,4 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts new file mode 100644 index 000000000000..8923657579fb --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Linaro Limited + */ + +/dts-v1/; + +#include +#include "sm8350.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. sm8350 MTP"; + compatible = "qcom,sm8350-mtp", "qcom,sm8350"; + + aliases { + serial0 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + pm8350-rpmh-regulators { + compatible = "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + + vdd-l1-l4-supply = <&vreg_s11b_0p95>; + vdd-l2-l7-supply = <&vreg_bob>; + vdd-l3-l5-supply = <&vreg_bob>; + vdd-l6-l9-l10-supply = <&vreg_s11b_0p95>; + vdd-l8-supply = <&vreg_s2c_0p8>; + + vreg_s10b_1p8: smps10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_s11b_0p95: smps11 { + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_s12b_1p25: smps12 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1360000>; + }; + + vreg_l1b_0p88: ldo1 { + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p07: ldo2 { + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l3b_0p9: ldo3 { + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + }; + + vreg_l5b_0p88: ldo5 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <888000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p2: ldo6 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1208000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p96: ldo7 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l9b_1p2: ldo9 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + pm8350c-rpmh-regulators { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l12-supply = <&vreg_s1c_1p86>; + vdd-l2-l8-supply = <&vreg_s1c_1p86>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>; + vdd-l6-l9-l11-supply = <&vreg_bob>; + vdd-l10-supply = <&vreg_s12b_1p25>; + + vdd-bob-supply = <&vph_pwr>; + + vreg_s1c_1p86: smps1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1952000>; + }; + + vreg_s2c_0p8: smps2 { + regulator-min-microvolt = <640000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_s10c_1p05: smps10 { + regulator-min-microvolt = <1048000>; + regulator-max-microvolt = <1128000>; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p8: ldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2c_1p8: ldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l3c_3p0: ldo3 { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l4c_uim1: ldo4 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l5c_uim2: ldo5 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l6c_1p8: ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p96: ldo9 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l10c_1p2: ldo10 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l11c_2p96: ldo11 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l12c_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l13c_3p0: ldo13 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + }; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <52 8>; +}; + +&uart2 { + status = "okay"; +};