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[192.237.175.120]) by mx.google.com with ESMTPS id j130si9041058ioe.163.2018.03.05.08.07.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Mar 2018 08:07:19 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=NgEvz33q; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1essbC-00075M-7e; Mon, 05 Mar 2018 16:04:26 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1essbB-000759-C7 for xen-devel@lists.xenproject.org; Mon, 05 Mar 2018 16:04:25 +0000 X-Inumbo-ID: b8145568-208e-11e8-ba59-bc764e045a96 Received: from mail-wr0-x241.google.com (unknown [2a00:1450:400c:c0c::241]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id b8145568-208e-11e8-ba59-bc764e045a96; Mon, 05 Mar 2018 17:03:18 +0100 (CET) Received: by mail-wr0-x241.google.com with SMTP id k9so17802949wre.9 for ; Mon, 05 Mar 2018 08:04:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=A1CJzkhaY0MdOZRenjj2/2cHAJzmJOCvtf9fbzzOBh0=; b=NgEvz33q/H80RRhG8W2v/JkAMDKASoiY4cUiWAovauCq5WdAH5Z47VYSqB73U8JdPX 9UDnGblvnA8SLSw6Ph4QyakzCAj/8PUusOrO031T6MNIZUEhu9Wc1H7UqK/Fto9udcKR OcK/GQsTe3it37pP2D0MeNKpt7uDYwO9eBVPw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=A1CJzkhaY0MdOZRenjj2/2cHAJzmJOCvtf9fbzzOBh0=; b=VdqlStCfJtkHywRKoq9EYqj4klpkruR7ZWlWZ2JTUcdzQnfk+Tg5C8MJxIajc10K3w LieHdbwSAnt8xJ8pXzu+hWFFpEY9fDqg8pNZqBbSXIdXyvU+LpX0/I4e9HH7Z3OjdY/L NtXV/MJt1eMGC+8f0KPmKQ8RDR+QRaGkXZN+akFE2NnxwrXyF4ftvrUJ1Jt3Rvjmin04 GfsY87iTGWJiTP+vX3sPYh+3sBMaPTcjV0HhclVEGCzEtVEKAF8xX0TUc7uByNjdp8yS b7bBHCD0ZBrB28QLvh5TTDd0njZFam8vyUW+JX3EYQ+RsajNQSiKVMNs4kaBuleLW/yh MYiw== X-Gm-Message-State: APf1xPCaP955Awabvzv54lLHWvQ8fvWD9T9ap+QkZcpCNe2fkqfWNKRA vVSWGSeRYKy1m6gUjOYjE5w8nQ== X-Received: by 10.223.187.199 with SMTP id z7mr13605576wrg.58.1520265863356; Mon, 05 Mar 2018 08:04:23 -0800 (PST) Received: from e104803-lin.lan (mail.andrep.de. [217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:22 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:19 +0000 Message-Id: <20180305160415.16760-2-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 01/57] tools: ARM: vGICv3: Avoid inserting optional DT properties X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" When creating a GICv3 devicetree node, we currently insert the redistributor-stride and #redistributor-regions properties, with fixed values which are actually the architected ones. Since those properties are optional, and in the case of the stride only needed to cover for broken platforms, we don't need to describe them if they don't differ from the default values. This will always be the case for our constructed DomU memory map. So we drop those properties altogether and provide a clean and architected GICv3 DT node for DomUs. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall Acked-by: Wei Liu --- Changelog RFC ... v1: - improve commit message tools/libxl/libxl_arm.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/tools/libxl/libxl_arm.c b/tools/libxl/libxl_arm.c index 86f59c0d80..906fd0dcdf 100644 --- a/tools/libxl/libxl_arm.c +++ b/tools/libxl/libxl_arm.c @@ -525,14 +525,6 @@ static int make_gicv3_node(libxl__gc *gc, void *fdt) res = fdt_property(fdt, "interrupt-controller", NULL, 0); if (res) return res; - res = fdt_property_cell(fdt, "redistributor-stride", - GUEST_GICV3_RDIST_STRIDE); - if (res) return res; - - res = fdt_property_cell(fdt, "#redistributor-regions", - GUEST_GICV3_RDIST_REGIONS); - if (res) return res; - res = fdt_property_regs(gc, fdt, ROOT_ADDRESS_CELLS, ROOT_SIZE_CELLS, 2, gicd_base, gicd_size, From patchwork Mon Mar 5 16:03:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130662 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853649lja; Mon, 5 Mar 2018 08:07:03 -0800 (PST) X-Google-Smtp-Source: AG47ELuVN4p/QkQPm0qjYIa6NNnzmMyfUhwPspJynV/OryaAUVYy3ZXGNcxn3BLzIOAUSup4c78U X-Received: by 10.36.157.16 with SMTP id f16mr14164081itd.83.1520266023558; Mon, 05 Mar 2018 08:07:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266023; cv=none; d=google.com; s=arc-20160816; b=n8xqlOCXkst1Fw3flY63hrqOjiT2lwFQIDIQaKcOFu7Yn7cw/NSYbpY1v0fCgKAK69 F2nx9fSMEc8SqOd518QAC3t1rD73xab7l3DN3JZo7TDFEtlXo41exlI5M9r8r49VIItR m3rDwmqNcCtjOY6UGsQXhNuvtZlDhbrRYtZnB6z+UH09RhcmWr3l6D7nw17np3w27LNc +gALXsRXCDfWJIQY9jxWaP1yOJXCcKbzhiCWDiJazDJ8DJOSTfuCc+7fygqjpEfONPoZ mWT+8NfcGOSiGntVvgKj7UOaUuefAv8OwsB/yGVNLaCNfm5o+VWLicKSYYUIzD1mc8Nt rLnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=dZwe0GUzKQgCKtMy2/cm1JkmWY5SNodtbux6Dd3Kyqk=; b=GyrNo4Jpmh6Kz0Nh9hlgtg9/Cu0MEq3zCAdtH82iiBKBJ/Iy2Ap3WYXW3vlSTePUBb u0E9lzos/aBY1ByocepviuZHmMILdOglEQGa1dZEmhjkZK2Ucsh4QDuDP01ZpXr2ENCR G5oKB4KsVBO6z7dVdEncYHz1ccce/fIEIkLGHoDROEVXa8ZVq8tio+54q/efVp7t1s8V 2+fIXIBTRZRbTctF+MkZWZEj/OuC9q+CGQD6aDzdC+x/a5n37SoE13FDi1s0htjXR4BT latVVTazahyss5DeZDM6HMto8qPaEUcGXgbrGGXeKfo1fbb/QF9M6wFQMErUyQ4d/2Bj OcfA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Exuobkb+; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:23 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:20 +0000 Message-Id: <20180305160415.16760-3-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 02/57] ARM: vGICv3: clarify on GUEST_GICV3_RDIST_REGIONS symbol X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Normally there is only one GICv3 redistributor region, and we use that for DomU guests using a GICv3. Explain the background in a comment and why we need to keep the number of hardware regions for Dom0. Signed-off-by: Andre Przywara Acked-by: Julien Grall --- Changelog RFC ... v1: - Keep GUEST_GICV3_RDIST_REGIONS symbol around, just extend comments xen/arch/arm/vgic-v3.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 2ad8a6be62..d5b34a7d0f 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -1632,6 +1632,16 @@ static int vgic_v3_vcpu_init(struct vcpu *v) static inline unsigned int vgic_v3_rdist_count(struct domain *d) { + /* + * Normally there is only one GICv3 redistributor region. + * The GICv3 DT binding provisions for multiple regions, since there are + * platforms out there which need those (multi-socket systems). + * For Dom0 we have to live with the MMIO layout the hardware provides, + * so we have to copy the multiple regions - as the first region may not + * provide enough space to hold all redistributors we need. + * However DomU get a constructed memory map, so we can go with + * the architected single redistributor region. + */ return is_hardware_domain(d) ? vgic_v3_hw.nr_rdist_regions : GUEST_GICV3_RDIST_REGIONS; } @@ -1692,7 +1702,7 @@ static int vgic_v3_domain_init(struct domain *d) { d->arch.vgic.dbase = GUEST_GICV3_GICD_BASE; - /* XXX: Only one Re-distributor region mapped for the guest */ + /* A single Re-distributor region is mapped for the guest. */ BUILD_BUG_ON(GUEST_GICV3_RDIST_REGIONS != 1); d->arch.vgic.rdist_stride = GUEST_GICV3_RDIST_STRIDE; From patchwork Mon Mar 5 16:03:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130684 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2854110lja; Mon, 5 Mar 2018 08:07:23 -0800 (PST) X-Google-Smtp-Source: AG47ELsFlI/ll7dB1HlPiNNy80ENM+7tw/ayEGkDVdd0D7CaiwZPLmsLrALB1/l6nlKS2CJmoQ/d X-Received: by 10.107.160.74 with SMTP id j71mr17386423ioe.10.1520266043771; Mon, 05 Mar 2018 08:07:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266043; cv=none; d=google.com; s=arc-20160816; b=hKYFY4+ZzKrWvNskFU69znyjQEkzb7nZgMzwUJQmbxe3JKzu7v72EVnJdUVjUX9Go2 CgfvrfB+/gVCDuMli6CMaVoUXE3B6lEJb9cOTqQ8OEqvkv12E8TkmzVdzcdyTcFMKSfL dj33dJ5texCWRts0tYuZGeWnKI0j2VGjLorjahu3yF5nnmqLPByHVrNXYmBbqCvusnFr +57/qmHYyQtctfCBUawFppzo6zobtuCKgh555AarWkCi9i6tReRGZcmiD5gyvePUa0O+ RQRUOLuVQdTUGhUD5CbKKVhiMduqfooAcsuf0F1L06vQCWk78jqB7g+xcv+gSuHPSxTW ++iA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=o4Dz9OBTOP8dl4E+pSD8BGSxBqsv8812UQSmN55YAVU=; b=BA6fF14oRIpMy1Xng23sYl7sgMEqqYx4U8CAsJccXsChNd0EmkGkxiJ4jAu8Bjc5E0 l9+zHmuurN7koDD0nILu4nGZZi7ly4sVZOfzW/ZNu4OFbHZB+cT/KfBAjdqusWhn617x /y6NA7iNPB2loAIJJ3IoPkSKg4ZQMowrqodMRR41kq5H0keDu0A6l2sCy+W/kpb0RMG+ XhtDKW4znyQ0vMj/seAAvtF04TzaJP0sUvizg3gYonTsTNvJJLxk8DRpr5tteslmbVPG I8/umB6tMk1xjF19QwxCoSv+dX2I07Ngk3RJMdRbHpAkQFct23Uyca07yQLuKrUGbnIF Y6Aw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=G28Y9bdP; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:25 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:21 +0000 Message-Id: <20180305160415.16760-4-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 03/57] ARM: GICv3: use hardware GICv3 redistributor values for Dom0 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The code to generate the DT node or MADT table for Dom0 reaches into the domain's VGIC structure to learn the number of redistributor regions and their base addresses. Since those values are copied from the hardware, we can as well use those hardware values directly when setting up the hardware domain. This avoids the hardware GIC code to reference vGIC data structures. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- Changelog RFC ... v1: - Use GIC hardware values consistently in this function. xen/arch/arm/gic-v3.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 25c30bb9ea..b1f8a86409 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1162,13 +1162,11 @@ static int gicv3_make_hwdom_dt_node(const struct domain *d, if ( res ) return res; - res = fdt_property_cell(fdt, "redistributor-stride", - d->arch.vgic.rdist_stride); + res = fdt_property_cell(fdt, "redistributor-stride", gicv3.rdist_stride); if ( res ) return res; - res = fdt_property_cell(fdt, "#redistributor-regions", - d->arch.vgic.nr_regions); + res = fdt_property_cell(fdt, "#redistributor-regions", gicv3.rdist_count); if ( res ) return res; @@ -1178,7 +1176,7 @@ static int gicv3_make_hwdom_dt_node(const struct domain *d, * CPU interface and virtual cpu interfaces accessesed as System registers * So cells are created only for Distributor and rdist regions */ - new_len = new_len * (d->arch.vgic.nr_regions + 1); + new_len = new_len * (gicv3.rdist_count + 1); hw_reg = dt_get_property(gic, "reg", &len); if ( !hw_reg ) @@ -1406,13 +1404,13 @@ static int gicv3_make_hwdom_madt(const struct domain *d, u32 offset) /* Add Generic Redistributor */ size = sizeof(struct acpi_madt_generic_redistributor); - for ( i = 0; i < d->arch.vgic.nr_regions; i++ ) + for ( i = 0; i < gicv3.rdist_count; i++ ) { gicr = (struct acpi_madt_generic_redistributor *)(base_ptr + table_len); gicr->header.type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; gicr->header.length = size; - gicr->base_address = d->arch.vgic.rdist_regions[i].base; - gicr->length = d->arch.vgic.rdist_regions[i].size; + gicr->base_address = gicv3.rdist_regions[i].base; + gicr->length = gicv3.rdist_regions[i].size; table_len += size; } @@ -1425,8 +1423,7 @@ static unsigned long gicv3_get_hwdom_extra_madt_size(const struct domain *d) { unsigned long size; - size = sizeof(struct acpi_madt_generic_redistributor) - * d->arch.vgic.nr_regions; + size = sizeof(struct acpi_madt_generic_redistributor) * gicv3.rdist_count; size += sizeof(struct acpi_madt_generic_translator) * vgic_v3_its_count(d); From patchwork Mon Mar 5 16:03:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130701 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2855986lja; Mon, 5 Mar 2018 08:08:58 -0800 (PST) X-Google-Smtp-Source: AG47ELuSijA+RXNY+N2LYGyeBND/r60Ry+Mj2hGl5i5e5sI4zvNCKmAQtty8OF8+++KGQHdTOVtU X-Received: by 10.36.94.197 with SMTP id h188mr14422390itb.141.1520266041693; Mon, 05 Mar 2018 08:07:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266041; cv=none; d=google.com; s=arc-20160816; b=eZ0H36REHku9r0LpjmMJqvxD2hX/rCL8PKAeLDuj7ganmUa0mTjP6knsP6K3pL3AXS qqlh+Pxhwotyiojm6lDZkLJM02aLn8fc9lnSZzfAXl8u7R/kcdHKcpBFhCm09tLOHddL kfWqrMEWWyxwFs1Zl1IN0yEw+O6qg9bf/o8OkS3c0K35s/32CdjqsmRJOeHMK7wW11Ph HCZDYGOKTsagif4mwFN/ZiUU1Pv7w2k20rGSXyd2svspBIvJCgJD8dty5MpEkiHwwMij ultyvdUIu7UxVU4GkmYNEq/ToCISGHWPNeMAZ5qmTTsnUmPNO+JfBT07XvTdqNIV4tVH Optw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=AMBjnWTwXA2sRQldzrWi5116KkWBiF933fY+qNOE/kI=; b=AurLUwdGOwfgPkRPDvOez9RVHgNsVy+N3EAlxt3n4LUvhKJR9f8nE/dRFNckppz6K6 4RlIJibW7USxM4BKw6cZJZXuMYt7vLZsltdXM/Q9xVR6JW7Qf4V9TJEJdE7xh7otb2YV 74gELjdweRkVve8f2jg6DN1a4cfhWzymMWmfMaGisIhXVth9IiIMjnarVWX2Cdaaz6+L VAMsSDxeNNqwL4B04CrCwzUYIqxfUYhRhBZh5Z0Pp6GLhxXd8sKq5oQb8fopFWMOPykv 8jBgGOR+DPRvdKCFOhMeM7d89xlIpy0BCh62avGbauRwEMuHbJn0jVbfeF9Izax0FRg/ 8DFA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=LfuVLpmd; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:26 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:22 +0000 Message-Id: <20180305160415.16760-5-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 04/57] ARM: GICv3: simplify GICv3 redistributor stride handling X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Instead of hard coding the architected redistributor stride into the code, lets use a clear #define to the two values for GICv3 and GICv4 and clarify the algorithm to determine the needed stride value. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - no changes xen/arch/arm/gic-v3.c | 18 ++++++++++-------- xen/include/asm-arm/gic_v3_defs.h | 5 +++++ 2 files changed, 15 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index b1f8a86409..be1787b39a 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -690,6 +690,15 @@ static int __init gicv3_populate_rdist(void) do { typer = readq_relaxed(ptr + GICR_TYPER); + /* Set the architectural redist size if not overridden by DT. */ + if ( !gicv3.rdist_stride ) + { + if ( typer & GICR_TYPER_VLPIS ) + gicv3.rdist_stride = GICV4_GICR_SIZE; + else + gicv3.rdist_stride = GICV3_GICR_SIZE; + } + if ( (typer >> 32) == aff ) { this_cpu(rbase) = ptr; @@ -732,14 +741,7 @@ static int __init gicv3_populate_rdist(void) if ( gicv3.rdist_regions[i].single_rdist ) break; - if ( gicv3.rdist_stride ) - ptr += gicv3.rdist_stride; - else - { - ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ - if ( typer & GICR_TYPER_VLPIS ) - ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ - } + ptr += gicv3.rdist_stride; } while ( !(typer & GICR_TYPER_LAST) ); } diff --git a/xen/include/asm-arm/gic_v3_defs.h b/xen/include/asm-arm/gic_v3_defs.h index 65c9dc47cf..412e41afed 100644 --- a/xen/include/asm-arm/gic_v3_defs.h +++ b/xen/include/asm-arm/gic_v3_defs.h @@ -18,6 +18,8 @@ #ifndef __ASM_ARM_GIC_V3_DEFS_H__ #define __ASM_ARM_GIC_V3_DEFS_H__ +#include + /* * Additional registers defined in GIC v3. * Common GICD registers are defined in gic.h @@ -68,6 +70,9 @@ #define GICV3_GICD_IIDR_VAL 0x34c #define GICV3_GICR_IIDR_VAL GICV3_GICD_IIDR_VAL +#define GICV3_GICR_SIZE (2 * SZ_64K) +#define GICV4_GICR_SIZE (4 * SZ_64K) + #define GICR_CTLR (0x0000) #define GICR_IIDR (0x0004) #define GICR_TYPER (0x0008) From patchwork Mon Mar 5 16:03:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130703 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2856067lja; Mon, 5 Mar 2018 08:09:02 -0800 (PST) X-Google-Smtp-Source: AG47ELssYDR+kbZxy9UnjcrRuvkCkIm2NrGLorkWn1BnD6z73JQ09B1IyL6CY2eu+NxtkhOJmKUU X-Received: by 10.107.170.14 with SMTP id t14mr17900892ioe.98.1520266039903; Mon, 05 Mar 2018 08:07:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266039; cv=none; d=google.com; s=arc-20160816; b=EmBcSYGwhGqvpIeLoVaFNjwSRb6Aa6FRr1PmHud3a4FwN1ljGBIYMqvNY5tc9GgdIK gRNr7YsydwIOxTLGxkcFiDjuvG5Mj3pfCgj5x1YtPfni3svXCz4Popha7Ua3CFEIY/Er 5fHzYtCXN6bAi3zaQiWO022Z5SjeTSheVyKTMizBGv7rZCgPK5BbcRWocRUpohilpW4o vFPgIpCgV3+J3XNimXe6lZTSrK8nWX+HKvpn5rpvnxCwxh0yB95FbOH4vV6oIhVcJ142 2KeExHtkNrlDsr62BrlYM7gcg37wRdxDm1Bs92QDWzRB4127CKGOBlJxkWYlE0RsU2S1 ZaYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=3XT0k3U6qvD5udrQlogCgtcAX1RvDncQX9b7d8ibdRg=; b=KYnJ3WD6G2Wlv0fY1qugUgtj7bhb9U2BiiBIJzfR3xOkaOmf0u+PCANCfQCXwXHgRs vdMfFJpvljEt9bSL9Ba47zV4Mc5RUJTBw1ccKtsSPa1JdKGaXSVAeg4OWk7WXFvUUeMD tFCP3A7XHvo0i7mkMmPAlmzSYF40OCg8Fyrdz2Wfy9QdSjAQFbeQySTwHJv2MdCu5IIA KuIxylMXlIV1Phn1lMfK2H/9NbhnfMTeJFkqwkTOMiwZC3T03YSiHvu995/s9z9Kfu5/ WnQAaSNzTXg4z565P6NYKYrJZQOBHShPgRR57PHyIr4jdXsF3g7sRpjnMBrIRCCWpw3U 1kGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=fK4MD7O0; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:27 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:23 +0000 Message-Id: <20180305160415.16760-6-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 05/57] ARM: vGICv3: always use architected redist stride X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The redistributor-stride property in a GICv3 DT node is only there to cover broken platforms where this value deviates from the architected one. Since we emulate the GICv3 distributor even for Dom0, we don't need to copy the broken behaviour. All the special handling for Dom0s using GICv3 is just for using the hardware's memory map, which is unaffected by the redistributor stride - it can never be smaller than the architected two pages. Remove the redistributor-stride property from Dom0's DT node and also remove the code that tried to reuse the hardware value for Dom0's GICv3 emulation. Signed-off-by: Andre Przywara Acked-by: Julien Grall --- Changelog RFC ... v1: - Add Julien's ACK xen/arch/arm/gic-v3.c | 4 ---- xen/arch/arm/vgic-v3.c | 14 ++++++-------- 2 files changed, 6 insertions(+), 12 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index be1787b39a..02c85e4c0c 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1164,10 +1164,6 @@ static int gicv3_make_hwdom_dt_node(const struct domain *d, if ( res ) return res; - res = fdt_property_cell(fdt, "redistributor-stride", gicv3.rdist_stride); - if ( res ) - return res; - res = fdt_property_cell(fdt, "#redistributor-regions", gicv3.rdist_count); if ( res ) return res; diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index d5b34a7d0f..56cc38ffcc 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -1024,10 +1024,9 @@ static struct vcpu *get_vcpu_from_rdist(struct domain *d, paddr_t gpa, uint32_t *offset) { struct vcpu *v; - uint32_t stride = d->arch.vgic.rdist_stride; unsigned int vcpu_id; - vcpu_id = region->first_cpu + ((gpa - region->base) / stride); + vcpu_id = region->first_cpu + ((gpa - region->base) / GICV3_GICR_SIZE); if ( unlikely(vcpu_id >= d->max_vcpus) ) return NULL; @@ -1586,7 +1585,6 @@ static int vgic_v3_vcpu_init(struct vcpu *v) /* Convenient alias */ struct domain *d = v->domain; - uint32_t rdist_stride = d->arch.vgic.rdist_stride; /* * Find the region where the re-distributor lives. For this purpose, @@ -1602,11 +1600,11 @@ static int vgic_v3_vcpu_init(struct vcpu *v) /* Get the base address of the redistributor */ rdist_base = region->base; - rdist_base += (v->vcpu_id - region->first_cpu) * rdist_stride; + rdist_base += (v->vcpu_id - region->first_cpu) * GICV3_GICR_SIZE; /* Check if a valid region was found for the re-distributor */ if ( (rdist_base < region->base) || - ((rdist_base + rdist_stride) > (region->base + region->size)) ) + ((rdist_base + GICV3_GICR_SIZE) > (region->base + region->size)) ) { dprintk(XENLOG_ERR, "d%u: Unable to find a re-distributor for VCPU %u\n", @@ -1622,7 +1620,7 @@ static int vgic_v3_vcpu_init(struct vcpu *v) * VGIC_V3_RDIST_LAST flags. * Note that we are assuming max_vcpus will never change. */ - last_cpu = (region->size / rdist_stride) + region->first_cpu - 1; + last_cpu = (region->size / GICV3_GICR_SIZE) + region->first_cpu - 1; if ( v->vcpu_id == last_cpu || (v->vcpu_id == (d->max_vcpus - 1)) ) v->arch.vgic.flags |= VGIC_V3_RDIST_LAST; @@ -1693,7 +1691,7 @@ static int vgic_v3_domain_init(struct domain *d) /* Set the first CPU handled by this region */ d->arch.vgic.rdist_regions[i].first_cpu = first_cpu; - first_cpu += size / d->arch.vgic.rdist_stride; + first_cpu += size / GICV3_GICR_SIZE; } d->arch.vgic.intid_bits = vgic_v3_hw.intid_bits; @@ -1708,7 +1706,7 @@ static int vgic_v3_domain_init(struct domain *d) d->arch.vgic.rdist_stride = GUEST_GICV3_RDIST_STRIDE; /* The first redistributor should contain enough space for all CPUs */ - BUILD_BUG_ON((GUEST_GICV3_GICR0_SIZE / GUEST_GICV3_RDIST_STRIDE) < MAX_VIRT_CPUS); + BUILD_BUG_ON((GUEST_GICV3_GICR0_SIZE / GICV3_GICR_SIZE) < MAX_VIRT_CPUS); d->arch.vgic.rdist_regions[0].base = GUEST_GICV3_GICR0_BASE; d->arch.vgic.rdist_regions[0].size = GUEST_GICV3_GICR0_SIZE; d->arch.vgic.rdist_regions[0].first_cpu = 0; From patchwork Mon Mar 5 16:03:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130678 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853908lja; Mon, 5 Mar 2018 08:07:16 -0800 (PST) X-Google-Smtp-Source: AG47ELui9PluFA5HvLtimmI+6cyESMB6iE1SPfXrAHX+lGTlbWkKhUKS7rsfAubuBzOHekyE3VKA X-Received: by 10.107.29.3 with SMTP id d3mr18039187iod.45.1520266036102; Mon, 05 Mar 2018 08:07:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266036; cv=none; d=google.com; s=arc-20160816; b=Dllszn+BtY8EO8Cq4FdZNcoAGoU5j0LKJM252wy1sq6cLjB6isWr6W7xKIDNgIGugt /wJh4zaAWzn/+lTCZYjbaqfeMkmWngfmqZ7x1I0jIcdAoeUgaqJHqB+0yS27zDhYVtmk GnHZ6Vf9UJM0lDJ3BYXN1cL/TeuBHkJJb/ibMeVl83XO7/wmedcH45HQKRmdIVOKCXXG Kol0P0A2zR0+bRa9rI015nChzzvE2nk/rsNN8NNvcco3eLlvvvscjznerrwpzJVde+0Z kFsCpv8WY9dvfisz7KqagmTM3LXq62o0PpNF13kk+cFxmGCqsjn1XU7hmY16/dC8Ko/0 wA+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=Pbi2u4r5KH3FNJi1VP0zCzZvyYk1ntkNAwVnkLCnHN0=; b=SWVOHMBJrJvc1krCyAqwThazmrEPgvTYWM9RP2tZrOqGxj5vGZElCCR7BAjIuAnEzB 8SUIXoEgGoi1rXGv4ib8eQkIX5c1yQHxDMPxcp+3/1NMu50p0ia62IMNEHIWaAt2/JaK hIqEUJVsPXkDOniztY8g02JMC1ObBCBmXkBxxG0pFdrM9dFoV2mfM+f31fsvJgbTEpr2 g5ArCEYiPwxIQ/vKNDIGUoQVX5tBurFj0MSM6F9dL9IpN82ps+dOH1zWzQHj23RmXiRy OTyFY+Zm5jF4JPQDDr19HAkjR9sB/on8naoiYBqrwitntKnfjo/LJYHhtWdbBHxjIY/v 7L5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=W26Nk4Cs; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:28 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:24 +0000 Message-Id: <20180305160415.16760-7-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 06/57] ARM: vGICv3: remove rdist_stride from VGIC structure X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The last patch removed the usage of the hardware's redistributor-stride value from our (Dom0) GICv3 emulation. This means we no longer need to store this value in the VGIC data structure. Remove that variable and every code snippet that handled that, instead simply always use the architected value. Signed-off-by: Andre Przywara Acked-by: Julien Grall --- Changelog RFC ... v1: - Add Julien's ACK xen/arch/arm/gic-v3.c | 3 +-- xen/arch/arm/vgic-v3.c | 14 -------------- xen/include/asm-arm/domain.h | 1 - xen/include/asm-arm/vgic.h | 1 - xen/include/public/arch-arm.h | 1 - 5 files changed, 1 insertion(+), 19 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 02c85e4c0c..ea14ab4028 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1682,8 +1682,7 @@ static int __init gicv3_init(void) reg = readl_relaxed(GICD + GICD_TYPER); intid_bits = GICD_TYPE_ID_BITS(reg); - vgic_v3_setup_hw(dbase, gicv3.rdist_count, gicv3.rdist_regions, - gicv3.rdist_stride, intid_bits); + vgic_v3_setup_hw(dbase, gicv3.rdist_count, gicv3.rdist_regions, intid_bits); gicv3_init_v2(); spin_lock_init(&gicv3.lock); diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 56cc38ffcc..4b42739a52 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -58,21 +58,18 @@ static struct { /* Re-distributor regions */ unsigned int nr_rdist_regions; const struct rdist_region *regions; - uint32_t rdist_stride; /* Re-distributor stride */ unsigned int intid_bits; /* Number of interrupt ID bits */ } vgic_v3_hw; void vgic_v3_setup_hw(paddr_t dbase, unsigned int nr_rdist_regions, const struct rdist_region *regions, - uint32_t rdist_stride, unsigned int intid_bits) { vgic_v3_hw.enabled = true; vgic_v3_hw.dbase = dbase; vgic_v3_hw.nr_rdist_regions = nr_rdist_regions; vgic_v3_hw.regions = regions; - vgic_v3_hw.rdist_stride = rdist_stride; vgic_v3_hw.intid_bits = intid_bits; } @@ -1672,15 +1669,6 @@ static int vgic_v3_domain_init(struct domain *d) d->arch.vgic.dbase = vgic_v3_hw.dbase; - d->arch.vgic.rdist_stride = vgic_v3_hw.rdist_stride; - /* - * If the stride is not set, the default stride for GICv3 is 2 * 64K: - * - first 64k page for Control and Physical LPIs - * - second 64k page for Control and Generation of SGIs - */ - if ( !d->arch.vgic.rdist_stride ) - d->arch.vgic.rdist_stride = 2 * SZ_64K; - for ( i = 0; i < vgic_v3_hw.nr_rdist_regions; i++ ) { paddr_t size = vgic_v3_hw.regions[i].size; @@ -1703,8 +1691,6 @@ static int vgic_v3_domain_init(struct domain *d) /* A single Re-distributor region is mapped for the guest. */ BUILD_BUG_ON(GUEST_GICV3_RDIST_REGIONS != 1); - d->arch.vgic.rdist_stride = GUEST_GICV3_RDIST_STRIDE; - /* The first redistributor should contain enough space for all CPUs */ BUILD_BUG_ON((GUEST_GICV3_GICR0_SIZE / GICV3_GICR_SIZE) < MAX_VIRT_CPUS); d->arch.vgic.rdist_regions[0].base = GUEST_GICV3_GICR0_BASE; diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 4fe189b1c3..3eda7196ff 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -108,7 +108,6 @@ struct arch_domain unsigned int first_cpu; /* First CPU handled */ } *rdist_regions; int nr_regions; /* Number of rdist regions */ - uint32_t rdist_stride; /* Re-Distributor stride */ unsigned long int nr_lpis; uint64_t rdist_propbase; struct rb_root its_devices; /* Devices mapped to an ITS */ diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 6ea9f140a7..d61b54867b 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -261,7 +261,6 @@ struct rdist_region; void vgic_v3_setup_hw(paddr_t dbase, unsigned int nr_rdist_regions, const struct rdist_region *regions, - uint32_t rdist_stride, unsigned int intid_bits); #endif diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index 05fd11ca38..eb424e8286 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -401,7 +401,6 @@ typedef uint64_t xen_callback_t; #define GUEST_GICV3_GICD_BASE xen_mk_ullong(0x03001000) #define GUEST_GICV3_GICD_SIZE xen_mk_ullong(0x00010000) -#define GUEST_GICV3_RDIST_STRIDE xen_mk_ullong(0x00020000) #define GUEST_GICV3_RDIST_REGIONS 1 #define GUEST_GICV3_GICR0_BASE xen_mk_ullong(0x03020000) /* vCPU0..127 */ From patchwork Mon Mar 5 16:03:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130686 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2854163lja; Mon, 5 Mar 2018 08:07:26 -0800 (PST) X-Google-Smtp-Source: AG47ELuLQRxvz94r357Jiu6+Djvfptd9XvsCXy7MZMyTDOc4lgQkgitUS8/5pjZeG/VwBBLX/r7V X-Received: by 10.36.28.213 with SMTP id c204mr4615048itc.86.1520266046034; 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:29 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:25 +0000 Message-Id: <20180305160415.16760-8-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 07/57] ARM: VGIC: rename gic_inject() and gic_clear_lrs() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The two central functions to synchronise our emulated VGIC state with the GIC hardware (the LRs, really), are named somewhat confusingly. Rename them from gic_inject() to vgic_sync_to_lrs() and from gic_clear_lrs() to vgic_sync_from_lrs(), to make the code more readable. Signed-off-by: Andre Przywara Acked-by: Julien Grall --- Changelog RFC ... v1: - new patch xen/arch/arm/gic-vgic.c | 4 ++-- xen/arch/arm/traps.c | 4 ++-- xen/include/asm-arm/gic.h | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index d273863556..c0fe38fd37 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -247,7 +247,7 @@ static void gic_update_one_lr(struct vcpu *v, int i) } } -void gic_clear_lrs(struct vcpu *v) +void vgic_sync_from_lrs(struct vcpu *v) { int i = 0; unsigned long flags; @@ -377,7 +377,7 @@ out: return rc; } -void gic_inject(void) +void vgic_sync_to_lrs(void) { ASSERT(!local_irq_is_enabled()); diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 1cba7e584d..7411bff7a7 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -2024,7 +2024,7 @@ static void enter_hypervisor_head(struct cpu_user_regs *regs) if ( current->arch.hcr_el2 & HCR_VA ) current->arch.hcr_el2 = READ_SYSREG(HCR_EL2); - gic_clear_lrs(current); + vgic_sync_from_lrs(current); } } @@ -2234,7 +2234,7 @@ void leave_hypervisor_tail(void) { local_irq_disable(); if (!softirq_pending(smp_processor_id())) { - gic_inject(); + vgic_sync_to_lrs(); /* * If the SErrors handle option is "DIVERSE", we have to prevent diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 497f195bc1..e2ae4254ed 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -237,7 +237,7 @@ extern int gic_route_irq_to_guest(struct domain *, unsigned int virq, int gic_remove_irq_from_guest(struct domain *d, unsigned int virq, struct irq_desc *desc); -extern void gic_inject(void); +extern void vgic_sync_to_lrs(void); extern void gic_clear_pending_irqs(struct vcpu *v); extern int gic_events_need_delivery(void); @@ -295,7 +295,7 @@ extern unsigned int gic_number_lines(void); /* IRQ translation function for the device tree */ int gic_irq_xlate(const u32 *intspec, unsigned int intsize, unsigned int *out_hwirq, unsigned int *out_type); -void gic_clear_lrs(struct vcpu *v); +void vgic_sync_from_lrs(struct vcpu *v); struct gic_info { /* GIC version */ From patchwork Mon Mar 5 16:03:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130696 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2855427lja; Mon, 5 Mar 2018 08:08:31 -0800 (PST) X-Google-Smtp-Source: AG47ELvw3k3ZdKNkU3dHzJeECpZdCnC+WEG0cw/d5sr1ghwe7HiLDlDcG1cXk43djFK28q8CKWfI X-Received: by 10.107.186.135 with SMTP id k129mr17439663iof.200.1520266033132; Mon, 05 Mar 2018 08:07:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266033; cv=none; d=google.com; s=arc-20160816; b=HEUQEKsWtyWrXrOxuigyPAApzXVA5Q5XJ+PT61d8RnreLFkRg5m/b3X9gWBYoLdoXh E1mvp3XLJjICe4NnRqflWFXiX/3UNwd1Wa01CCctg8nIa6of1zH7UmNPOK6yyq/0F6Qb psJAgYAWJ9jwTI2yw9r4wrqKkzV5OU5dFwMvniwYywasVr7nZvU7/hVl6+gT60P1CXE4 EAV3rH+iJ0tvskLuimdOyU4cuku65F7kGanLwv/l6D9y9fQntg//mvk5D//uYbcCBlkc DOuOW15do5GoO+Ony4D8BKZAtQF0lTg7Eff4TajQg71Pbpa3PUPsSYK7vsP4RmNEBVVm seog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=TEssJ9obaGbGP8NMXfhz/0WPjm4KDAVNVO8imM7dwOY=; b=PSOU7tjkSecSOmGexAwBp7IfVgIvp/S4MXJ7CvaDrhha4RzP0QqVXMOMn/FjTB4GZ/ c8IwOWE+W9481025SAXovjLo3rjOQ7KYHiTwf74Lf5+zNtOdzYIbNePP4JJcBwpzk6rq wFlf9Cua3ppQblVuUfX9z/MGT5+R6tey5rPNz2bQANV7rIVZ9RZUyvre7qVRvpLCxmYZ /JGdbYWgwD7WeMGqbrvoi87hDrXGAS5IlQSld0ka++3A5jypr2QguJst10M9w0BZQLkE VC+FOiSZ9laLaij1a4cn6pgcGLZyw9PdqRAEhLDbeqclFSuEw6ucH52klwg2yh7aL2LB VJlQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=RKpYKYU0; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:30 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:26 +0000 Message-Id: <20180305160415.16760-9-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 08/57] ARM: VGIC: Move gic_remove_from_lr_pending() prototype X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The prototype for gic_remove_from_lr_pending() is the last function in gic.h which references a VGIC data structure. Move it over to vgic.h, so that we can remove the inclusion of vgic.h from gic.h. We add it to asm/domain.h instead, where it is actually needed. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- Changelog RFC ... v1: - Add Julien's Reviewed-by: xen/include/asm-arm/domain.h | 1 + xen/include/asm-arm/gic.h | 2 -- xen/include/asm-arm/vgic.h | 1 + 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 3eda7196ff..1dd9683d25 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index e2ae4254ed..3b2d0217a6 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -156,7 +156,6 @@ #ifndef __ASSEMBLY__ #include #include -#include #define DT_COMPAT_GIC_CORTEX_A15 "arm,cortex-a15-gic" @@ -245,7 +244,6 @@ extern void init_maintenance_interrupt(void); extern void gic_raise_guest_irq(struct vcpu *v, unsigned int irq, unsigned int priority); extern void gic_raise_inflight_irq(struct vcpu *v, unsigned int virtual_irq); -extern void gic_remove_from_lr_pending(struct vcpu *v, struct pending_irq *p); /* Accept an interrupt from the GIC and dispatch its handler */ extern void gic_interrupt(struct cpu_user_regs *regs, int is_fiq); diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index d61b54867b..d03298e12c 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -205,6 +205,7 @@ extern struct vcpu *vgic_get_target_vcpu(struct vcpu *v, unsigned int virq); extern void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int virq); extern void vgic_vcpu_inject_spi(struct domain *d, unsigned int virq); extern void vgic_remove_irq_from_queues(struct vcpu *v, struct pending_irq *p); +extern void gic_remove_from_lr_pending(struct vcpu *v, struct pending_irq *p); extern void vgic_clear_pending_irqs(struct vcpu *v); extern void vgic_init_pending_irq(struct pending_irq *p, unsigned int virq); extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq); From patchwork Mon Mar 5 16:03:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130700 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2855775lja; Mon, 5 Mar 2018 08:08:48 -0800 (PST) X-Google-Smtp-Source: AG47ELtu84yrDRXFEVoNExhCxD+2VO//wrkTWcWyg/xew/MrJ4zGe4POmXTnxngJhrS4cM3mfZ34 X-Received: by 10.36.233.68 with SMTP id f65mr14154795ith.149.1520266026297; Mon, 05 Mar 2018 08:07:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266026; cv=none; d=google.com; s=arc-20160816; b=DX2Et7lOqWdEwm/0CmZgSxjI9tQi0xJsQUfJpqcRNVeeEYCyDWZ24brug/VogHYExR eu+CE0+SCdTDau7SOk4dottF1SAxX4XQVPj9JhYSTQHrhEL0/OHUmYYZ8jq/zLD7bRiH dnhYkryo+T/Jomgs4A17yA0OEHy9AJ4WvbHNjFhIlULdWwsxAYTJcuvUOyikDSDX2Kq0 uhyAGDBOFVtvTiKERsiN5DCx8g3yfLrk+7n5TTDjn+CFw8EfC4c0fBuf7dM13p9HAIzu tYZlyhKMuSIGoALHryHnNniB56HFkFVwEp9Q6YfwyWmxxhI6KC4yLUhnGTaLi0yO9NKZ 2QpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=Xqi7Mb0rNqo41GYfFS7Z6xY5W4MV07O/DXA3JL5Kues=; b=tt/2icPACJKBX1Bnj/QpFPwG5ffTsz0sf61K0+jniDRSOeehxAR597v3MtFmgzzjru YI79zRbXRe6aCRWGKgqx2aZyF9BcjNfeJMbYnsX7qfXRs99giF19aTV+dU/eBvRWOPbF E1CRD0/nb8e9XugFs25dKWx1jAFzATZk73aTfveanKgxot2nlCntYjzFjfTDXLCFlXqi EEWtcfJTQEVhmcP12lMKMJ9SFgbiSESl61qAWZyBoC28AgvUqfwN5oto6DvFU3i33M0p 1LhdLWAjWdC4aYoFAp2g3Z+q7x4INl4IYr4tNzCWV6NNb0d6CVASZlzcwnkH1ZNy29e2 kXrw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=c7o8HEdU; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:31 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:27 +0000 Message-Id: <20180305160415.16760-10-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 09/57] ARM: VGIC: Move domain_max_vcpus() to be VGIC specific X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" domain_max_vcpus(), which is used by generic Xen code, returns the maximum number of VCPUs for a domain, which on ARM is mostly limited by the VGIC model emulated (a (v)GICv2 can only handle 8 CPUs). Our current implementation lives in arch/arm/domain.c, but reaches into VGIC internal data structures. Move this function into vgic.c, to keep this VGIC internal. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - dump previous approach, move function to VGIC specific file instead xen/arch/arm/domain.c | 14 -------------- xen/arch/arm/vgic.c | 14 ++++++++++++++ 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index a010443bfd..8546443bad 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -968,20 +968,6 @@ void vcpu_block_unless_event_pending(struct vcpu *v) vcpu_unblock(current); } -unsigned int domain_max_vcpus(const struct domain *d) -{ - /* - * Since evtchn_init would call domain_max_vcpus for poll_mask - * allocation when the vgic_ops haven't been initialised yet, - * we return MAX_VIRT_CPUS if d->arch.vgic.handler is null. - */ - if ( !d->arch.vgic.handler ) - return MAX_VIRT_CPUS; - else - return min_t(unsigned int, MAX_VIRT_CPUS, - d->arch.vgic.handler->max_vcpus); -} - /* * Local variables: * mode: C diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index 34269bcf27..c3fdcebbde 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -665,6 +665,20 @@ void vgic_free_virq(struct domain *d, unsigned int virq) clear_bit(virq, d->arch.vgic.allocated_irqs); } +unsigned int domain_max_vcpus(const struct domain *d) +{ + /* + * Since evtchn_init would call domain_max_vcpus for poll_mask + * allocation when the vgic_ops haven't been initialised yet, + * we return MAX_VIRT_CPUS if d->arch.vgic.handler is null. + */ + if ( !d->arch.vgic.handler ) + return MAX_VIRT_CPUS; + else + return min_t(unsigned int, MAX_VIRT_CPUS, + d->arch.vgic.handler->max_vcpus); +} + /* * Local variables: * mode: C From patchwork Mon Mar 5 16:03:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130685 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2854151lja; Mon, 5 Mar 2018 08:07:25 -0800 (PST) X-Google-Smtp-Source: AG47ELvPPukPvQIrGqHMjFAg0Hoy0lfw4okAeIe7Ng4ozetRjJ3IziHmxaFOURrvjbsh8mCibD1O X-Received: by 10.36.219.214 with SMTP id c205mr14757301itg.63.1520266045321; Mon, 05 Mar 2018 08:07:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266045; cv=none; d=google.com; s=arc-20160816; b=gwEI/2Ad3O69GsN43UhvfOL0jm4WUa2BHYG+C3gNAWkp5akTd35q4DPDQjev7p02ju MxRLYyPmRm+kYwjLi2vxIUkHRqQYHSN4pb0X0FJnCuArEZVnwOan4KYCN8fm4d8H3ADk ReLfNIVhA2ja+UNkB06MmQ+EVV5AUR53kB7u/UW9ahDZxnbbegdIH1C03vakavkW/x0N jloZTu983VkZdfmN/F8hQRPLOeOSerc6SzGCUsc79t+F4GF6UGT8ZZNbcAC3lgXsJer6 KOUe+hMTBJkWSSzNUo7ygX9CrVo8JmDUqlFegVKHAoD3xffK/ulajNa/5D10IA2NKIFj Ipeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=dKI3uumutntbsEc+0+QVRJ8t2WFm5LKSL1yppbjhynQ=; b=uULnyUvhSsMIvXxPczVVPV9uxKptxBO+17yZTAcx0Uc6wSOSevSngPGjnqoyMqDs/m 0VTUwq/N4VNv7PcaZWbOHRj5dsymgsd/HzTGx1gJvXhpja3vP2rksI8OWdRZvOnirntT 9RzUNqqgVGkZob4T83uGooo30m2pyPxUCXSWVtb6liwN5liplCon3+nnoDLxaSpTP/Ab M8Asj5xNeVtPHtnpUqjWGKqocF1CQuasvH1VLDER6sqGkDOcDoP3d8+fwdkFCPygK6Zn fHr3qjqv/rKlFxVwZ0iEdVhYXdLQ8ZZJykHNQv7QRBb1GxI2G0v42KzD8PJ1QaZwlrbd /gUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Ed/CFg+5; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id d124si5926349itg.65.2018.03.05.08.07.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Mar 2018 08:07:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Ed/CFg+5; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1essbL-0007Dj-Fb; Mon, 05 Mar 2018 16:04:35 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1essbK-0007CL-Bp for xen-devel@lists.xenproject.org; Mon, 05 Mar 2018 16:04:34 +0000 X-Inumbo-ID: bd991422-208e-11e8-ba59-bc764e045a96 Received: from mail-wm0-x243.google.com (unknown [2a00:1450:400c:c09::243]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id bd991422-208e-11e8-ba59-bc764e045a96; Mon, 05 Mar 2018 17:03:28 +0100 (CET) Received: by mail-wm0-x243.google.com with SMTP id x7so16534422wmc.0 for ; Mon, 05 Mar 2018 08:04:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WuvPOQVi6UpGBIIgDuv7ml+wfAOHAGc9R62uL7hIf+w=; b=Ed/CFg+5/VISQG2EU4WqUZcfwBy9YwR+6l/Q+6wXmD6pNNoMzaImy6wd2n7gsWPqFd yHV8UkPUPAIig48Avvx4JThnOIz6poDTBAOYxbedmz0guPVEpyLoNfl73NwVsbPlzm0n amqVCWhpXisREdzBkszbjifoLifqs5MyrBwos= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WuvPOQVi6UpGBIIgDuv7ml+wfAOHAGc9R62uL7hIf+w=; b=RV7f81UwoIDcevWanjGEwAruV41WC2Yl5CxABXE0h2IOL1UZlRei1zuLam+oA9jgYp E/a9j0XW2Ijuk3NZsaJKvQIY57VYIUWZv3cx2pU+CIGw7QoSuD8siCysMrzYUJ6KPXjb 5Gvtilz6aPZia0nY7CVHk/pLM81565LRFPHXSb6V8YT/lppd2sjpjCFti+0Rw7UQNQ+A 4DYkrdjGE/4qBt3oymE2jAKydBMkRjvkUuQ40WEDl+m/tWm4x0ZUm5GhoSysKHYPl0Y9 F2eKmszS2J5BZ2pBCJA6mMVr/ZHLTMGXHw1Cr85BxQmkdr9qLFjc6nSNxobKJvSfuuS7 7/yA== X-Gm-Message-State: AElRT7HiA3I8inW4jxVSQMXGScZpaTcY21/1rfZDv6bGOQsdfZCcDwvJ L7zXwp9eGRrpdNz8eHpeCxLH7g== X-Received: by 10.28.16.138 with SMTP id 132mr8975688wmq.28.1520265872622; Mon, 05 Mar 2018 08:04:32 -0800 (PST) Received: from e104803-lin.lan (mail.andrep.de. [217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:32 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:28 +0000 Message-Id: <20180305160415.16760-11-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 10/57] ARM: VGIC: rename gic_event_needs_delivery() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" gic_event_needs_delivery() is not named very intuitively, especially the gic_ prefix is somewhat misleading. Rename it to vgic_pending_irq(), which makes it clear that this relates to the virtual GIC and is about interrupts. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - new patch xen/arch/arm/gic-vgic.c | 2 +- xen/include/asm-arm/event.h | 2 +- xen/include/asm-arm/gic.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index c0fe38fd37..60c6c463e9 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -339,7 +339,7 @@ void gic_clear_pending_irqs(struct vcpu *v) gic_remove_from_lr_pending(v, p); } -int gic_events_need_delivery(void) +int vgic_pending_irq(void) { struct vcpu *v = current; struct pending_irq *p; diff --git a/xen/include/asm-arm/event.h b/xen/include/asm-arm/event.h index e8c2a6cb44..c4c79fa87d 100644 --- a/xen/include/asm-arm/event.h +++ b/xen/include/asm-arm/event.h @@ -24,7 +24,7 @@ static inline int local_events_need_delivery_nomask(void) * interrupts disabled so this shouldn't be a problem in the general * case. */ - if ( gic_events_need_delivery() ) + if ( vgic_pending_irq() ) return 1; if ( !vcpu_info(current, evtchn_upcall_pending) ) diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 3b2d0217a6..a23c307c3a 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -238,7 +238,7 @@ int gic_remove_irq_from_guest(struct domain *d, unsigned int virq, extern void vgic_sync_to_lrs(void); extern void gic_clear_pending_irqs(struct vcpu *v); -extern int gic_events_need_delivery(void); +extern int vgic_pending_irq(void); extern void init_maintenance_interrupt(void); extern void gic_raise_guest_irq(struct vcpu *v, unsigned int irq, From patchwork Mon Mar 5 16:03:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130682 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2854007lja; Mon, 5 Mar 2018 08:07:19 -0800 (PST) X-Google-Smtp-Source: AG47ELuEKati7CNy3hDDvwLZmyKBVU031MdP8gDxpMGDXbCL81D1r4N1bG8rQow4v2fizn5VPATA X-Received: by 10.36.140.3 with SMTP id j3mr15119836itd.66.1520266039528; Mon, 05 Mar 2018 08:07:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266039; cv=none; d=google.com; s=arc-20160816; b=b/bhdNI304Oazxg9vwcxiJOtOHcP7tFCFacFIgdcLtHEwT/KbLU6yz9SAWo8KwUKTh ltgltX5ziZdxuym76x/aih2XwyfHotkpBwCEYGOLgR5Th56ihoISokSxSs2QJYwJfT71 1yw7bwiVTI8+uDX+dVa4jM0YExesVjS9wxfJfmRUiy1Ju6WCjMIACuOiREQQOuS0zcY3 vw6J6btrXkQkd6Gg98m+zbgGutbDw2HJn+6klX2vMxUHE2ONlT6mNzil5ap0bXpLR7Rc 6W2jm73pfh778cL/Ah1oFTz1Vf5QG4MWdsEZL/TKhUQQDQ01nu7QV2FTYmjN5u7HGDci ZSeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=gdoW6i6taxL1eR70+7ynHWxhT2w+XZZS4Xxhjik5WqE=; b=UCXd0nabKqq92NdiDONRoQ9j/lwGVsGKrgoLCzmyxQKEaUC+DpXS9R/hOGAGzwduJz pt8W8PJevNe7HsJsLwRtRPOZxZAg9swWk0JMHIv0vQDWoQlon5uXpRfHkaVdhvmH22g5 mRz4X0u9DOUJW7iwUXCBgCOkAorDjgW+eioI7wh1yfEY+FNC23jXgmaS2AWXAS5aHCG9 nZBBLSH/7IthSpQeYMDw86MusfzAfAB/hGfni/H/GHSeTZAEaRXnGyl0wdu+43QOmIT9 Kaeom9pc+xpot3UojLYjX4a3A719lArmoJBeKXRV0HYah1i6acTfX6Wap1cqOnweaSCm gJkg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=PCCqyFF7; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:33 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:29 +0000 Message-Id: <20180305160415.16760-12-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 11/57] ARM: VGIC: change to level-IRQ compatible IRQ injection interface X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment vgic_vcpu_inject_irq() is the interface for Xen internal code and virtual devices to inject IRQs into a guest. This interface has two shortcomings: 1) It requires a VCPU pointer, which we may not know (and don't need!) for shared interrupts. A second function (vgic_vcpu_inject_spi()), was there to work around this issue. 2) This interface only really supports edge triggered IRQs, which is what the Xen VGIC emulates only anyway. However this needs to and will change, so we need to add the desired level (high or low) to the interface. This replaces the existing injection call (taking a VCPU and an IRQ parameter) with a new one, taking domain, VCPU, IRQ and level parameters. The VCPU can be NULL in case we don't know and don't care. We change all call sites to use this new interface. This still doesn't give us the missing level IRQ handling, but at least prepares the callers to do the right thing later automatically. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - no change xen/arch/arm/domain.c | 4 ++-- xen/arch/arm/gic-v3-lpi.c | 2 +- xen/arch/arm/irq.c | 2 +- xen/arch/arm/time.c | 2 +- xen/arch/arm/vgic.c | 43 +++++++++++++++++++++++++------------------ xen/arch/arm/vpl011.c | 2 +- xen/arch/arm/vtimer.c | 4 ++-- xen/include/asm-arm/vgic.h | 4 ++-- 8 files changed, 35 insertions(+), 28 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 8546443bad..a7bba3ad44 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -952,14 +952,14 @@ void vcpu_mark_events_pending(struct vcpu *v) if ( already_pending ) return; - vgic_vcpu_inject_irq(v, v->domain->arch.evtchn_irq); + vgic_inject_irq(v->domain, v, v->domain->arch.evtchn_irq, true); } /* The ARM spec declares that even if local irqs are masked in * the CPSR register, an irq should wake up a cpu from WFI anyway. * For this reason we need to check for irqs that need delivery, * ignoring the CPSR register, *after* calling SCHEDOP_block to - * avoid races with vgic_vcpu_inject_irq. + * avoid races with vgic_inject_irq. */ void vcpu_block_unless_event_pending(struct vcpu *v) { diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c index 84582157b8..efd5cd62fb 100644 --- a/xen/arch/arm/gic-v3-lpi.c +++ b/xen/arch/arm/gic-v3-lpi.c @@ -153,7 +153,7 @@ void vgic_vcpu_inject_lpi(struct domain *d, unsigned int virq) if ( vcpu_id >= d->max_vcpus ) return; - vgic_vcpu_inject_irq(d->vcpu[vcpu_id], virq); + vgic_inject_irq(d, d->vcpu[vcpu_id], virq, true); } /* diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index 29af10e82c..aa4e832cae 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -225,7 +225,7 @@ void do_IRQ(struct cpu_user_regs *regs, unsigned int irq, int is_fiq) * The irq cannot be a PPI, we only support delivery of SPIs to * guests. */ - vgic_vcpu_inject_spi(info->d, info->virq); + vgic_inject_irq(info->d, NULL, info->virq, true); goto out_no_end; } diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c index 36f640f0c1..c11fcfeadd 100644 --- a/xen/arch/arm/time.c +++ b/xen/arch/arm/time.c @@ -260,7 +260,7 @@ static void vtimer_interrupt(int irq, void *dev_id, struct cpu_user_regs *regs) current->arch.virt_timer.ctl = READ_SYSREG32(CNTV_CTL_EL0); WRITE_SYSREG32(current->arch.virt_timer.ctl | CNTx_CTL_MASK, CNTV_CTL_EL0); - vgic_vcpu_inject_irq(current, current->arch.virt_timer.irq); + vgic_inject_irq(current->domain, current, current->arch.virt_timer.irq, true); } /* diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index c3fdcebbde..3c77d5fef6 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -291,7 +291,7 @@ bool vgic_migrate_irq(struct vcpu *old, struct vcpu *new, unsigned int irq) vgic_remove_irq_from_queues(old, p); irq_set_affinity(p->desc, cpumask_of(new->processor)); spin_unlock_irqrestore(&old->arch.vgic.lock, flags); - vgic_vcpu_inject_irq(new, irq); + vgic_inject_irq(new->domain, new, irq, true); return true; } /* if the IRQ is in a GICH_LR register, set GIC_IRQ_GUEST_MIGRATING @@ -450,7 +450,7 @@ bool vgic_to_sgi(struct vcpu *v, register_t sgir, enum gic_sgi_mode irqmode, sgir, target->list); continue; } - vgic_vcpu_inject_irq(d->vcpu[vcpuid], virq); + vgic_inject_irq(d, d->vcpu[vcpuid], virq, true); } break; case SGI_TARGET_OTHERS: @@ -459,12 +459,12 @@ bool vgic_to_sgi(struct vcpu *v, register_t sgir, enum gic_sgi_mode irqmode, { if ( i != current->vcpu_id && d->vcpu[i] != NULL && is_vcpu_online(d->vcpu[i]) ) - vgic_vcpu_inject_irq(d->vcpu[i], virq); + vgic_inject_irq(d, d->vcpu[i], virq, true); } break; case SGI_TARGET_SELF: perfc_incr(vgic_sgi_self); - vgic_vcpu_inject_irq(d->vcpu[current->vcpu_id], virq); + vgic_inject_irq(d, current, virq, true); break; default: gprintk(XENLOG_WARNING, @@ -524,13 +524,29 @@ void vgic_remove_irq_from_queues(struct vcpu *v, struct pending_irq *p) gic_remove_from_lr_pending(v, p); } -void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int virq) +int vgic_inject_irq(struct domain *d, struct vcpu *v, unsigned int virq, + bool level) { uint8_t priority; struct pending_irq *iter, *n; unsigned long flags; bool running; + /* + * For edge triggered interrupts we always ignore a "falling edge". + * For level triggered interrupts we shouldn't, but do anyways. + */ + if ( !level ) + return 0; + + if ( !v ) + { + /* The IRQ needs to be an SPI if no vCPU is specified. */ + ASSERT(virq >= 32 && virq <= vgic_num_irqs(d)); + + v = vgic_get_target_vcpu(d->vcpu[0], virq); + }; + spin_lock_irqsave(&v->arch.vgic.lock, flags); n = irq_to_pending(v, virq); @@ -538,14 +554,14 @@ void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int virq) if ( unlikely(!n) ) { spin_unlock_irqrestore(&v->arch.vgic.lock, flags); - return; + return 0; } /* vcpu offline */ if ( test_bit(_VPF_down, &v->pause_flags) ) { spin_unlock_irqrestore(&v->arch.vgic.lock, flags); - return; + return 0; } set_bit(GIC_IRQ_GUEST_QUEUED, &n->status); @@ -582,22 +598,13 @@ out: perfc_incr(vgic_cross_cpu_intr_inject); smp_send_event_check_mask(cpumask_of(v->processor)); } -} - -void vgic_vcpu_inject_spi(struct domain *d, unsigned int virq) -{ - struct vcpu *v; - /* the IRQ needs to be an SPI */ - ASSERT(virq >= 32 && virq <= vgic_num_irqs(d)); - - v = vgic_get_target_vcpu(d->vcpu[0], virq); - vgic_vcpu_inject_irq(v, virq); + return 0; } void arch_evtchn_inject(struct vcpu *v) { - vgic_vcpu_inject_irq(v, v->domain->arch.evtchn_irq); + vgic_inject_irq(v->domain, v, v->domain->arch.evtchn_irq, true); } bool vgic_evtchn_irq_pending(struct vcpu *v) diff --git a/xen/arch/arm/vpl011.c b/xen/arch/arm/vpl011.c index 7788c2fc32..5dcf4bec18 100644 --- a/xen/arch/arm/vpl011.c +++ b/xen/arch/arm/vpl011.c @@ -68,7 +68,7 @@ static void vpl011_update_interrupt_status(struct domain *d) * status bit has been set since the last time. */ if ( uartmis & ~vpl011->shadow_uartmis ) - vgic_vcpu_inject_spi(d, GUEST_VPL011_SPI); + vgic_inject_irq(d, NULL, GUEST_VPL011_SPI, true); vpl011->shadow_uartmis = uartmis; } diff --git a/xen/arch/arm/vtimer.c b/xen/arch/arm/vtimer.c index f52a723a5f..8164f6c7f1 100644 --- a/xen/arch/arm/vtimer.c +++ b/xen/arch/arm/vtimer.c @@ -46,7 +46,7 @@ static void phys_timer_expired(void *data) if ( !(t->ctl & CNTx_CTL_MASK) ) { perfc_incr(vtimer_phys_inject); - vgic_vcpu_inject_irq(t->v, t->irq); + vgic_inject_irq(t->v->domain, t->v, t->irq, true); } else perfc_incr(vtimer_phys_masked); @@ -56,7 +56,7 @@ static void virt_timer_expired(void *data) { struct vtimer *t = data; t->ctl |= CNTx_CTL_MASK; - vgic_vcpu_inject_irq(t->v, t->irq); + vgic_inject_irq(t->v->domain, t->v, t->irq, true); perfc_incr(vtimer_virt_inject); } diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index d03298e12c..b75fdeb068 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -202,8 +202,8 @@ extern int domain_vgic_init(struct domain *d, unsigned int nr_spis); extern void domain_vgic_free(struct domain *d); extern int vcpu_vgic_init(struct vcpu *v); extern struct vcpu *vgic_get_target_vcpu(struct vcpu *v, unsigned int virq); -extern void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int virq); -extern void vgic_vcpu_inject_spi(struct domain *d, unsigned int virq); +extern int vgic_inject_irq(struct domain *d, struct vcpu *v, unsigned int virq, + bool level); extern void vgic_remove_irq_from_queues(struct vcpu *v, struct pending_irq *p); extern void gic_remove_from_lr_pending(struct vcpu *v, struct pending_irq *p); extern void vgic_clear_pending_irqs(struct vcpu *v); From patchwork Mon Mar 5 16:03:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130697 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2855454lja; Mon, 5 Mar 2018 08:08:32 -0800 (PST) X-Google-Smtp-Source: AG47ELsS4F2y3cZPnA7oiJeN88WIHhLM6vzNgsxq2An1NLwxkoYCxQPL/yjm9wA7aFTcz+CCUUjo X-Received: by 10.36.93.206 with SMTP id w197mr15101976ita.144.1520266028689; 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:34 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:30 +0000 Message-Id: <20180305160415.16760-13-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 12/57] ARM: VGIC: carve out struct vgic_cpu and struct vgic_dist X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Currently we describe the VGIC specific fields in a structure *embedded* in struct arch_domain and struct arch_vcpu. These members there are however related to the current VGIC implementation, and will be substantially different in the future. To allow coexistence of two implementations, move the definition of these embedded structures into vgic.h, and just use the opaque type in the arch specific structures. This allows easy switching between different implementations later. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- Changelog RFC ... v1: - No changes xen/include/asm-arm/domain.h | 85 +----------------------------------------- xen/include/asm-arm/vgic.h | 88 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 90 insertions(+), 83 deletions(-) diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 1dd9683d25..bb7a46c1d0 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -74,57 +74,7 @@ struct arch_domain uint64_t offset; } virt_timer_base; - struct { - /* Version of the vGIC */ - enum gic_version version; - /* GIC HW version specific vGIC driver handler */ - const struct vgic_ops *handler; - /* - * Covers access to other members of this struct _except_ for - * shared_irqs where each member contains its own locking. - * - * If both class of lock is required then this lock must be - * taken first. If multiple rank locks are required (including - * the per-vcpu private_irqs rank) then they must be taken in - * rank order. - */ - spinlock_t lock; - uint32_t ctlr; - int nr_spis; /* Number of SPIs */ - unsigned long *allocated_irqs; /* bitmap of IRQs allocated */ - struct vgic_irq_rank *shared_irqs; - /* - * SPIs are domain global, SGIs and PPIs are per-VCPU and stored in - * struct arch_vcpu. - */ - struct pending_irq *pending_irqs; - /* Base address for guest GIC */ - paddr_t dbase; /* Distributor base address */ -#ifdef CONFIG_HAS_GICV3 - /* GIC V3 addressing */ - /* List of contiguous occupied by the redistributors */ - struct vgic_rdist_region { - paddr_t base; /* Base address */ - paddr_t size; /* Size */ - unsigned int first_cpu; /* First CPU handled */ - } *rdist_regions; - int nr_regions; /* Number of rdist regions */ - unsigned long int nr_lpis; - uint64_t rdist_propbase; - struct rb_root its_devices; /* Devices mapped to an ITS */ - spinlock_t its_devices_lock; /* Protects the its_devices tree */ - struct radix_tree_root pend_lpi_tree; /* Stores struct pending_irq's */ - rwlock_t pend_lpi_tree_lock; /* Protects the pend_lpi_tree */ - struct list_head vits_list; /* List of virtual ITSes */ - unsigned int intid_bits; - /* - * TODO: if there are more bool's being added below, consider - * a flags variable instead. - */ - bool rdists_enabled; /* Is any redistributor enabled? */ - bool has_its; -#endif - } vgic; + struct vgic_dist vgic; struct vuart { #define VUART_BUF_SIZE 128 @@ -247,38 +197,7 @@ struct arch_vcpu union gic_state_data gic; uint64_t lr_mask; - struct { - /* - * SGIs and PPIs are per-VCPU, SPIs are domain global and in - * struct arch_domain. - */ - struct pending_irq pending_irqs[32]; - struct vgic_irq_rank *private_irqs; - - /* This list is ordered by IRQ priority and it is used to keep - * track of the IRQs that the VGIC injected into the guest. - * Depending on the availability of LR registers, the IRQs might - * actually be in an LR, and therefore injected into the guest, - * or queued in gic.lr_pending. - * As soon as an IRQ is EOI'd by the guest and removed from the - * corresponding LR it is also removed from this list. */ - struct list_head inflight_irqs; - /* lr_pending is used to queue IRQs (struct pending_irq) that the - * vgic tried to inject in the guest (calling gic_set_guest_irq) but - * no LRs were available at the time. - * As soon as an LR is freed we remove the first IRQ from this - * list and write it to the LR register. - * lr_pending is a subset of vgic.inflight_irqs. */ - struct list_head lr_pending; - spinlock_t lock; - - /* GICv3: redistributor base and flags for this vCPU */ - paddr_t rdist_base; - uint64_t rdist_pendbase; -#define VGIC_V3_RDIST_LAST (1 << 0) /* last vCPU of the rdist */ -#define VGIC_V3_LPIS_ENABLED (1 << 1) - uint8_t flags; - } vgic; + struct vgic_cpu vgic; /* Timer registers */ uint32_t cntkctl; diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index b75fdeb068..4e1c37f091 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -19,6 +19,9 @@ #define __ASM_ARM_VGIC_H__ #include +#include +#include +#include #include #include @@ -123,6 +126,91 @@ struct vgic_irq_rank { uint8_t vcpu[32]; }; +struct vgic_dist { + /* Version of the vGIC */ + enum gic_version version; + /* GIC HW version specific vGIC driver handler */ + const struct vgic_ops *handler; + /* + * Covers access to other members of this struct _except_ for + * shared_irqs where each member contains its own locking. + * + * If both class of lock is required then this lock must be + * taken first. If multiple rank locks are required (including + * the per-vcpu private_irqs rank) then they must be taken in + * rank order. + */ + spinlock_t lock; + uint32_t ctlr; + int nr_spis; /* Number of SPIs */ + unsigned long *allocated_irqs; /* bitmap of IRQs allocated */ + struct vgic_irq_rank *shared_irqs; + /* + * SPIs are domain global, SGIs and PPIs are per-VCPU and stored in + * struct arch_vcpu. + */ + struct pending_irq *pending_irqs; + /* Base address for guest GIC */ + paddr_t dbase; /* Distributor base address */ +#ifdef CONFIG_HAS_GICV3 + /* GIC V3 addressing */ + /* List of contiguous occupied by the redistributors */ + struct vgic_rdist_region { + paddr_t base; /* Base address */ + paddr_t size; /* Size */ + unsigned int first_cpu; /* First CPU handled */ + } *rdist_regions; + int nr_regions; /* Number of rdist regions */ + unsigned long int nr_lpis; + uint64_t rdist_propbase; + struct rb_root its_devices; /* Devices mapped to an ITS */ + spinlock_t its_devices_lock; /* Protects the its_devices tree */ + struct radix_tree_root pend_lpi_tree; /* Stores struct pending_irq's */ + rwlock_t pend_lpi_tree_lock; /* Protects the pend_lpi_tree */ + struct list_head vits_list; /* List of virtual ITSes */ + unsigned int intid_bits; + /* + * TODO: if there are more bool's being added below, consider + * a flags variable instead. + */ + bool rdists_enabled; /* Is any redistributor enabled? */ + bool has_its; +#endif +}; + +struct vgic_cpu { + /* + * SGIs and PPIs are per-VCPU, SPIs are domain global and in + * struct arch_domain. + */ + struct pending_irq pending_irqs[32]; + struct vgic_irq_rank *private_irqs; + + /* This list is ordered by IRQ priority and it is used to keep + * track of the IRQs that the VGIC injected into the guest. + * Depending on the availability of LR registers, the IRQs might + * actually be in an LR, and therefore injected into the guest, + * or queued in gic.lr_pending. + * As soon as an IRQ is EOI'd by the guest and removed from the + * corresponding LR it is also removed from this list. */ + struct list_head inflight_irqs; + /* lr_pending is used to queue IRQs (struct pending_irq) that the + * vgic tried to inject in the guest (calling gic_set_guest_irq) but + * no LRs were available at the time. + * As soon as an LR is freed we remove the first IRQ from this + * list and write it to the LR register. + * lr_pending is a subset of vgic.inflight_irqs. */ + struct list_head lr_pending; + spinlock_t lock; + + /* GICv3: redistributor base and flags for this vCPU */ + paddr_t rdist_base; + uint64_t rdist_pendbase; +#define VGIC_V3_RDIST_LAST (1 << 0) /* last vCPU of the rdist */ +#define VGIC_V3_LPIS_ENABLED (1 << 1) + uint8_t flags; +}; + struct sgi_target { uint8_t aff1; uint16_t list; From patchwork Mon Mar 5 16:03:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130647 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853285lja; Mon, 5 Mar 2018 08:06:47 -0800 (PST) X-Google-Smtp-Source: AG47ELsFe7Fb54Q0QJNzKzwSKkJtcLuIz0XmtzH3UoXNZSs8b5iWPKYNhudUvTlzWJVuqVryf2TF X-Received: by 10.107.140.86 with SMTP id o83mr17477804iod.127.1520266007373; Mon, 05 Mar 2018 08:06:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266007; cv=none; d=google.com; s=arc-20160816; b=Ynd3J6DlEYS3f7F/oJ8GHFnwQCO5bZ7z2/RMX+LwSkAacjoF163p9JRcO+i2shL1wq 11gZlUbF84BuBhPLzUG22fA2Pe4buK0MSGLBrgZTFM94yXEu1GMbbufPwGfwOFlJZz44 0bdFtX4YajU+h73DktOhFzXjRgmQq0OtJ1z01sou/RnwJvQ4cHcxZ0x/YVjtZutYX1nI e2WDjATL7so77lIA/mp1azUZGKkGlXxz1rlJSzfn8lIMEk6QZ2Lzcpul+Oionjdd29CQ FTZuaTgT7+yOUaFTj1UE2yH63ZxqGLVYjBWIA5CK8Uwg7GzH+E5KaJboOH4TWEO/s70v H4lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=0fIj+TcbOvux0juLY871eeLjKt7+KD/wjKX6CWw7XwU=; b=j67Xyw6RMn93bi5ThtvUkSLnmEkk/KGgoMjTpBxYez68/mW2C59HSZhg8rDlwtMibl JVtQbJ1ZZT/vl6We2FS0+C+p32ekCxzGF7TVOdFmE4M0912EUKMrDzkkxe1LHb/y5/qN biYtSVQBpMkmHO/tgoqXRH8JZgLp8XKh40Ub54i5Oi3gQ6/ElYWEBFTT42slRdfW8EpP uvDKMr3UgwZSxxR+cAVEG25w7jhDzTYs6WCNwF8DR1fKZFdaDgHA+I61maHnM7GUxvzq bw04qtbt8pQkxLaiheKYbgoD+COsH4TbGF7s3FSxzrBSrd0I//5FAVM7/7X+BLpJNd2t wtNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=VcN3y73Q; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:35 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:31 +0000 Message-Id: <20180305160415.16760-14-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 13/57] ARM: VGIC: reorder prototypes in vgic.h X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Currently vgic.h both contains prototypes used by Xen arch code outside of the actual VGIC (for instance vgic_vcpu_inject_irq()), and prototypes for functions used by the VGIC internally. Group them to later allow an easy split with one #ifdef. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- Changelog RFC ... v1: - Remove two redundant prototypes - Add Julien's Reviewed-by: xen/include/asm-arm/vgic.h | 54 +++++++++++++++++++++++++--------------------- 1 file changed, 30 insertions(+), 24 deletions(-) diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 4e1c37f091..84d82e6eb3 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -279,49 +279,34 @@ enum gic_sgi_mode; */ #define REG_RANK_INDEX(b, n, s) ((((n) >> s) & ((b)-1)) % 32) -/* - * In the moment vgic_num_irqs() just covers SPIs and the private IRQs, - * as it's mostly used for allocating the pending_irq and irq_desc array, - * in which LPIs don't participate. - */ -#define vgic_num_irqs(d) ((d)->arch.vgic.nr_spis + 32) -extern int domain_vgic_init(struct domain *d, unsigned int nr_spis); -extern void domain_vgic_free(struct domain *d); -extern int vcpu_vgic_init(struct vcpu *v); extern struct vcpu *vgic_get_target_vcpu(struct vcpu *v, unsigned int virq); -extern int vgic_inject_irq(struct domain *d, struct vcpu *v, unsigned int virq, - bool level); extern void vgic_remove_irq_from_queues(struct vcpu *v, struct pending_irq *p); extern void gic_remove_from_lr_pending(struct vcpu *v, struct pending_irq *p); -extern void vgic_clear_pending_irqs(struct vcpu *v); extern void vgic_init_pending_irq(struct pending_irq *p, unsigned int virq); extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq); extern struct pending_irq *spi_to_pending(struct domain *d, unsigned int irq); extern struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v, int b, int n, int s); extern struct vgic_irq_rank *vgic_rank_irq(struct vcpu *v, unsigned int irq); -extern bool vgic_emulate(struct cpu_user_regs *regs, union hsr hsr); extern void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n); extern void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n); extern void register_vgic_ops(struct domain *d, const struct vgic_ops *ops); int vgic_v2_init(struct domain *d, int *mmio_count); int vgic_v3_init(struct domain *d, int *mmio_count); -bool vgic_evtchn_irq_pending(struct vcpu *v); -struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, - unsigned int virq); -int vgic_connect_hw_irq(struct domain *d, struct vcpu *v, unsigned int virq, - struct irq_desc *desc, bool connect); - -extern int domain_vgic_register(struct domain *d, int *mmio_count); -extern int vcpu_vgic_free(struct vcpu *v); extern bool vgic_to_sgi(struct vcpu *v, register_t sgir, enum gic_sgi_mode irqmode, int virq, const struct sgi_target *target); extern bool vgic_migrate_irq(struct vcpu *old, struct vcpu *new, unsigned int irq); -/* Reserve a specific guest vIRQ */ -extern bool vgic_reserve_virq(struct domain *d, unsigned int virq); +/*** Common VGIC functions used by Xen arch code ****/ + +/* + * In the moment vgic_num_irqs() just covers SPIs and the private IRQs, + * as it's mostly used for allocating the pending_irq and irq_desc array, + * in which LPIs don't participate. + */ +#define vgic_num_irqs(d) ((d)->arch.vgic.nr_spis + 32) /* * Allocate a guest VIRQ @@ -329,6 +314,9 @@ extern bool vgic_reserve_virq(struct domain *d, unsigned int virq); * - spi == 1 => allocate an SPI */ extern int vgic_allocate_virq(struct domain *d, bool spi); +/* Reserve a specific guest vIRQ */ +extern bool vgic_reserve_virq(struct domain *d, unsigned int virq); +extern void vgic_free_virq(struct domain *d, unsigned int virq); static inline int vgic_allocate_ppi(struct domain *d) { @@ -340,7 +328,25 @@ static inline int vgic_allocate_spi(struct domain *d) return vgic_allocate_virq(d, true /* spi */); } -extern void vgic_free_virq(struct domain *d, unsigned int virq); +struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, + unsigned int virq); +int vgic_connect_hw_irq(struct domain *d, struct vcpu *v, unsigned int virq, + struct irq_desc *desc, bool connect); + +bool vgic_evtchn_irq_pending(struct vcpu *v); + +int domain_vgic_register(struct domain *d, int *mmio_count); +int domain_vgic_init(struct domain *d, unsigned int nr_spis); +void domain_vgic_free(struct domain *d); +int vcpu_vgic_init(struct vcpu *vcpu); +int vcpu_vgic_free(struct vcpu *vcpu); + +int vgic_inject_irq(struct domain *d, struct vcpu *v, unsigned int virq, + bool level); + +extern void vgic_clear_pending_irqs(struct vcpu *v); + +extern bool vgic_emulate(struct cpu_user_regs *regs, union hsr hsr); void vgic_v2_setup_hw(paddr_t dbase, paddr_t cbase, paddr_t csize, paddr_t vbase, uint32_t aliased_offset); From patchwork Mon Mar 5 16:03:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130677 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853871lja; Mon, 5 Mar 2018 08:07:14 -0800 (PST) X-Google-Smtp-Source: AG47ELtLanv1i5D8yDZXU0IbjV1byyymGxOgbrykJ139Rf3E9uqWB1NCjqS/s++V+lSKKc5uA+rf X-Received: by 10.36.43.137 with SMTP id h131mr8914526ita.97.1520266034326; Mon, 05 Mar 2018 08:07:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266034; cv=none; d=google.com; s=arc-20160816; b=c+YQHPl1lGO+lKXle7vFT9ijFfIZViez9anLoNYU/xdykien9I0K4tkpriKi/KZQ6/ tYf1h18JcdXq6zV7jXYvM0UukvHaP6WF6vtBaBjxviGaLnxL9F3tCaEcUpPhsVkAPEyy /onSZ6tLsckUJlbRIQv/evDAxs0Nmp2+quP9aiEB3eGWLnt1uaKIX3xx1vxMwaBIujJC pAJHaXGfU6s6DX8J6PamXRt9pebuWjvFidzi+xoxnLLQkMi0iMJrIpuUpqNBYqX0YgSf lPyi4Vdj4yDsmUkHcOJILpi6iHnH7crRvz/WQza3zkuwn3PESLqU1RO6nY53EsFVBmvG 1uCA== ARC-Message-Signature: i=1; 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:36 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:32 +0000 Message-Id: <20180305160415.16760-15-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 14/57] ARM: VGIC: Introduce gic_get_nr_lrs() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" So far the number of list registers (LRs) a GIC implements is only needed in the hardware facing side of the VGIC code (gic-vgic.c). The new VGIC will need this information in more and multiple places, so export a function that returns the number. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- Changelog RFC ... v1: - move gic_get_nr_lrs() into gic.h (as a static inline) xen/arch/arm/gic-vgic.c | 10 +++++----- xen/include/asm-arm/gic.h | 6 ++++++ 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index 60c6c463e9..93e42739d9 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -25,7 +25,7 @@ #include #include -#define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_hw_ops->info->nr_lrs) - 1)) +#define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_get_nr_lrs()) - 1)) #undef GIC_DEBUG @@ -110,7 +110,7 @@ static unsigned int gic_find_unused_lr(struct vcpu *v, struct pending_irq *p, unsigned int lr) { - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned int nr_lrs = gic_get_nr_lrs(); unsigned long *lr_mask = (unsigned long *) &this_cpu(lr_mask); struct gic_lr lr_val; @@ -137,7 +137,7 @@ void gic_raise_guest_irq(struct vcpu *v, unsigned int virtual_irq, unsigned int priority) { int i; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned int nr_lrs = gic_get_nr_lrs(); struct pending_irq *p = irq_to_pending(v, virtual_irq); ASSERT(spin_is_locked(&v->arch.vgic.lock)); @@ -251,7 +251,7 @@ void vgic_sync_from_lrs(struct vcpu *v) { int i = 0; unsigned long flags; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned int nr_lrs = gic_get_nr_lrs(); /* The idle domain has no LRs to be cleared. Since gic_restore_state * doesn't write any LR registers for the idle domain they could be @@ -278,7 +278,7 @@ static void gic_restore_pending_irqs(struct vcpu *v) struct pending_irq *p, *t, *p_r; struct list_head *inflight_r; unsigned long flags; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned int nr_lrs = gic_get_nr_lrs(); int lrs = nr_lrs; spin_lock_irqsave(&v->arch.vgic.lock, flags); diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index a23c307c3a..b3f840ea9a 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -374,6 +374,12 @@ struct gic_hw_operations { }; extern const struct gic_hw_operations *gic_hw_ops; + +static inline unsigned int gic_get_nr_lrs(void) +{ + return gic_hw_ops->info->nr_lrs; +} + void register_gic_ops(const struct gic_hw_operations *ops); int gic_make_hwdom_dt_node(const struct domain *d, const struct dt_device_node *gic, From patchwork Mon Mar 5 16:03:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130653 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853480lja; Mon, 5 Mar 2018 08:06:56 -0800 (PST) X-Google-Smtp-Source: AG47ELt/flhgcA4rAjwYKCC6pXhUaMK0PXQeeL0bz5/sO1Tu8owuiVMD/C4CgtK4Lvsh7o+3Dyl/ X-Received: by 10.36.76.21 with SMTP id a21mr14870043itb.118.1520266015935; Mon, 05 Mar 2018 08:06:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266015; cv=none; d=google.com; s=arc-20160816; b=Fv1G6FVArs79V9jvUaiEjQ/Yi1bg8XboricPPnw5AnPhcxwZT2v+x5wSOOol84JHt7 dO4Hp4dErJcFVeZFyFJ8g2CyM58UVoiYObd7gmFEaTzOcPZejEhtsIIardfGUPe5ar36 cZEzIEACHtVw3i6Xoc1Ly7FvSZa5V0zIw7bmrGDnM2NOV/kG9U3WVuG3CkJcBJgDkXKB J3B+vrOzsLrvj7hD3Oumlv+siHJ3EWA4NeS7u+8T+SIxQnC4IUx6GspfiN0FC6ahoLt5 +u8zIXaGwCaAEnc5TsG8Bvpe6iXRelFehdPOM0TkFJe3K+oFlZ/m2QdRjsKZMlIZD+L7 kNwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=f/+OgCUaeRLDYqRb9CeWX5+crHOM2b7hW0FZceewZHU=; b=eJEn/uWwsWXHiRZ442QsbrJ6TT5yj+WsOJhFHOkHf1YoFnsAFyAcC1RWxLhYL/pMNS bq1vhH0rluLEMzuPmx9qXHi+cdpGYfMO4CA1CGDUy2eS778VYBLao51dtiqoWOqciyVh f41Jpuve9eSOK5L49JeLKF6yRBuCVPLLRsUZxpVIaCunyqz1Ip9kRlw6hOms8gTVWWcs /hkNjdd0kA/1OpenVkgk4XgoNzyz+1GuFMN1W0NDqR4ldaHVNL4LDwL0nH1hTWvvQI4v piczCEQaXePrHNzV8ncXxwERe/9fdcVoFwFCUhyr+bpBhpU64U5wG9SWb76fsUmEo45t 1whQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=RYxkjQgH; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:37 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:33 +0000 Message-Id: <20180305160415.16760-16-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 15/57] ARM: GICv2: Extend and adjust register definitions X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The new VGIC will shortly use more bits of the various GIC registers, so add the respective definitions from the manual. This includes bits from the GICC_CTL register and some minor other bits. Adjust the usage of ICC_CTL_ENABLE on the way, to be more precise about which of the two enable bits we actually deal with. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - extend commit message xen/arch/arm/gic-v2.c | 2 +- xen/include/asm-arm/gic.h | 18 ++++++++++++++++-- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 2b271ba322..7938a42591 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -358,7 +358,7 @@ static void gicv2_cpu_init(void) /* Finest granularity of priority */ writel_gicc(0x0, GICC_BPR); /* Turn on delivery */ - writel_gicc(GICC_CTL_ENABLE|GICC_CTL_EOI, GICC_CTLR); + writel_gicc(GICC_CTL_ENABLE0|GICC_CTL_EOI, GICC_CTLR); } static void gicv2_cpu_disable(void) diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index b3f840ea9a..8fab458d7f 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -77,6 +77,7 @@ #define GICC_EOIR (0x0010) #define GICC_RPR (0x0014) #define GICC_HPPIR (0x0018) +#define GICC_ABPR (0x001c) #define GICC_APR (0x00D0) #define GICC_NSAPR (0x00E0) #define GICC_IIDR (0x00FC) @@ -102,8 +103,18 @@ #define GICD_TYPE_SEC 0x400 #define GICD_TYPER_DVIS (1U << 18) -#define GICC_CTL_ENABLE 0x1 -#define GICC_CTL_EOI (0x1 << 9) +#define GICC_CTL_ENABLE0_SHIFT 0 +#define GICC_CTL_ENABLE0 (1U << GICC_CTL_ENABLE0_SHIFT) +#define GICC_CTL_ENABLE1_SHIFT 1 +#define GICC_CTL_ENABLE1 (1U << GICC_CTL_ENABLE1) +#define GICC_CTL_AC_SHIFT 2 +#define GICC_CTL_AC (1U << GICC_CTL_AC_SHIFT) +#define GICC_CTL_FIQEN_SHIFT 3 +#define GICC_CTL_FIQEN (1U << GICC_CTL_FIQEN_SHIFT) +#define GICC_CTL_CBPR_SHIFT 4 +#define GICC_CTL_CBPR (1U << GICC_CTL_CBPR_SHIFT) +#define GICC_CTL_EOI_SHIFT 9 +#define GICC_CTL_EOI (1U << GICC_CTL_EOI_SHIFT) #define GICC_IA_IRQ 0x03ff #define GICC_IA_CPU_MASK 0x1c00 @@ -127,6 +138,9 @@ #define GICH_MISR_VGRP1E (1 << 6) #define GICH_MISR_VGRP1D (1 << 7) +#define GICV_PMR_PRIORITY_SHIFT 3 +#define GICV_PMR_PRIORITY_MASK (0x1f << GICV_PMR_PRIORITY_SHIFT) + /* * The minimum GICC_BPR is required to be in the range 0-3. We set * GICC_BPR to 0 but we must expect that it might be 3. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:38 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:34 +0000 Message-Id: <20180305160415.16760-17-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 16/57] ARM: GICv3: rename HYP interface definitions to use ICH_ prefix X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" On a GICv3 in non-compat mode the hypervisor interface is always accessed via system registers. Those register names have a "ICH_" prefix in the manual, to differentiate them from the MMIO registers. Also those registers are mostly 64-bit (compared to the 32-bit GICv2 registers) and use different bit assignments. To make this obvious and to avoid clashes with double definitions using the same names for actually different bits, lets change all GICv3 hypervisor interface registers to use the "ICH_" prefix from the manual. This renames the definitions in gic_v3_defs.h and their usage in gic-v3.c and is needed to allow co-existence of the GICv2 and GICv3 definitions in the same file. Signed-off-by: Andre Przywara Acked-by: Julien Grall --- Changelog RFC ... v1: - new patch xen/arch/arm/gic-v3.c | 48 +++++++++++++++++++------------------- xen/include/asm-arm/gic_v3_defs.h | 49 +++++++++++++++++++-------------------- 2 files changed, 48 insertions(+), 49 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index ea14ab4028..3e381d031b 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -830,14 +830,14 @@ static void gicv3_hyp_init(void) uint32_t vtr; vtr = READ_SYSREG32(ICH_VTR_EL2); - gicv3_info.nr_lrs = (vtr & GICH_VTR_NRLRGS) + 1; - gicv3.nr_priorities = ((vtr >> GICH_VTR_PRIBITS_SHIFT) & - GICH_VTR_PRIBITS_MASK) + 1; + gicv3_info.nr_lrs = (vtr & ICH_VTR_NRLRGS) + 1; + gicv3.nr_priorities = ((vtr >> ICH_VTR_PRIBITS_SHIFT) & + ICH_VTR_PRIBITS_MASK) + 1; if ( !((gicv3.nr_priorities > 4) && (gicv3.nr_priorities < 8)) ) panic("GICv3: Invalid number of priority bits\n"); - WRITE_SYSREG32(GICH_VMCR_EOI | GICH_VMCR_VENG1, ICH_VMCR_EL2); + WRITE_SYSREG32(ICH_VMCR_EOI | ICH_VMCR_VENG1, ICH_VMCR_EL2); WRITE_SYSREG32(GICH_HCR_EN, ICH_HCR_EL2); } @@ -976,21 +976,21 @@ static void gicv3_update_lr(int lr, unsigned int virq, uint8_t priority, BUG_ON(lr >= gicv3_info.nr_lrs); BUG_ON(lr < 0); - val = (((uint64_t)state & 0x3) << GICH_LR_STATE_SHIFT); + val = (((uint64_t)state & 0x3) << ICH_LR_STATE_SHIFT); /* * When the guest is GICv3, all guest IRQs are Group 1, as Group0 * would result in a FIQ in the guest, which it wouldn't expect */ if ( current->domain->arch.vgic.version == GIC_V3 ) - val |= GICH_LR_GRP1; + val |= ICH_LR_GRP1; - val |= (uint64_t)priority << GICH_LR_PRIORITY_SHIFT; - val |= ((uint64_t)virq & GICH_LR_VIRTUAL_MASK) << GICH_LR_VIRTUAL_SHIFT; + val |= (uint64_t)priority << ICH_LR_PRIORITY_SHIFT; + val |= ((uint64_t)virq & ICH_LR_VIRTUAL_MASK) << ICH_LR_VIRTUAL_SHIFT; if ( hw_irq != INVALID_IRQ ) - val |= GICH_LR_HW | (((uint64_t)hw_irq & GICH_LR_PHYSICAL_MASK) - << GICH_LR_PHYSICAL_SHIFT); + val |= ICH_LR_HW | (((uint64_t)hw_irq & ICH_LR_PHYSICAL_MASK) + << ICH_LR_PHYSICAL_SHIFT); gicv3_ich_write_lr(lr, val); } @@ -1006,25 +1006,25 @@ static void gicv3_read_lr(int lr, struct gic_lr *lr_reg) lrv = gicv3_ich_read_lr(lr); - lr_reg->pirq = (lrv >> GICH_LR_PHYSICAL_SHIFT) & GICH_LR_PHYSICAL_MASK; - lr_reg->virq = (lrv >> GICH_LR_VIRTUAL_SHIFT) & GICH_LR_VIRTUAL_MASK; + lr_reg->pirq = (lrv >> ICH_LR_PHYSICAL_SHIFT) & ICH_LR_PHYSICAL_MASK; + lr_reg->virq = (lrv >> ICH_LR_VIRTUAL_SHIFT) & ICH_LR_VIRTUAL_MASK; - lr_reg->priority = (lrv >> GICH_LR_PRIORITY_SHIFT) & GICH_LR_PRIORITY_MASK; - lr_reg->state = (lrv >> GICH_LR_STATE_SHIFT) & GICH_LR_STATE_MASK; - lr_reg->hw_status = (lrv >> GICH_LR_HW_SHIFT) & GICH_LR_HW_MASK; - lr_reg->grp = (lrv >> GICH_LR_GRP_SHIFT) & GICH_LR_GRP_MASK; + lr_reg->priority = (lrv >> ICH_LR_PRIORITY_SHIFT) & ICH_LR_PRIORITY_MASK; + lr_reg->state = (lrv >> ICH_LR_STATE_SHIFT) & ICH_LR_STATE_MASK; + lr_reg->hw_status = (lrv >> ICH_LR_HW_SHIFT) & ICH_LR_HW_MASK; + lr_reg->grp = (lrv >> ICH_LR_GRP_SHIFT) & ICH_LR_GRP_MASK; } static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr) { uint64_t lrv = 0; - lrv = ( ((u64)(lr->pirq & GICH_LR_PHYSICAL_MASK) << GICH_LR_PHYSICAL_SHIFT)| - ((u64)(lr->virq & GICH_LR_VIRTUAL_MASK) << GICH_LR_VIRTUAL_SHIFT) | - ((u64)(lr->priority & GICH_LR_PRIORITY_MASK) << GICH_LR_PRIORITY_SHIFT)| - ((u64)(lr->state & GICH_LR_STATE_MASK) << GICH_LR_STATE_SHIFT) | - ((u64)(lr->hw_status & GICH_LR_HW_MASK) << GICH_LR_HW_SHIFT) | - ((u64)(lr->grp & GICH_LR_GRP_MASK) << GICH_LR_GRP_SHIFT) ); + lrv = ( ((u64)(lr->pirq & ICH_LR_PHYSICAL_MASK) << ICH_LR_PHYSICAL_SHIFT)| + ((u64)(lr->virq & ICH_LR_VIRTUAL_MASK) << ICH_LR_VIRTUAL_SHIFT) | + ((u64)(lr->priority & ICH_LR_PRIORITY_MASK) << ICH_LR_PRIORITY_SHIFT)| + ((u64)(lr->state & ICH_LR_STATE_MASK) << ICH_LR_STATE_SHIFT) | + ((u64)(lr->hw_status & ICH_LR_HW_MASK) << ICH_LR_HW_SHIFT) | + ((u64)(lr->grp & ICH_LR_GRP_MASK) << ICH_LR_GRP_SHIFT) ); gicv3_ich_write_lr(lr_reg, lrv); } @@ -1043,8 +1043,8 @@ static void gicv3_hcr_status(uint32_t flag, bool status) static unsigned int gicv3_read_vmcr_priority(void) { - return ((READ_SYSREG32(ICH_VMCR_EL2) >> GICH_VMCR_PRIORITY_SHIFT) & - GICH_VMCR_PRIORITY_MASK); + return ((READ_SYSREG32(ICH_VMCR_EL2) >> ICH_VMCR_PRIORITY_SHIFT) & + ICH_VMCR_PRIORITY_MASK); } /* Only support reading GRP1 APRn registers */ diff --git a/xen/include/asm-arm/gic_v3_defs.h b/xen/include/asm-arm/gic_v3_defs.h index 412e41afed..947de5162d 100644 --- a/xen/include/asm-arm/gic_v3_defs.h +++ b/xen/include/asm-arm/gic_v3_defs.h @@ -160,31 +160,30 @@ #define LPI_PROP_RES1 (1 << 1) #define LPI_PROP_ENABLED (1 << 0) -#define GICH_VMCR_EOI (1 << 9) -#define GICH_VMCR_VENG1 (1 << 1) - -#define GICH_LR_VIRTUAL_MASK 0xffff -#define GICH_LR_VIRTUAL_SHIFT 0 -#define GICH_LR_PHYSICAL_MASK 0x3ff -#define GICH_LR_PHYSICAL_SHIFT 32 -#define GICH_LR_STATE_MASK 0x3 -#define GICH_LR_STATE_SHIFT 62 -#define GICH_LR_PRIORITY_MASK 0xff -#define GICH_LR_PRIORITY_SHIFT 48 -#define GICH_LR_HW_MASK 0x1 -#define GICH_LR_HW_SHIFT 61 -#define GICH_LR_GRP_MASK 0x1 -#define GICH_LR_GRP_SHIFT 60 -#define GICH_LR_MAINTENANCE_IRQ (1UL<<41) -#define GICH_LR_GRP1 (1UL<<60) -#define GICH_LR_HW (1UL<<61) - -#define GICH_VTR_NRLRGS 0x3f -#define GICH_VTR_PRIBITS_MASK 0x7 -#define GICH_VTR_PRIBITS_SHIFT 29 - -#define GICH_VMCR_PRIORITY_MASK 0xff -#define GICH_VMCR_PRIORITY_SHIFT 24 +#define ICH_VMCR_EOI (1 << 9) +#define ICH_VMCR_VENG1 (1 << 1) +#define ICH_VMCR_PRIORITY_MASK 0xff +#define ICH_VMCR_PRIORITY_SHIFT 24 + +#define ICH_LR_VIRTUAL_MASK 0xffff +#define ICH_LR_VIRTUAL_SHIFT 0 +#define ICH_LR_PHYSICAL_MASK 0x3ff +#define ICH_LR_PHYSICAL_SHIFT 32 +#define ICH_LR_STATE_MASK 0x3 +#define ICH_LR_STATE_SHIFT 62 +#define ICH_LR_PRIORITY_MASK 0xff +#define ICH_LR_PRIORITY_SHIFT 48 +#define ICH_LR_HW_MASK 0x1 +#define ICH_LR_HW_SHIFT 61 +#define ICH_LR_GRP_MASK 0x1 +#define ICH_LR_GRP_SHIFT 60 +#define ICH_LR_MAINTENANCE_IRQ (1UL<<41) +#define ICH_LR_GRP1 (1UL<<60) +#define ICH_LR_HW (1UL<<61) + +#define ICH_VTR_NRLRGS 0x3f +#define ICH_VTR_PRIBITS_MASK 0x7 +#define ICH_VTR_PRIBITS_SHIFT 29 #define ICH_SGI_IRQMODE_SHIFT 40 #define ICH_SGI_IRQMODE_MASK 0x1 From patchwork Mon Mar 5 16:03:35 2018 Content-Type: text/plain; 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:39 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:35 +0000 Message-Id: <20180305160415.16760-18-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 17/57] ARM: Introduce kick_vcpu() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" If we change something in a vCPU that affects its runnability or otherwise needs the vCPU's attention, we might need to tell the scheduler about it. We are using this in one place (vIRQ injection) at the moment, but will need this at more places soon. So let's factor out this functionality in the new kick_vcpu() function and make this available to the whole Xen arch code. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - new patch xen/arch/arm/smp.c | 14 ++++++++++++++ xen/arch/arm/vgic.c | 10 ++-------- xen/include/asm-arm/smp.h | 3 +++ 3 files changed, 19 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/smp.c b/xen/arch/arm/smp.c index 62f57f0ba2..381a4786a2 100644 --- a/xen/arch/arm/smp.c +++ b/xen/arch/arm/smp.c @@ -4,6 +4,8 @@ #include #include #include +#include +#include void flush_tlb_mask(const cpumask_t *mask) { @@ -32,6 +34,18 @@ void smp_send_call_function_mask(const cpumask_t *mask) } } +void kick_vcpu(struct vcpu *vcpu) +{ + bool running = vcpu->is_running; + + vcpu_unblock(vcpu); + if ( running && vcpu != current ) + { + perfc_incr(vgic_cross_cpu_intr_inject); + smp_send_event_check_mask(cpumask_of(vcpu->processor)); + } +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index 3c77d5fef6..e44de9ea95 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -530,7 +530,6 @@ int vgic_inject_irq(struct domain *d, struct vcpu *v, unsigned int virq, uint8_t priority; struct pending_irq *iter, *n; unsigned long flags; - bool running; /* * For edge triggered interrupts we always ignore a "falling edge". @@ -590,14 +589,9 @@ int vgic_inject_irq(struct domain *d, struct vcpu *v, unsigned int virq, list_add_tail(&n->inflight, &v->arch.vgic.inflight_irqs); out: spin_unlock_irqrestore(&v->arch.vgic.lock, flags); + /* we have a new higher priority irq, inject it into the guest */ - running = v->is_running; - vcpu_unblock(v); - if ( running && v != current ) - { - perfc_incr(vgic_cross_cpu_intr_inject); - smp_send_event_check_mask(cpumask_of(v->processor)); - } + kick_vcpu(v); return 0; } diff --git a/xen/include/asm-arm/smp.h b/xen/include/asm-arm/smp.h index 3c122681d7..7c8ef75789 100644 --- a/xen/include/asm-arm/smp.h +++ b/xen/include/asm-arm/smp.h @@ -28,6 +28,9 @@ extern void init_secondary(void); extern void smp_init_cpus(void); extern void smp_clear_cpu_maps (void); extern int smp_get_max_cpus (void); + +void kick_vcpu(struct vcpu *vcpu); + #endif /* From patchwork Mon Mar 5 16:03:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130646 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853284lja; Mon, 5 Mar 2018 08:06:47 -0800 (PST) X-Google-Smtp-Source: AG47ELu/KsY5FjPGpZLbsQXei8P7ox4bouVTd9B5o8p2QYzsZGG2xqXBmaAtD8SEsxrlpp90HB+N X-Received: by 10.36.34.11 with SMTP id o11mr14855038ito.60.1520266007371; Mon, 05 Mar 2018 08:06:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266007; cv=none; d=google.com; s=arc-20160816; b=VARKmSwGNZO8zPtGGwLlH3TnOib/qtAeewU05wMTcWzwXBYm3IpHnkWxhuKmjaAKO3 lly2fhZ4gtKERBvH++YI5Q8Pg4Kavo4QW8spZLk1f7WaQWRFelIqiWnpnU11GFShAfPX GPclgyFEfz6TiLOzwLXpQXTie+zT5aLmgussbgBDsR4wdoKt3b2LdiFuxnp1zxSnaOBn PZy2EFIb42puQgS9atUDTY9zYO2N1pcmF7XN34pKT2XMwq4GB6PfDKu3TClCeGArtfEA o/2FUegp9PNwciXIQWxD/SnFYY4WfI9N5+Hx15qh36PzmCsgwn/Zaem9scGokGGSJEtk kxrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=UtWZffQA/vxd6rDN+g3Qm/UQ2KOhosBrwXPt2xUCE98=; b=q1jugvFjzZ1+opYHHq9rkZA/V5XjSW/spdaIDAWMpnWnMdrFWnn9dJTst8wZYd+WZP mdCEXaTIH9di1jLEg519MLJ3svkdXaCEU2mQKa3sHfSw98z3e2giwd2Bm8GBmSYdoaUL i9sxn2YGSFpzBhqrQ3F0uiulhw47japsh8Ui/0ukAeRl97MKjadCUWYB6eGdaiyELoUt VRbcnu2iTjL58f+gScJGfN+Dcyo0v53znp+DNtj7R7zahT+p6uOFaeC2MZcqlvNorSF9 4qLJ4R6i0zb0L1kXPIq7etXo/B3Q6th23qBvLkIB9BA/JCvTqKL9zR9QKhQpqofbIVRm JR5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=J3CUzQSc; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:40 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:36 +0000 Message-Id: <20180305160415.16760-19-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 18/57] ARM: GICv2: introduce gicv2_poke_irq() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The GICv2 uses bitmaps spanning several MMIO registers for holding some interrupt state. Similar to GICv3, add a poke helper functions to set a bit for a given irq_desc in one of those bitmaps. At the moment there is only one use in gic-v2.c, but there will be more coming soon. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- Changelog RFC ... v1: - new patch xen/arch/arm/gic-v2.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 7938a42591..618dd94120 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -235,6 +235,11 @@ static unsigned int gicv2_read_irq(void) return (readl_gicc(GICC_IAR) & GICC_IA_IRQ); } +static void gicv2_poke_irq(struct irq_desc *irqd, uint32_t offset) +{ + writel_gicd(1U << (irqd->irq % 32), offset + (irqd->irq / 32) * 4); +} + static void gicv2_set_irq_type(struct irq_desc *desc, unsigned int type) { uint32_t cfg, actual, edgebit; @@ -509,7 +514,6 @@ static unsigned int gicv2_read_apr(int apr_reg) static void gicv2_irq_enable(struct irq_desc *desc) { unsigned long flags; - int irq = desc->irq; ASSERT(spin_is_locked(&desc->lock)); @@ -517,20 +521,19 @@ static void gicv2_irq_enable(struct irq_desc *desc) clear_bit(_IRQ_DISABLED, &desc->status); dsb(sy); /* Enable routing */ - writel_gicd((1u << (irq % 32)), GICD_ISENABLER + (irq / 32) * 4); + gicv2_poke_irq(desc, GICD_ISENABLER); spin_unlock_irqrestore(&gicv2.lock, flags); } static void gicv2_irq_disable(struct irq_desc *desc) { unsigned long flags; - int irq = desc->irq; ASSERT(spin_is_locked(&desc->lock)); spin_lock_irqsave(&gicv2.lock, flags); /* Disable routing */ - writel_gicd(1u << (irq % 32), GICD_ICENABLER + (irq / 32) * 4); + gicv2_poke_irq(desc, GICD_ICENABLER); set_bit(_IRQ_DISABLED, &desc->status); spin_unlock_irqrestore(&gicv2.lock, flags); } From patchwork Mon Mar 5 16:03:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130667 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853704lja; Mon, 5 Mar 2018 08:07:06 -0800 (PST) X-Google-Smtp-Source: AG47ELv43DtJFsYINYCRunlBsuhYvlOhWKlCctqdTqAzpojbCkIghYD5gpa9XBEFtkKcVhFqr5Ts X-Received: by 10.107.149.70 with SMTP id x67mr17566079iod.156.1520266026190; Mon, 05 Mar 2018 08:07:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266026; cv=none; d=google.com; s=arc-20160816; b=dZTDUEPa0FXNv1B7f8h4lDfQRaJ7ELBhX0/VQDLZ89Mi2TzE3934uNhGTl3VW7jp9n ijKx74H2tCuCeUmjw78F55CgtZb6Xw0dWfZ4ZtWIJqfoCKOkMwte/JvSOzX3OWW1QxXy Hx8kycxnGqg/gYgmvUWI4/nb4x+goAqcxjfknXxhmnDNBIDCIk6sCYGe8SBAot7K2oqE FpsHrWSAXjakCKiFgSLQIIQuZM5toRUABNE0pyudbNHG44CE7r8L/yOUtWMCaJKwPVho qbQPSc7elmNVGnIHq+6D3R4xL02ALqSYVXVDKpAcjJV98QOR+/PEv4QdpaL04Z/OsSup h66g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=c8heAJVG7Af5YvpAXHLl8w9dtN4EdkQkG8+LDG9OJRc=; b=sb30dM5IXl3NVotQQHkSnA4R4HzUHqlQO4RaOc8QLMpToqPhO9aWOXg17k/RV2GuuU oz9RegZA1TNjEfg9kYXjxYsiSCNaJmt87Ca70HQTapfz9CdGvIivmOyeMAGkcrcCp+H/ WF4X924c95GUgMcllkA1+FS9JhM5D9i9Jr3b1eIQD4KeCictP8FajEXrSbBSmoin0rR3 xkWH1A0GhvXhKOt6t1Rdum3Ii96AEfb9Om74WzEFWlr5d9pPz7zk6l2OMN1qgTMQRRX8 ogY2dd9AcRifCDckbZvtOlQnnuioX1d0Mxw2rhQ5qr/2J00bAy6kIcImD0/7ygyW5E1F OAIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=dO8X1Jq3; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 68si6042198itx.45.2018.03.05.08.07.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Mar 2018 08:07:06 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=dO8X1Jq3; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1essbV-0007W7-4s; Mon, 05 Mar 2018 16:04:45 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1essbT-0007SN-K3 for xen-devel@lists.xenproject.org; Mon, 05 Mar 2018 16:04:43 +0000 X-Inumbo-ID: c315898c-208e-11e8-ba59-bc764e045a96 Received: from mail-wm0-x244.google.com (unknown [2a00:1450:400c:c09::244]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id c315898c-208e-11e8-ba59-bc764e045a96; Mon, 05 Mar 2018 17:03:37 +0100 (CET) Received: by mail-wm0-x244.google.com with SMTP id z81so16905044wmb.4 for ; Mon, 05 Mar 2018 08:04:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CQoYBoPLg4VB46nZ7qBAunaDUXtTUAw1DLZOvtEg9wo=; b=dO8X1Jq3l4aDj1x0Ql+BQIZbYEFoTpeplBdXT1JlPJNps8Uzm9NYfoIyULLE/5xvo4 Bsa0K09xEn80qKRlDZG0HnObLoBhEbS4ZjVbhZq4aKum7I4eDHHXTyhQ3lotC9/i0cvX dQLWqq3MthUEUbromehQNsfqSmagUkSnwezxM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CQoYBoPLg4VB46nZ7qBAunaDUXtTUAw1DLZOvtEg9wo=; b=fvJ88O3/Qv8dEEzDiDL8pnJHBrdJCuG47Kkdaxct7LRHgWIpZPtjzpPNxSFnJICR/v qTBn2DB58b46OKcZLQ0GZhIo4QwIjrKuVFyoK60oWHus0COGa1+jJz2lwdFrVAbJrvd2 BoV3p0zSPUsgEI6F5r5IHwWgkbDrDKuLCJNXQg3q5XCmkrvdIfIqQMRPrU4P5sdlDWdP NrTOyssGr5cCZFreRUwym3e6MzUA364OyylOu3lbIoaOGMEbQhjW9Ax0c7AE9RdX41pi GSBX0ktEI1Qu60Gs3imQFkZNow4x8cJznky9ggCzvGffs6nTF51bPh4JqNL/hQoyOsVA /qqw== X-Gm-Message-State: AElRT7HJrFBlCQLOuCa8S2sOJMuwHCGkYnX4W3NQbd40d60rohoFDfxe cMKC9kx5L7qEGB5mVDKoxiw4AA== X-Received: by 10.28.50.69 with SMTP id y66mr9336644wmy.133.1520265881821; Mon, 05 Mar 2018 08:04:41 -0800 (PST) Received: from e104803-lin.lan (mail.andrep.de. [217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:41 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:37 +0000 Message-Id: <20180305160415.16760-20-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 19/57] ARM: GICv3: poke_irq: make RWP optional X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" A GICv3 hardware implementation can be implemented in several parts that communicate with each other (think multi-socket systems). To make sure that critical settings have arrived at all endpoints, some bits are tracked using the RWP bit in the GICD_CTLR register, which signals whether a register write is still in progress. However this only applies to *some* registers, namely the bits in the GICD_ICENABLER (disabling interrupts) and some bits in the GICD_CTLR register (cf. Arm IHI 0069D, 8.9.4: RWP, bit[31]). But our gicv3_poke_irq() was always polling this bit before returning, resulting in pointless MMIO reads for many registers. Add an option to gicv3_poke_irq() to state whether we want to wait for this bit and use it accordingly to match the spec. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- Changelog RFC ... v1: - new patch xen/arch/arm/gic-v3.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 3e381d031b..44dfba2267 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -428,9 +428,9 @@ static void gicv3_dump_state(const struct vcpu *v) } } -static void gicv3_poke_irq(struct irq_desc *irqd, u32 offset) +static void gicv3_poke_irq(struct irq_desc *irqd, u32 offset, bool wait_for_rwp) { - u32 mask = 1 << (irqd->irq % 32); + u32 mask = 1U << (irqd->irq % 32); void __iomem *base; if ( irqd->irq < NR_GIC_LOCAL_IRQS ) @@ -439,17 +439,19 @@ static void gicv3_poke_irq(struct irq_desc *irqd, u32 offset) base = GICD; writel_relaxed(mask, base + offset + (irqd->irq / 32) * 4); - gicv3_wait_for_rwp(irqd->irq); + + if ( wait_for_rwp ) + gicv3_wait_for_rwp(irqd->irq); } static void gicv3_unmask_irq(struct irq_desc *irqd) { - gicv3_poke_irq(irqd, GICD_ISENABLER); + gicv3_poke_irq(irqd, GICD_ISENABLER, false); } static void gicv3_mask_irq(struct irq_desc *irqd) { - gicv3_poke_irq(irqd, GICD_ICENABLER); + gicv3_poke_irq(irqd, GICD_ICENABLER, true); } static void gicv3_eoi_irq(struct irq_desc *irqd) From patchwork Mon Mar 5 16:03:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130668 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853728lja; Mon, 5 Mar 2018 08:07:07 -0800 (PST) X-Google-Smtp-Source: AG47ELuNG2UVgq3mLXZXIxpWZ5k0TmZb1Ss6MJSKdCqzcNm5Jb93xLfMBXCPVuDQ5UAGhmgl6zKm X-Received: by 10.36.83.142 with SMTP id n136mr14858070itb.0.1520266027497; Mon, 05 Mar 2018 08:07:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266027; cv=none; d=google.com; s=arc-20160816; b=Bfc736EOHK55EIPw/QepiKTRg3bHL9/iDwc2Hz9srPnLJBoK8b3JVMIwFXPAVhhm3B P31ltbR90RS0wOij949l7laB/fMSVEEPu4fWHiqEwaX16Z0oV34BHzrRLYek+v/1otZJ 5qijrTG4238LpzSPRPXauGook4J1WYnC/em0r/SQbkA2eCEhRU+hY10lcgBDaD8fep4I rpOjceEuMMA2CXv5MEYrBZoC8huub7rMgdgTCMQv1v5xbf/PJNOJL0zyjUxVkgYvb4u7 vNqg8wy3aI2A1z4salRWon6B+LFa6vN8KMsBKL6FbsTj7JeC47RgkbzS/+rQjA+L08HE t12w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=dNiyHCdPEtA5nZCtNcPPXgDiZNfL+s0SYvkxwJbwnoI=; b=lHEz9pXRtgAqj/6y9W6HJ4qPssG40LQVoQ6p0m2GimSR9Nfj1uWQD5HLSFxuEPXBs9 LEdqr6v5EW75kldjB7YBGG6MJ8t+npM8jOP/Pgk8xNyLdgvCEjnSVQB+zNq+fEQu7io4 mfFnBQ2HSnbTY+b2FakmZ3k4Kcim87sjtJ/x52+Y424WnJviYiYrT/brkhJQrJtFKd5w aHbNwzhW3OygFaDy5/NHPO7EGn6ZrsUrpUMZGPfDCY2XGFaccNo4XRR5fw3uBg5Z8xhv utcWpJ9SUWp8uBGQBpc/oDdnTbuz5QMMO4j/xNikWRAhflO8SZwdA2hK59OXnxRbwUdk 8jtw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=KANCjO/V; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:42 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:38 +0000 Message-Id: <20180305160415.16760-21-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 20/57] ARM: GICv2: fix GICH_V2_LR definitions X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The bit definition for the CPUID mask in the GICv2 LR register was wrong, fortunately the current implementation does not use that bit. Fix it up (it's starting at bit 10, not bit 9) and clean up some nearby definitions on the way. This will be used by the new VGIC shortly. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- Changelog RFC ... v1: - new patch xen/arch/arm/gic-v2.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 618dd94120..031be920cc 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -57,10 +57,11 @@ #define GICH_V2_LR_HW_MASK 0x1 #define GICH_V2_LR_GRP_SHIFT 30 #define GICH_V2_LR_GRP_MASK 0x1 -#define GICH_V2_LR_MAINTENANCE_IRQ (1<<19) -#define GICH_V2_LR_GRP1 (1<<30) -#define GICH_V2_LR_HW (1<<31) -#define GICH_V2_LR_CPUID_SHIFT 9 +#define GICH_V2_LR_MAINTENANCE_IRQ (1U << 19) +#define GICH_V2_LR_GRP1 (1U << 30) +#define GICH_V2_LR_HW (1U << GICH_V2_LR_HW_SHIFT) +#define GICH_V2_LR_CPUID_SHIFT 10 +#define GICH_V2_LR_CPUID_MASK 0x7 #define GICH_V2_VTR_NRLRGS 0x3f #define GICH_V2_VMCR_PRIORITY_MASK 0x1f From patchwork Mon Mar 5 16:03:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130648 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853391lja; Mon, 5 Mar 2018 08:06:51 -0800 (PST) X-Google-Smtp-Source: AG47ELtnnX55Gdlj0C/IAiaQNUaZ4vwZIiQYNyfz1H70mVJaLpmg9wo3vX5S4IBY9DbXM5YH9hFG X-Received: by 10.36.46.78 with SMTP id i75mr14054607ita.96.1520266011828; Mon, 05 Mar 2018 08:06:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266011; cv=none; d=google.com; s=arc-20160816; b=XWiAbo9XhsylYtZ3Jzlzy1KI/tQwBwdLOuN2yxt1gq7LjMXxlDGobCofExX3znQ+gK HF3r/Jtnu19aLLnzYFIdExSH4bWNdq9Yp4D42ALUJCqjA/SFy9KbQ2DtmtvUL2ygf11f rVl7Arkbpjss+6raZCKQTYHNZ0vnNvh67uPIheEAwjYE7jPWn+HDUhlRicvq6JIJXrrW yDvZLu6dTNzwS9Wmy8qFF8xgdun1ExnfuN5lCqqlK4Jzf+X4Q3om8YyYlkKxFHJ4aLiS xGy9UHoR5UpNyri2p598tGSNClAyrcyzwH6d4ncAyLFc6yWLPJFM+/axl2JStOhUSELd k8KQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=0pgKoZ+pnywOjnBmZZBYjC31jfeRFGKeiLKBRLsJh+s=; b=pIQtw5TxkjveyNHoBxooSO6DypuWj1EHLzSZYWHcCS9D7kGxUiKjRHoAJLaWDHDl0w o8QshQV/izdlXEAwnuQVAM7JSwyv1Ym8ax5W/o5WTov8byxl0cOfF8uR6y3wHcmk3Xp1 xxVhGHjKPlxdybcahsztQhfduNkBB9odz62FWcuy45cTvrk8JFjnuxsAhKLOo7ieBAI+ ArFo5+6o7QCEOowhLqybcWcXV86YdJ3WMgsQlz+/6JljejUgDU6+EFV6NsXIayOjupO6 zcZ2yGRtB1i8qcknBS/IDZ/krZVl+M1otnhddoa3v/0EXiH/v9rU2U63+xmczVW/uhfv UL2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=jTqF/aYw; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:43 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:39 +0000 Message-Id: <20180305160415.16760-22-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 21/57] ARM: GICv2: extend LR read/write functions to cover EOI and source X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" So far our LR read/write functions do not handle the EOI bit and the source CPUID bits in an LR, because the current VGIC implementation does not use them. Extend the gic_lr data structure to hold these bits of information as well, packing it on the way to avoid it to grow. Then extract and assemble those bits from/to an LR. This allows the new VGIC to use this information. Signed-off-by: Andre Przywara Nacked-by: Julien Grall --- Changelog RFC ... v1: - new patch xen/arch/arm/gic-v2.c | 7 +++++++ xen/include/asm-arm/gic.h | 8 +++++--- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 031be920cc..c5ec0d4d35 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -470,6 +470,9 @@ static void gicv2_read_lr(int lr, struct gic_lr *lr_reg) lr_reg->state = (lrv >> GICH_V2_LR_STATE_SHIFT) & GICH_V2_LR_STATE_MASK; lr_reg->hw_status = (lrv >> GICH_V2_LR_HW_SHIFT) & GICH_V2_LR_HW_MASK; lr_reg->grp = (lrv >> GICH_V2_LR_GRP_SHIFT) & GICH_V2_LR_GRP_MASK; + lr_reg->eoi = !!(lrv & GICH_V2_LR_MAINTENANCE_IRQ); + if ( lr_reg->virq < NR_GIC_SGI ) + lr_reg->source = (lrv >> GICH_V2_LR_CPUID_SHIFT) & GICH_V2_LR_CPUID_MASK; } static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) @@ -485,6 +488,10 @@ static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) ((uint32_t)(lr_reg->hw_status & GICH_V2_LR_HW_MASK) << GICH_V2_LR_HW_SHIFT) | ((uint32_t)(lr_reg->grp & GICH_V2_LR_GRP_MASK) << GICH_V2_LR_GRP_SHIFT) ); + if ( lr_reg->eoi ) + lrv |= GICH_V2_LR_MAINTENANCE_IRQ; + if ( lr_reg->virq < NR_GIC_SGI ) + lrv |= (uint32_t)lr_reg->source << GICH_V2_LR_CPUID_SHIFT; writel_gich(lrv, GICH_LR + lr * 4); } diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 8fab458d7f..89a07ae6b4 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -223,9 +223,11 @@ struct gic_lr { /* Virtual IRQ */ uint32_t virq; uint8_t priority; - uint8_t state; - uint8_t hw_status; - uint8_t grp; + uint8_t source; + uint8_t state:2; + uint8_t hw_status:1; + uint8_t grp:1; + uint8_t eoi:1; }; enum gic_version { From patchwork Mon Mar 5 16:03:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130650 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853428lja; Mon, 5 Mar 2018 08:06:53 -0800 (PST) X-Google-Smtp-Source: AG47ELvFVwOdWJZbBTJTv+OYy8GAza75cElyOrJpBmXwm8NYUVz4GEPpwjYqDQCQpIQCsnF+RHTA X-Received: by 10.36.98.21 with SMTP id d21mr14889072itc.1.1520266013320; Mon, 05 Mar 2018 08:06:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266013; cv=none; d=google.com; s=arc-20160816; b=Yiw3YRGMXDsmz6WiFYcPvlO87LAr1r22mFsGVGMrctI8zSwnz3+5OtyCRQOPHNHD8N ZbpWBKy/A15yHyCrPuHpREW2Y6F8sQyXSbIKHpM7nAWxOc5cdxIley8fU0YEOfTC2qtU 7ER/cJjhag38M/zsVmB8e10wUfHShtLS27IcJgkRGhniOlvbj3PdMrlNlYbm5poF1G3O fQ5ezjy6cvaCt495w4dEmVmV6KK974OzndUvOi9pQqNgOUDErjGU2eEw6TPvPmAchaD+ +H+1+0vRm/t+7JNOahJYfUNc5EAYS+ATCJ/QiPU8ZXFyCEVPQ2KEwCcwiu4htolIO2b1 2VZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=RUtoipqEnhL4M/dH1ZXVeIrByEw+Kvhk2lHZ6T96Ztg=; b=nHwq4mkVqtOGjhqw0Shz8/qdJ1KboP3cGY2cfxT4PibKl4MuF8Qsnk3nFXqgbifCwv HFO9pMVhOrHB6Q9zIYIIw0wGFqr21WrVZphg2HvreVe/npd2KoQrTq7nRDYoNt7qGtxh QYxIYu80qx1wbtoZlQiHKVDbxRlL+C16pKvQNvJ0exkVbJ2nPg/JBys6AIjsSLlQE4YU 7Ng6HSml58AGMHxQChLMVv/NbutCwT8XiBxJJ3kQr5mIfOHjOb/si9mutWkvaexJ2TPH t2mMb89ak8sXQszGFB7eVZyW2Dm2cGxGtvhq6p4GvkO0sLkF9I/e0FcrLn114MKpXwso Dr8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=BrBVdEsH; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:44 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:40 +0000 Message-Id: <20180305160415.16760-23-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 22/57] ARM: GIC: Allow tweaking the active and pending state of an IRQ X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" When playing around with hardware mapped, level triggered virtual IRQs, there is the need to explicitly set the active or pending state of an interrupt at some point. To prepare the GIC for that, we introduce a set_active_state() and a set_pending_state() function to let the VGIC manipulate the state of an associated hardware IRQ. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - use struct irq_desc* in the interface (instead of just the IRQ number) - add set_pending_state() (needed later) xen/arch/arm/gic-v2.c | 32 ++++++++++++++++++++++++++++++++ xen/arch/arm/gic-v3.c | 28 ++++++++++++++++++++++++++++ xen/arch/arm/gic.c | 10 ++++++++++ xen/include/asm-arm/gic.h | 10 ++++++++++ 4 files changed, 80 insertions(+) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index c5ec0d4d35..74169b5633 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -241,6 +241,36 @@ static void gicv2_poke_irq(struct irq_desc *irqd, uint32_t offset) writel_gicd(1U << (irqd->irq % 32), offset + (irqd->irq / 32) * 4); } +static void gicv2_set_active_state(struct irq_desc *irqd, bool active) +{ + ASSERT(spin_is_locked(&irqd->lock)); + + if ( active ) + { + set_bit(_IRQ_INPROGRESS, &irqd->status); + gicv2_poke_irq(irqd, GICD_ISACTIVER); + } + else + { + gicv2_poke_irq(irqd, GICD_ICACTIVER); + } +} + +static void gicv2_set_pending_state(struct irq_desc *irqd, bool pending) +{ + ASSERT(spin_is_locked(&irqd->lock)); + + if ( pending ) + { + set_bit(_IRQ_INPROGRESS, &irqd->status); + gicv2_poke_irq(irqd, GICD_ISPENDR); + } + else + { + gicv2_poke_irq(irqd, GICD_ICPENDR); + } +} + static void gicv2_set_irq_type(struct irq_desc *desc, unsigned int type) { uint32_t cfg, actual, edgebit; @@ -1251,6 +1281,8 @@ const static struct gic_hw_operations gicv2_ops = { .eoi_irq = gicv2_eoi_irq, .deactivate_irq = gicv2_dir_irq, .read_irq = gicv2_read_irq, + .set_active_state = gicv2_set_active_state, + .set_pending_state = gicv2_set_pending_state, .set_irq_type = gicv2_set_irq_type, .set_irq_priority = gicv2_set_irq_priority, .send_SGI = gicv2_send_SGI, diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 44dfba2267..c96469f09d 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -477,6 +477,32 @@ static unsigned int gicv3_read_irq(void) return irq; } +static void gicv3_set_active_state(struct irq_desc *irqd, bool active) +{ + ASSERT(spin_is_locked(&irqd->lock)); + + if ( active ) + { + set_bit(_IRQ_INPROGRESS, &irqd->status); + gicv3_poke_irq(irqd, GICD_ISACTIVER, false); + } + else + gicv3_poke_irq(irqd, GICD_ICACTIVER, false); +} + +static void gicv3_set_pending_state(struct irq_desc *irqd, bool pending) +{ + ASSERT(spin_is_locked(&irqd->lock)); + + if ( pending ) + { + set_bit(_IRQ_INPROGRESS, &irqd->status); + gicv3_poke_irq(irqd, GICD_ISPENDR, false); + } + else + gicv3_poke_irq(irqd, GICD_ICPENDR, false); +} + static inline uint64_t gicv3_mpidr_to_affinity(int cpu) { uint64_t mpidr = cpu_logical_map(cpu); @@ -1723,6 +1749,8 @@ static const struct gic_hw_operations gicv3_ops = { .eoi_irq = gicv3_eoi_irq, .deactivate_irq = gicv3_dir_irq, .read_irq = gicv3_read_irq, + .set_active_state = gicv3_set_active_state, + .set_pending_state = gicv3_set_pending_state, .set_irq_type = gicv3_set_irq_type, .set_irq_priority = gicv3_set_irq_priority, .send_SGI = gicv3_send_sgi, diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 968e46fabb..f1329a630a 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -87,6 +87,16 @@ void gic_restore_state(struct vcpu *v) isb(); } +void gic_set_active_state(struct irq_desc *irqd, bool state) +{ + gic_hw_ops->set_active_state(irqd, state); +} + +void gic_set_pending_state(struct irq_desc *irqd, bool state) +{ + gic_hw_ops->set_pending_state(irqd, state); +} + /* desc->irq needs to be disabled before calling this function */ void gic_set_irq_type(struct irq_desc *desc, unsigned int type) { diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 89a07ae6b4..46dcb0fe7c 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -239,6 +239,12 @@ DECLARE_PER_CPU(uint64_t, lr_mask); extern enum gic_version gic_hw_version(void); +/* Force the active state of an IRQ. */ +void gic_set_active_state(struct irq_desc *irqd, bool state); + +/* Force the pending state of an IRQ. */ +void gic_set_pending_state(struct irq_desc *irqd, bool state); + /* Program the IRQ type into the GIC */ void gic_set_irq_type(struct irq_desc *desc, unsigned int type); @@ -348,6 +354,10 @@ struct gic_hw_operations { void (*deactivate_irq)(struct irq_desc *irqd); /* Read IRQ id and Ack */ unsigned int (*read_irq)(void); + /* Force the active state of an IRQ by accessing the distributor */ + void (*set_active_state)(struct irq_desc *irqd, bool state); + /* Force the pending state of an IRQ by accessing the distributor */ + void (*set_pending_state)(struct irq_desc *irqd, bool state); /* Set IRQ type */ void (*set_irq_type)(struct irq_desc *desc, unsigned int type); /* Set IRQ priority */ From patchwork Mon Mar 5 16:03:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130654 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853522lja; Mon, 5 Mar 2018 08:06:57 -0800 (PST) X-Google-Smtp-Source: AG47ELvwpHdCXxfR368VgLzqYbyzghrdDUE+NBqdcN2apLTNP83ap9RBFp9OHOVWKqtYOP/hRVF0 X-Received: by 10.107.88.10 with SMTP id m10mr16221956iob.144.1520266017768; Mon, 05 Mar 2018 08:06:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266017; 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:45 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:41 +0000 Message-Id: <20180305160415.16760-24-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 23/57] ARM: GIC: allow reading pending state of a hardware IRQ X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" To synchronize level triggered interrupts which are mapped into a guest, we need to update the virtual line level at certain points in time. For a hardware mapped interrupt the GIC is the only place where we can easily access this information. Implement a gic_hw_operations member to return the pending state of a particular interrupt. Due to hardware limitations this only works for private interrupts of the current CPU, so there is no CPU field in the prototype. This adds gicv2/3_peek_irq() helper functions, to read a bit in a bitmap spread over several MMIO registers. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - add gicv2/3_peek_irq() helpers - use struct irq_desc* in the interface (instead of just the IRQ number) xen/arch/arm/gic-v2.c | 15 +++++++++++++++ xen/arch/arm/gic-v3.c | 19 +++++++++++++++++++ xen/arch/arm/gic.c | 5 +++++ xen/include/asm-arm/gic.h | 5 +++++ 4 files changed, 44 insertions(+) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 74169b5633..48352f6499 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -241,6 +241,15 @@ static void gicv2_poke_irq(struct irq_desc *irqd, uint32_t offset) writel_gicd(1U << (irqd->irq % 32), offset + (irqd->irq / 32) * 4); } +static bool gicv2_peek_irq(struct irq_desc *irqd, uint32_t offset) +{ + uint32_t reg; + + reg = readl_gicd(offset + (irqd->irq / 32) * 4) & (1U << (irqd->irq % 32)); + + return reg; +} + static void gicv2_set_active_state(struct irq_desc *irqd, bool active) { ASSERT(spin_is_locked(&irqd->lock)); @@ -549,6 +558,11 @@ static unsigned int gicv2_read_apr(int apr_reg) return readl_gich(GICH_APR); } +static bool gicv2_read_pending_state(struct irq_desc *irqd) +{ + return gicv2_peek_irq(irqd, GICD_ISPENDR); +} + static void gicv2_irq_enable(struct irq_desc *desc) { unsigned long flags; @@ -1294,6 +1308,7 @@ const static struct gic_hw_operations gicv2_ops = { .write_lr = gicv2_write_lr, .read_vmcr_priority = gicv2_read_vmcr_priority, .read_apr = gicv2_read_apr, + .read_pending_state = gicv2_read_pending_state, .make_hwdom_dt_node = gicv2_make_hwdom_dt_node, .make_hwdom_madt = gicv2_make_hwdom_madt, .get_hwdom_extra_madt_size = gicv2_get_hwdom_extra_madt_size, diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index c96469f09d..3e75d06c3b 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -444,6 +444,19 @@ static void gicv3_poke_irq(struct irq_desc *irqd, u32 offset, bool wait_for_rwp) gicv3_wait_for_rwp(irqd->irq); } +static bool gicv3_peek_irq(struct irq_desc *irqd, u32 offset) +{ + void __iomem *base; + unsigned int irq = irqd->irq; + + if ( irq >= NR_GIC_LOCAL_IRQS) + base = GICD + (irq / 32) * 4; + else + base = GICD_RDIST_SGI_BASE; + + return !!(readl(base + offset) & (1U << (irq % 32))); +} + static void gicv3_unmask_irq(struct irq_desc *irqd) { gicv3_poke_irq(irqd, GICD_ISENABLER, false); @@ -1094,6 +1107,11 @@ static unsigned int gicv3_read_apr(int apr_reg) } } +static bool gicv3_read_pending_state(struct irq_desc *irqd) +{ + return gicv3_peek_irq(irqd, GICD_ISPENDR); +} + static void gicv3_irq_enable(struct irq_desc *desc) { unsigned long flags; @@ -1762,6 +1780,7 @@ static const struct gic_hw_operations gicv3_ops = { .write_lr = gicv3_write_lr, .read_vmcr_priority = gicv3_read_vmcr_priority, .read_apr = gicv3_read_apr, + .read_pending_state = gicv3_read_pending_state, .secondary_init = gicv3_secondary_cpu_init, .make_hwdom_dt_node = gicv3_make_hwdom_dt_node, .make_hwdom_madt = gicv3_make_hwdom_madt, diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index f1329a630a..67c3b4d86d 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -116,6 +116,11 @@ static void gic_set_irq_priority(struct irq_desc *desc, unsigned int priority) gic_hw_ops->set_irq_priority(desc, priority); } +bool gic_read_pending_state(struct irq_desc *irqd) +{ + return gic_hw_ops->read_pending_state(irqd); +} + /* Program the GIC to route an interrupt to the host (i.e. Xen) * - needs to be called with desc.lock held */ diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 46dcb0fe7c..03667f00cf 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -248,6 +248,9 @@ void gic_set_pending_state(struct irq_desc *irqd, bool state); /* Program the IRQ type into the GIC */ void gic_set_irq_type(struct irq_desc *desc, unsigned int type); +/* Read the pending state of an interrupt from the distributor. */ +bool gic_read_pending_state(struct irq_desc *irqd); + /* Program the GIC to route an interrupt */ extern void gic_route_irq_to_xen(struct irq_desc *desc, unsigned int priority); extern int gic_route_irq_to_guest(struct domain *, unsigned int virq, @@ -382,6 +385,8 @@ struct gic_hw_operations { unsigned int (*read_vmcr_priority)(void); /* Read APRn register */ unsigned int (*read_apr)(int apr_reg); + /* Query the pending state of an interrupt at the distributor level. */ + bool (*read_pending_state)(struct irq_desc *irqd); /* Secondary CPU init */ int (*secondary_init)(void); /* Create GIC node for the hardware domain */ From patchwork Mon Mar 5 16:03:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130651 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853455lja; Mon, 5 Mar 2018 08:06:54 -0800 (PST) X-Google-Smtp-Source: AG47ELtjohtkEa9UXP39UPMRwIRyu3QXmkl+FMtsPz6eY4//N3g27+Lg2HAqgFX8ARtIH4TS1698 X-Received: by 10.107.9.138 with SMTP id 10mr17583423ioj.257.1520266014662; Mon, 05 Mar 2018 08:06:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266014; cv=none; d=google.com; s=arc-20160816; b=hZ5JdqPWQYUubWs7mhEwm+H0QCLi/CVkgQbSSjqUddzGOSOzRf6E5WJNYpVIxeSdoP 1fu4VTV5xf34nkqptpWd2hqc0qheiPMN4nbysUzJNB0Oq7QhYrQIpKNlT8DCcUs9MLf/ Qj1Egf3/2IS8BWpLkPuX0gcuCGStLhBS6gkdCKyLsgOJxJ4bCZnnNllZanh/Q3lq6PlA ctTdxfFUzg9K7Oo/i5JSR1qTbZDx15WhEWOLCSxtd3Ra7Xqn6pXybABN9t4Q8Stn6xyU 5wzAr1z/QuDs9kcoxUY5MNjCa9mddPXRUxGo63RE6+ccjP4xxkwW121ZZAe+3EOoM9qZ us+Q== ARC-Message-Signature: i=1; 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:46 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:42 +0000 Message-Id: <20180305160415.16760-25-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 24/57] ARM: timer: Handle level triggered IRQs correctly X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The ARM Generic Timer uses a level-sensitive interrupt semantic. We easily catch when the line goes high, as this triggers the hardware IRQ. However we have to sync the state of the interrupt condition at certain points to catch when the line goes low and we can remove the vtimer vIRQ from the vGIC (and the LR). The VGIC in Xen so far only implemented edge triggered vIRQs, really, so we need to add new functionality to re-sample the interrupt state. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - extend comments - don't read CNTV_CVAL_EL0 - use symbolic names for constants xen/arch/arm/time.c | 36 ++++++++++++++++++++++++++++++++++++ xen/arch/arm/traps.c | 6 ++++++ xen/include/xen/timer.h | 2 ++ 3 files changed, 44 insertions(+) diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c index c11fcfeadd..c0ae781ecd 100644 --- a/xen/arch/arm/time.c +++ b/xen/arch/arm/time.c @@ -263,6 +263,42 @@ static void vtimer_interrupt(int irq, void *dev_id, struct cpu_user_regs *regs) vgic_inject_irq(current->domain, current, current->arch.virt_timer.irq, true); } +/** + * vtimer_sync() - update the state of the virtual timer after a guest run + * @vcpu: The VCPU to sync the arch timer state + * + * After returning from a guest, update the state of the virtual interrupt + * line, to model the level triggered interrupt correctly. + * If the guest has handled a timer interrupt, the virtual interrupt line + * needs to be lowered explicitly. vgic_inject_irq() takes care of that. + */ +void vtimer_sync(struct vcpu *vcpu) +{ + struct vtimer *vtimer = &vcpu->arch.virt_timer; + uint32_t vtimer_ctl = READ_SYSREG32(CNTV_CTL_EL0); + bool level; + + /* + * Technically the mask should include the CNTx_CTL_MASK bit here, + * to catch if the timer interrupt is masked. However Xen always masks + * the timer upon entering the hypervisor, leaving it up to the guest + * to un-mask it. So we would always read a "low" level, despite the + * condition being actually "high". + * Ignoring the mask bit solves this (for now). + * Another possible check would be to compare the value of CNTVCT_EL0 + * against vtimer->cval and derive the interrupt state from that. + */ + vtimer_ctl &= (CNTx_CTL_ENABLE | CNTx_CTL_PENDING); + level = (vtimer_ctl == (CNTx_CTL_ENABLE | CNTx_CTL_PENDING)); + + /* + * TODO: The proper fix for this is to make vtimer vIRQ hardware mapped, + * but this requires reworking the arch timer to implement this. + */ + + vgic_inject_irq(vcpu->domain, vcpu, vtimer->irq, level); +} + /* * Arch timer interrupt really ought to be level triggered, since the * design of the timer/comparator mechanism is based around that diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 7411bff7a7..0713723bb7 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -2024,6 +2024,12 @@ static void enter_hypervisor_head(struct cpu_user_regs *regs) if ( current->arch.hcr_el2 & HCR_VA ) current->arch.hcr_el2 = READ_SYSREG(HCR_EL2); + /* + * We need to update the state of our emulated devices using level + * triggered interrupts before syncing back the VGIC state. + */ + vtimer_sync(current); + vgic_sync_from_lrs(current); } } diff --git a/xen/include/xen/timer.h b/xen/include/xen/timer.h index 4513260b0d..eddbbf3903 100644 --- a/xen/include/xen/timer.h +++ b/xen/include/xen/timer.h @@ -94,6 +94,8 @@ DECLARE_PER_CPU(s_time_t, timer_deadline); /* Arch-defined function to reprogram timer hardware for new deadline. */ int reprogram_timer(s_time_t timeout); +void vtimer_sync(struct vcpu *vcpu); + /* Calculate the aligned first tick time for a given periodic timer. */ s_time_t align_timer(s_time_t firsttick, uint64_t period); From patchwork Mon Mar 5 16:03:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130649 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853397lja; Mon, 5 Mar 2018 08:06:52 -0800 (PST) X-Google-Smtp-Source: AG47ELvcgu13XbONMaGAv5y1pUoCAbGKAWEthGOU+4weg/TZdGk1vmW58vua1fhZlhtzbga5hhTa X-Received: by 10.107.79.11 with SMTP id d11mr17804728iob.253.1520266011987; Mon, 05 Mar 2018 08:06:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266011; cv=none; d=google.com; s=arc-20160816; b=GzGPgh1SrqgCNm07bqMVx2EWrfOQmReZfEP+URXI5Rs6Otb8e6MHxLxxV7Z5Pl8FiG 9/RxfgRKX2ZuOUYOUrer9iZSMJejpaPUQ1GxBBgL/Hlj2XQVw6AAdaGCR/jtYR3UljEx /Ax8fxfawBxU0wQUFT8eF5+71kCM4jXJTzNEPyz4pxw6Wu3tsuUIiWnqc9cCvGBnU0kG Dz54BfBYIT+CA8amlKndPbYUhppYdidQtsDWO9UF2p4Iv0jCMqM3EbE1H+xl+JJARdMe J8XDSTwy/bdqBxJ83QJGnra5EAAEXz4y+IRlMS5BxruQJy6qQuIrTZBX4qz6S1nxDdsP eKLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=T2WW4Ba9P8hHIq0j9mcWbRdedkGUSWiuMm/L/IQNTAg=; b=hgAhbaywLFpr6zqJVnzr/gheEPJgFYfQMGOmtoWDFbMW/J9F+2zM7gz9jRor7F0ss5 o1XSE3tIzrwZIuknIj8Ng5W9b+XlTZMJYXoD8b6oAKC9UExvIBaR2Tuq0Yhcn4xi4G+N GTo3XMwI1OjYtUNZAyS12yIBpLemZoix24/4CkEOHAv1Jcf854d1wI1SPMKFXUsE7V1R bNvRPjef+cF2ScbuR8+G9mGZMmpqMK7jxaOPalwSq7T13nDcSkA4+cyxTxUdj6J/h9gX GVFMJETnzkvvDRoRI1iguQb2NmtlNDyv7QU2x/FZ7zWgGlQ501bPeISu7cbgMPZ2kbff pwlg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ET82bCbF; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:47 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:43 +0000 Message-Id: <20180305160415.16760-26-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 25/57] ARM: evtchn: Handle level triggered IRQs correctly X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The event channel IRQ has level triggered semantics, however the current VGIC treats everything as edge triggered. To correctly process those IRQs, we have to lower the (virtual) IRQ line at some point in time, depending on whether ther interrupt condition still prevails. Check the per-VCPU evtchn_upcall_pending variable to make the interrupt line match its status, and call this function upon every hypervisor entry. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - no changes xen/arch/arm/domain.c | 7 +++++++ xen/arch/arm/traps.c | 1 + xen/include/asm-arm/event.h | 1 + 3 files changed, 9 insertions(+) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index a7bba3ad44..11a46aa27f 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -955,6 +955,13 @@ void vcpu_mark_events_pending(struct vcpu *v) vgic_inject_irq(v->domain, v, v->domain->arch.evtchn_irq, true); } +void vcpu_update_evtchn_irq(struct vcpu *v) +{ + bool pending = vcpu_info(v, evtchn_upcall_pending); + + vgic_inject_irq(v->domain, v, v->domain->arch.evtchn_irq, pending); +} + /* The ARM spec declares that even if local irqs are masked in * the CPSR register, an irq should wake up a cpu from WFI anyway. * For this reason we need to check for irqs that need delivery, diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 0713723bb7..fcf5db50ae 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -2029,6 +2029,7 @@ static void enter_hypervisor_head(struct cpu_user_regs *regs) * triggered interrupts before syncing back the VGIC state. */ vtimer_sync(current); + vcpu_update_evtchn_irq(current); vgic_sync_from_lrs(current); } diff --git a/xen/include/asm-arm/event.h b/xen/include/asm-arm/event.h index c4c79fa87d..eafb2e7f3e 100644 --- a/xen/include/asm-arm/event.h +++ b/xen/include/asm-arm/event.h @@ -6,6 +6,7 @@ void vcpu_kick(struct vcpu *v); void vcpu_mark_events_pending(struct vcpu *v); +void vcpu_update_evtchn_irq(struct vcpu *v); void vcpu_block_unless_event_pending(struct vcpu *v); static inline int vcpu_event_delivery_is_enabled(struct vcpu *v) From patchwork Mon Mar 5 16:03:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130652 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853479lja; Mon, 5 Mar 2018 08:06:56 -0800 (PST) X-Google-Smtp-Source: AG47ELtJQGqXs8n3NnRPB0Vin7Nmcm8WsOEqWyb6FZCVr2fkPekoaOr0JjkrDje+1d0NPU/ua9ZT X-Received: by 10.36.63.66 with SMTP id d63mr13823998ita.91.1520266015928; Mon, 05 Mar 2018 08:06:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266015; cv=none; d=google.com; s=arc-20160816; b=VaJe3yagkmFJDM5LYQEUpmPXi7iJWUP020vPGxUvvVEczPl/0hNUtqxGNGjqAEZuos WXjq9dhPDTnWMLlDg8r7KV9WntC8PPEDdvQp+jMyv86NxyrF7Yw8mESZtQhfJ3vXNf/k dJFGdNGiswvsA9xxc/DyL4/cpDXar5FksntjXwQYm7my28DiYzQ9fTJ47OzFfJTm0zWW yyWqB7wUPvP93ugCI7oZOhJw5rSZwxuFxkiVa41G69AUB+9x0ySQ1lN1ukmw96fsvsPR yuUKJr/Ybj9VrgfojhDeDMAwL4ogQQ66Occ+kqw6BJ1v/Cq8vTtpF/c5EIVDRCK6PQES b9YA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=dOgkPHHGcVWQjmy7xG6acwOXyrKSgEpZJSfhIMNGoYk=; b=F2klgBRehyl9bi8XoOSMW80uqX7wFPQ8mlwxRqplJu7pycAUfqCD9tYCBeVg5RYs9G Z34CLbyasb1343TQEVeAMUYqg3PzF5X4hjr9ic1QCvaGzseCtn7TZ8GSTNq/O9wVNU7s sNhuo7fFxqvz/pW/bIf8S8KnauVZaDtjiLyeNoPSk/3pI8mnX1KF39nOoUCIsmVYukN9 enCM2bsXrkHanpOmIff3rr+xxyMrCr13ary6NC13h1UfwTGk17jb0g+EgDdmsK/iLYCQ e1kFZEtPLeKELjhIhZKk7eNZX7fclf7kKRlJeWMICpRhmvT/YYpZZYT9QDFnxvVcU8Fo EsSw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=GfQZUf1Z; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:48 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:44 +0000 Message-Id: <20180305160415.16760-27-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 26/57] ARM: vPL011: Use the VGIC's level triggered IRQs handling if available X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The emulated ARM SBSA UART is using level triggered IRQ semantics, however the current VGIC can only handle edge triggered IRQs, really. Disable the existing workaround for this problem in case we have the new VGIC in place, which can properly handle level triggered IRQs. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - no changes xen/arch/arm/vpl011.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/xen/arch/arm/vpl011.c b/xen/arch/arm/vpl011.c index 5dcf4bec18..197ece8873 100644 --- a/xen/arch/arm/vpl011.c +++ b/xen/arch/arm/vpl011.c @@ -54,6 +54,7 @@ static void vpl011_update_interrupt_status(struct domain *d) */ ASSERT(spin_is_locked(&vpl011->lock)); +#ifndef CONFIG_NEW_VGIC /* * TODO: PL011 interrupts are level triggered which means * that interrupt needs to be set/clear instead of being @@ -71,6 +72,9 @@ static void vpl011_update_interrupt_status(struct domain *d) vgic_inject_irq(d, NULL, GUEST_VPL011_SPI, true); vpl011->shadow_uartmis = uartmis; +#else + vgic_inject_irq(d, NULL, GUEST_VPL011_SPI, !!uartmis); +#endif } static uint8_t vpl011_read_data(struct domain *d) From patchwork Mon Mar 5 16:03:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130676 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853854lja; Mon, 5 Mar 2018 08:07:13 -0800 (PST) X-Google-Smtp-Source: AG47ELuieRXkBevKNpftCBlqLnL2cj/l2K0ofweEQKjkFtM3hBxVslZqlLZyT1894MeT+UsaH8N7 X-Received: by 10.36.179.8 with SMTP id e8mr14376291itf.36.1520266033189; Mon, 05 Mar 2018 08:07:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266033; cv=none; d=google.com; s=arc-20160816; b=bKOjBr97GZv7xsO05VuXiyEMk2KMvGSvNGaCuJ3SbrpFevm+lmhX5W1/oX6j3pIEZJ 8X9XdkAqN1tj3u2qMYg/I3hprbNm+AuMggd7w9bxohEhJPqSHQSiYllCzjhznC65qml1 0hfNDE30jgmMJned/W6aS6D8xj670K+9JFdiVjm/BrCOwKVRxAgFDzEA+TDyTxkRJLhQ Uub0I+RxNJ5a6IX9ryIQ+YuQhPWgLjGtXKGtV9SZ04NXnMavzSfDmT5UQlW2cIf4qopF 58Bw3DleU6S3bD8v0nLm8uTJ5q0b7XhRI4xE0IEtvAD/JgDFxTmzFnS8ricvshOAecmO ePdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=S3iil/QUZntbXTR+26/ODRMYokluIxEy3UZTSQ3ruOM=; b=ZhHuuWNtEO1ZwyY3X8Vn7tMOA38pGwbJLneb08tT8WMmAoFHscY2rwQGv6PDKKJtWa aj7GZ/X3N+kSfuy0nRaiKXC2ni6LDG8xLoNXIR6WxpQl4AWwcz17xoEXn9ll0LO9kFc4 zV6gSZs511F22mQVnFPmPoSJ+/TiqbS0XZPTBRsbzowuhAYVLx548c6+MVammFiZ6jMa 35iJEuNr+k+qpTaEdWqR+wWdvx1r2Svmmhwj4MAnvj2vEQZjRsqGZ5CbxoBlNG8kFgIE TlX592wqQMlors6j0PtfNHcXEHa9frFery9bQNh6POLLR3JlG2lZwx1wT4lpbBUgc2L7 iMoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=khYUb46K; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:49 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:45 +0000 Message-Id: <20180305160415.16760-28-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 27/57] ARM: new VGIC: Add data structure definitions X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Add a new header file for the new and improved GIC implementation. The big change is that we now have a struct vgic_irq per IRQ instead of spreading all the information over various bitmaps in the ranks. We include this new header conditionally from within the old header file for the time being to avoid touching all the users. This is based on Linux commit b18b57787f5e, written by Christoffer Dall. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - rename header file to new_vgic.h - drop unneeded data structures (vgic_its, vgic_v_cpu_if) - reorder members in vgic_irq to avoid padding - move flags members into bool bitfields - drop prototypes - use unsigned and uint_t data types - keep arch_vcpu member name as "vgic" xen/include/asm-arm/new_vgic.h | 198 +++++++++++++++++++++++++++++++++++++++++ xen/include/asm-arm/vgic.h | 6 ++ 2 files changed, 204 insertions(+) create mode 100644 xen/include/asm-arm/new_vgic.h diff --git a/xen/include/asm-arm/new_vgic.h b/xen/include/asm-arm/new_vgic.h new file mode 100644 index 0000000000..54be5aa3eb --- /dev/null +++ b/xen/include/asm-arm/new_vgic.h @@ -0,0 +1,198 @@ +/* + * Copyright (C) 2015, 2016 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __ASM_ARM_NEW_VGIC_H +#define __ASM_ARM_NEW_VGIC_H + +#include +#include +#include +#include +#include + +#define VGIC_V3_MAX_CPUS 255 +#define VGIC_V2_MAX_CPUS 8 +#define VGIC_NR_SGIS 16 +#define VGIC_NR_PPIS 16 +#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS) +#define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1) +#define VGIC_MAX_SPI 1019 +#define VGIC_MAX_RESERVED 1023 +#define VGIC_MIN_LPI 8192 + +#define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS) +#define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \ + (irq) <= VGIC_MAX_SPI) + +enum vgic_type { + VGIC_V2, /* Good ol' GICv2 */ + VGIC_V3, /* New fancy GICv3 */ +}; + +#define VGIC_V2_MAX_LRS (1 << 6) +#define VGIC_V3_MAX_LRS 16 +#define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr) + +enum vgic_irq_config { + VGIC_CONFIG_EDGE = 0, + VGIC_CONFIG_LEVEL +}; + +struct vgic_irq { + struct list_head ap_list; + + struct vcpu *vcpu; /* + * SGIs and PPIs: The VCPU + * SPIs and LPIs: The VCPU whose ap_list + * this is queued on. + */ + + struct vcpu *target_vcpu; /* + * The VCPU that this interrupt should + * be sent to, as a result of the + * targets reg (v2) or the affinity reg (v3). + */ + + spinlock_t irq_lock; /* Protects the content of the struct */ + uint32_t intid; /* Guest visible INTID */ + atomic_t refcount; /* Used for LPIs */ + uint32_t hwintid; /* HW INTID number */ + union + { + struct { + uint8_t targets; /* GICv2 target VCPUs mask */ + uint8_t source; /* GICv2 SGIs only */ + }; + uint32_t mpidr; /* GICv3 target VCPU */ + }; + uint8_t priority; + bool line_level:1; /* Level only */ + bool pending_latch:1; /* + * The pending latch state used to + * calculate the pending state for both + * level and edge triggered IRQs. + */ + bool active:1; /* not used for LPIs */ + bool enabled:1; + bool hw:1; /* Tied to HW IRQ */ + bool config:1; /* Level or edge */ + struct list_head lpi_list; /* Used to link all LPIs together */ +}; + +struct vgic_register_region; + +enum iodev_type { + IODEV_DIST, + IODEV_REDIST, +}; + +struct vgic_io_device { + gfn_t base_fn; + struct vcpu *redist_vcpu; + const struct vgic_register_region *regions; + enum iodev_type iodev_type; + unsigned int nr_regions; +}; + +struct vgic_dist { + bool ready; + bool initialized; + + /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */ + uint32_t version; + + /* Do injected MSIs require an additional device ID? */ + bool msis_require_devid; + + unsigned int nr_spis; + + /* base addresses in guest physical address space: */ + paddr_t vgic_dist_base; /* distributor */ + union + { + /* either a GICv2 CPU interface */ + paddr_t vgic_cpu_base; + /* or a number of GICv3 redistributor regions */ + struct + { + paddr_t vgic_redist_base; + paddr_t vgic_redist_free_offset; + }; + }; + + /* distributor enabled */ + bool enabled; + + struct vgic_irq *spis; + unsigned long *allocated_irqs; /* bitmap of IRQs allocated */ + + struct vgic_io_device dist_iodev; + + bool has_its; + + /* + * Contains the attributes and gpa of the LPI configuration table. + * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share + * one address across all redistributors. + * GICv3 spec: 6.1.2 "LPI Configuration tables" + */ + uint64_t propbaser; + + /* Protects the lpi_list and the count value below. */ + spinlock_t lpi_list_lock; + struct list_head lpi_list_head; + unsigned int lpi_list_count; +}; + +struct vgic_cpu { + struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS]; + + struct list_head ap_list_head; + spinlock_t ap_list_lock; /* Protects the ap_list */ + + unsigned int used_lrs; + + /* + * List of IRQs that this VCPU should consider because they are either + * Active or Pending (hence the name; AP list), or because they recently + * were one of the two and need to be migrated off this list to another + * VCPU. + */ + + /* + * Members below are used with GICv3 emulation only and represent + * parts of the redistributor. + */ + struct vgic_io_device rd_iodev; + struct vgic_io_device sgi_iodev; + + /* Contains the attributes and gpa of the LPI pending tables. */ + uint64_t pendbaser; + + bool lpis_enabled; + + /* Cache guest priority bits */ + uint32_t num_pri_bits; + + /* Cache guest interrupt ID bits */ + uint32_t num_id_bits; +}; + +#define vgic_initialized(k) ((k)->arch.vgic.initialized) +#define vgic_ready(k) ((k)->arch.vgic.ready) +#define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \ + ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS)) + +#endif /* __ASM_ARM_NEW_VGIC_H */ diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 84d82e6eb3..b28b8f8df7 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -18,6 +18,10 @@ #ifndef __ASM_ARM_VGIC_H__ #define __ASM_ARM_VGIC_H__ +#ifdef CONFIG_NEW_VGIC +#include +#else + #include #include #include @@ -299,6 +303,8 @@ extern bool vgic_to_sgi(struct vcpu *v, register_t sgir, const struct sgi_target *target); extern bool vgic_migrate_irq(struct vcpu *old, struct vcpu *new, unsigned int irq); +#endif /* !CONFIG_NEW_VGIC */ + /*** Common VGIC functions used by Xen arch code ****/ /* From patchwork Mon Mar 5 16:03:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130671 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853780lja; Mon, 5 Mar 2018 08:07:10 -0800 (PST) X-Google-Smtp-Source: AG47ELvJ3f+h/vT+PLPa/DyrkAJgF2edLsfgsnwfJfK5XZzoTK7KIPIZ7a8yH6SsU+LI+jE3LY93 X-Received: by 10.107.82.1 with SMTP id g1mr18730192iob.203.1520266029904; Mon, 05 Mar 2018 08:07:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266029; cv=none; d=google.com; s=arc-20160816; b=bvj1uzbIXa7yH3rzVsvKA+s8mPK7HeOOJtMfnRBUb5VHrIWnvrSbvpsI8boJa/POdP Qxa6rl2dU57yCim1Xb28aMklErASlTMGXQ1YiWoPt5rAJfexLobelN9syPneV1l+HwPX v3oNNvNWpt0Z1+BoDR5gHWdcAZ+6SpdpfXqsr/KpoA+gMKhAfw01h5Q5CIgHChVOE5jb xpL0LbNLvlOiDl0IOalt3vv60pRO6TxbgVMnDVHY0soVLj3RsOpcMGW9gLtt0OborXXL Cc6NcqUn4foQjWcVIlyFD5v7RhdnUsrivZ54nynGVvx6GSSSO9iep/GSFguAGX7OwWjf dX1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=pdkuV7armqpSaYl7PlDZxdzHqnRWCcvWbNPd8yOlGAM=; b=FXWhDkuz6RiizalxKR9dhmQmhmvwKWEMuI8r6rArQJ6H3qvmfcuNWv+NL9Q+ZOyQ1f bkiqXH6jzDig7EURyvynaN+5qtGhFYTZ/90a/G5yy9VZ/k0wHLlbuslb0sy6PU7JKalq RIFX4jbnqlom3kqPWTu4xYs3yQ3HN4urSenpBeGPj81marO0zn0rgsfpwVt2YDeNZ1ps CVz33oubeYXc/tSDhcmoZfIlx1oQFp59hhN5BOKbG66wa4V0+ekAfpmzXFspulKn6NWF kPJd5aba+RQEM3BsJeP2YmgU/dkigPeBhuaFBitdmAT8mkStOOTkJlc0GbRnYcNmJ7Mc ZrFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=MOw37BmV; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:50 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:46 +0000 Message-Id: <20180305160415.16760-29-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 28/57] ARM: new VGIC: Add acccessor to new struct vgic_irq instance X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The new VGIC implementation centers around a struct vgic_irq instance per virtual IRQ. Provide a function to retrieve the right instance for a given IRQ number and (in case of private interrupts) the right VCPU. This also includes the corresponding put function, which does nothing for private interrupts and SPIs, but handles the ref-counting for LPIs. This is based on Linux commit 64a959d66e47, written by Christoffer Dall. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - add kernel-doc comments to exported functions - adapt to previous changes (new_vgic.h, arch_vcpu member name) - use ASSERT_UNREACHABLE xen/arch/arm/vgic/vgic.c | 124 +++++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic.h | 41 ++++++++++++++++ 2 files changed, 165 insertions(+) create mode 100644 xen/arch/arm/vgic/vgic.c create mode 100644 xen/arch/arm/vgic/vgic.h diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c new file mode 100644 index 0000000000..ace30f78d0 --- /dev/null +++ b/xen/arch/arm/vgic/vgic.c @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2015, 2016 ARM Ltd. + * Imported from Linux ("new" KVM VGIC) and heavily adapted to Xen. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include + +#include "vgic.h" + +/* + * Iterate over the VM's list of mapped LPIs to find the one with a + * matching interrupt ID and return a reference to the IRQ structure. + */ +static struct vgic_irq *vgic_get_lpi(struct domain *d, u32 intid) +{ + struct vgic_dist *dist = &d->arch.vgic; + struct vgic_irq *irq = NULL; + + spin_lock(&dist->lpi_list_lock); + + list_for_each_entry( irq, &dist->lpi_list_head, lpi_list ) + { + if ( irq->intid != intid ) + continue; + + /* + * This increases the refcount, the caller is expected to + * call vgic_put_irq() later once it's finished with the IRQ. + */ + vgic_get_irq_kref(irq); + goto out_unlock; + } + irq = NULL; + +out_unlock: + spin_unlock(&dist->lpi_list_lock); + + return irq; +} + +/** + * vgic_get_irq() - obtain a reference to a virtual IRQ + * @d: The domain the virtual IRQ belongs to. + * @vcpu: For private IRQs (SGIs, PPIs) the virtual CPU this IRQ + * is associated with. Will be ignored for SPIs and LPIs. + * @intid: The virtual IRQ number. + * + * This looks up the virtual interrupt ID to get the corresponding + * struct vgic_irq. It also increases the refcount, so any caller is expected + * to call vgic_put_irq() once it's finished with this IRQ. + * + * Return: The pointer to the requested struct vgic_irq. + */ +struct vgic_irq *vgic_get_irq(struct domain *d, struct vcpu *vcpu, + u32 intid) +{ + /* SGIs and PPIs */ + if ( intid <= VGIC_MAX_PRIVATE ) + return &vcpu->arch.vgic.private_irqs[intid]; + + /* SPIs */ + if ( intid <= VGIC_MAX_SPI ) + return &d->arch.vgic.spis[intid - VGIC_NR_PRIVATE_IRQS]; + + /* LPIs */ + if ( intid >= VGIC_MIN_LPI ) + return vgic_get_lpi(d, intid); + + ASSERT_UNREACHABLE(); +} + +/** + * vgic_put_irq() - drop the reference to a virtual IRQ + * @d: The domain the virtual IRQ belongs to. + * @irq: The pointer to struct vgic_irq, as obtained from vgic_get_irq(). + * + * This drops the reference to a virtual IRQ. It decreases the refcount + * of the pointer, so dynamic IRQs can be freed when no longer needed. + * This should always be called after a vgic_get_irq(), though the reference + * can be deliberately held for longer periods, if needed. + */ +void vgic_put_irq(struct domain *d, struct vgic_irq *irq) +{ + struct vgic_dist *dist = &d->arch.vgic; + + if ( irq->intid < VGIC_MIN_LPI ) + return; + + spin_lock(&dist->lpi_list_lock); + if ( !atomic_dec_and_test(&irq->refcount) ) + { + spin_unlock(&dist->lpi_list_lock); + return; + }; + + list_del(&irq->lpi_list); + dist->lpi_list_count--; + spin_unlock(&dist->lpi_list_lock); + + xfree(irq); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h new file mode 100644 index 0000000000..a3befd386b --- /dev/null +++ b/xen/arch/arm/vgic/vgic.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2015, 2016 ARM Ltd. + * Imported from Linux ("new" KVM VGIC) and heavily adapted to Xen. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __XEN_ARM_VGIC_VGIC_H__ +#define __XEN_ARM_VGIC_VGIC_H__ + +struct vgic_irq *vgic_get_irq(struct domain *d, struct vcpu *vcpu, + u32 intid); +void vgic_put_irq(struct domain *d, struct vgic_irq *irq); + +static inline void vgic_get_irq_kref(struct vgic_irq *irq) +{ + if ( irq->intid < VGIC_MIN_LPI ) + return; + + atomic_inc(&irq->refcount); +} + +#endif + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Mon Mar 5 16:03:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130669 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853743lja; Mon, 5 Mar 2018 08:07:08 -0800 (PST) X-Google-Smtp-Source: AG47ELukhuhCgN9sHcQAG906b9PbjJHphJ824pKCyG36yszZYJAKcnt8QTRCi9hfL/3v6NujB/Xq X-Received: by 10.107.192.131 with SMTP id q125mr17300745iof.184.1520266028037; Mon, 05 Mar 2018 08:07:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266028; cv=none; d=google.com; s=arc-20160816; b=ZyMl1gv0KfZeL8vVx6j7Kwl3cdQuus0gtiNoEtqch9Ev+g29BrnmRllfe/VKCrG1YI lbVuWma+TO5NEV8FLoPYBN4zLMEiSQxewUWJDwa4zJ0O1OV1efZ+Rnt5kuAXrKPqXMSA 0SvQ8sUdmYg5iu9Hb99l/dUZObg7XDUo/Y3x35FnBXj1XN3Ah4+hVyewonMWI8pO8TfD +FIOhmeFLNum+TUlZz67VtCTYARElUyzpK9hXRaDM8G/1FQ+9QlOTZADF7lB50HWM/YL DpNLS1kzxrUjeD5Zh3KF9k37ksvP5XHvaR4P05almdCGc7j4X2NmVKI92Aeofpt968e2 Oecg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=ieutfrESO8Ix7GXcHny7evdo/ENkmfjNMoAVgXtRNAI=; b=KXTo8kT+qLSTvrEu3oDyIiGJKz99mlPNca4RQcWt9mWNNeUXYzj/EwxubfjHspNZRh +xzR+lHh/MpHK4QThyvQiK69tXWnM9mFBo3YwLXMoO1PlH/40w0fs9ORJmuFtFXJdDdi y0kaYWP5J3AlrM7aOVvrAIZIHcIbYkdT4+ry/V34LZ6jzBY3fmzRAwfy8aw+3FD83hvT CUxB3y8IhhUTnZarTEtYJQjIpdut6C4ngIyXkjQkT/nFjnbmGVbaI0QWtDpwR5LgZ58a xAryjxS2Qlak9Cbym/7s4/scksdivGxXHDCdwTlMcFLud13wP6OHH6lAFJlTNh6ArPwK ZiOg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=D1x6jShY; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:51 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:47 +0000 Message-Id: <20180305160415.16760-30-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 29/57] ARM: new VGIC: Implement virtual IRQ injection X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Provide a vgic_queue_irq_unlock() function which decides whether a given IRQ needs to be queued to a VCPU's ap_list. This should be called whenever an IRQ becomes pending or enabled, either as a result of a hardware IRQ injection, from devices emulated by Xen (like the architected timer) or from MMIO accesses to the distributor emulation. Also provides the necessary functions to allow to inject an IRQ to a guest. Since this is the first code that starts using our locking mechanism, we add some (hopefully) clear documentation of our locking strategy and requirements along with this patch. This is based on Linux commit 81eeb95ddbab, written by Christoffer Dall. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - fix locking order comment - adapt to former changes - extend comments - use kick_vcpu() xen/arch/arm/vgic/vgic.c | 227 +++++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic.h | 10 +++ 2 files changed, 237 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index ace30f78d0..ae922815bd 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -21,6 +21,31 @@ #include "vgic.h" +/* + * Locking order is always: + * vgic->lock + * vgic_cpu->ap_list_lock + * vgic->lpi_list_lock + * desc->lock + * vgic_irq->irq_lock + * + * If you need to take multiple locks, always take the upper lock first, + * then the lower ones, e.g. first take the ap_list_lock, then the irq_lock. + * If you are already holding a lock and need to take a higher one, you + * have to drop the lower ranking lock first and re-acquire it after having + * taken the upper one. + * + * When taking more than one ap_list_lock at the same time, always take the + * lowest numbered VCPU's ap_list_lock first, so: + * vcpuX->vcpu_id < vcpuY->vcpu_id: + * spin_lock(vcpuX->arch.vgic.ap_list_lock); + * spin_lock(vcpuY->arch.vgic.ap_list_lock); + * + * Since the VGIC must support injecting virtual interrupts from ISRs, we have + * to use the spin_lock_irqsave/spin_unlock_irqrestore versions of outer + * spinlocks for any lock that may be taken while injecting an interrupt. + */ + /* * Iterate over the VM's list of mapped LPIs to find the one with a * matching interrupt ID and return a reference to the IRQ structure. @@ -114,6 +139,208 @@ void vgic_put_irq(struct domain *d, struct vgic_irq *irq) xfree(irq); } +/** + * vgic_target_oracle() - compute the target vcpu for an irq + * @irq: The irq to route. Must be already locked. + * + * Based on the current state of the interrupt (enabled, pending, + * active, vcpu and target_vcpu), compute the next vcpu this should be + * given to. Return NULL if this shouldn't be injected at all. + * + * Requires the IRQ lock to be held. + * + * Returns: The pointer to the virtual CPU this interrupt should be injected + * to. Will be NULL if this IRQ does not need to be injected. + */ +static struct vcpu *vgic_target_oracle(struct vgic_irq *irq) +{ + ASSERT(spin_is_locked(&irq->irq_lock)); + + /* If the interrupt is active, it must stay on the current vcpu */ + if ( irq->active ) + return irq->vcpu ? : irq->target_vcpu; + + /* + * If the IRQ is not active but enabled and pending, we should direct + * it to its configured target VCPU. + * If the distributor is disabled, pending interrupts shouldn't be + * forwarded. + */ + if ( irq->enabled && irq_is_pending(irq) ) + { + if ( unlikely(irq->target_vcpu && + !irq->target_vcpu->domain->arch.vgic.enabled) ) + return NULL; + + return irq->target_vcpu; + } + + /* + * If neither active nor pending and enabled, then this IRQ should not + * be queued to any VCPU. + */ + return NULL; +} + +/* + * Only valid injection if changing level for level-triggered IRQs or for a + * rising edge. + */ +static bool vgic_validate_injection(struct vgic_irq *irq, bool level) +{ + if ( irq->config == VGIC_CONFIG_LEVEL ) + return irq->line_level != level; + + return level; +} + +/** + * vgic_queue_irq_unlock() - Queue an IRQ to a VCPU, to be injected to a guest. + * @d: The domain the virtual IRQ belongs to. + * @irq: A pointer to the vgic_irq of the virtual IRQ, with the lock held. + * @flags: The flags used when having grabbed the IRQ lock. + * + * Check whether an IRQ needs to (and can) be queued to a VCPU's ap list. + * Do the queuing if necessary, taking the right locks in the right order. + * + * Needs to be entered with the IRQ lock already held, but will return + * with all locks dropped. + * + * Returns: True when the IRQ was queued, false otherwise. + */ +void vgic_queue_irq_unlock(struct domain *d, struct vgic_irq *irq, + unsigned long flags) +{ + struct vcpu *vcpu; + + ASSERT(spin_is_locked(&irq->irq_lock)); + +retry: + vcpu = vgic_target_oracle(irq); + if ( irq->vcpu || !vcpu ) + { + /* + * If this IRQ is already on a VCPU's ap_list, then it + * cannot be moved or modified and there is no more work for + * us to do. + * + * Otherwise, if the irq is not pending and enabled, it does + * not need to be inserted into an ap_list and there is also + * no more work for us to do. + */ + spin_unlock_irqrestore(&irq->irq_lock, flags); + + /* + * We have to kick the VCPU here, because we could be + * queueing an edge-triggered interrupt for which we + * get no EOI maintenance interrupt. In that case, + * while the IRQ is already on the VCPU's AP list, the + * VCPU could have EOI'ed the original interrupt and + * won't see this one until it exits for some other + * reason. + */ + if ( vcpu ) + kick_vcpu(vcpu); + + return; + } + + /* + * We must unlock the irq lock to take the ap_list_lock where + * we are going to insert this new pending interrupt. + */ + spin_unlock_irqrestore(&irq->irq_lock, flags); + + /* someone can do stuff here, which we re-check below */ + + spin_lock_irqsave(&vcpu->arch.vgic.ap_list_lock, flags); + spin_lock(&irq->irq_lock); + + /* + * Did something change behind our backs? + * + * There are two cases: + * 1) The irq lost its pending state or was disabled behind our + * backs and/or it was queued to another VCPU's ap_list. + * 2) Someone changed the affinity on this irq behind our + * backs and we are now holding the wrong ap_list_lock. + * + * In both cases, drop the locks and retry. + */ + + if ( unlikely(irq->vcpu || vcpu != vgic_target_oracle(irq)) ) + { + spin_unlock(&irq->irq_lock); + spin_unlock_irqrestore(&vcpu->arch.vgic.ap_list_lock, flags); + + spin_lock_irqsave(&irq->irq_lock, flags); + goto retry; + } + + /* + * Grab a reference to the irq to reflect the fact that it is + * now in the ap_list. + */ + vgic_get_irq_kref(irq); + list_add_tail(&irq->ap_list, &vcpu->arch.vgic.ap_list_head); + irq->vcpu = vcpu; + + spin_unlock(&irq->irq_lock); + spin_unlock_irqrestore(&vcpu->arch.vgic.ap_list_lock, flags); + + kick_vcpu(vcpu); + + return; +} + +/** + * vgic_inject_irq() - Inject an IRQ from a device to the vgic + * @d: The domain pointer + * @vcpu: The vCPU for private IRQs (PPIs, SGIs). Ignored for SPIs and LPIs. + * @intid: The INTID to inject a new state to. + * @level: Edge-triggered: true: to trigger the interrupt + * false: to ignore the call + * Level-sensitive true: raise the input signal + * false: lower the input signal + * + * Injects an instance of the given virtual IRQ into a domain. + * The VGIC is not concerned with devices being active-LOW or active-HIGH for + * level-sensitive interrupts. You can think of the level parameter as 1 + * being HIGH and 0 being LOW and all devices being active-HIGH. + * + * Return: A negative error code if the injection failed, or 0 on success. + */ +int vgic_inject_irq(struct domain *d, struct vcpu *vcpu, unsigned int intid, + bool level) +{ + struct vgic_irq *irq; + unsigned long flags; + + irq = vgic_get_irq(d, vcpu, intid); + if ( !irq ) + return -EINVAL; + + spin_lock_irqsave(&irq->irq_lock, flags); + + if ( !vgic_validate_injection(irq, level) ) + { + /* Nothing to see here, move along... */ + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(d, irq); + return 0; + } + + if ( irq->config == VGIC_CONFIG_LEVEL ) + irq->line_level = level; + else + irq->pending_latch = true; + + vgic_queue_irq_unlock(d, irq, flags); + vgic_put_irq(d, irq); + + return 0; +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index a3befd386b..3430955d9f 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -17,9 +17,19 @@ #ifndef __XEN_ARM_VGIC_VGIC_H__ #define __XEN_ARM_VGIC_VGIC_H__ +static inline bool irq_is_pending(struct vgic_irq *irq) +{ + if ( irq->config == VGIC_CONFIG_EDGE ) + return irq->pending_latch; + else + return irq->pending_latch || irq->line_level; +} + struct vgic_irq *vgic_get_irq(struct domain *d, struct vcpu *vcpu, u32 intid); void vgic_put_irq(struct domain *d, struct vgic_irq *irq); +void vgic_queue_irq_unlock(struct domain *d, struct vgic_irq *irq, + unsigned long flags); static inline void vgic_get_irq_kref(struct vgic_irq *irq) { From patchwork Mon Mar 5 16:03:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130658 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853600lja; Mon, 5 Mar 2018 08:07:01 -0800 (PST) X-Google-Smtp-Source: AG47ELuQ5SxFRDVXLBqAwmM53J+AUnCG42t+TpuQL5sLlBboo9lxgyvDfSZY/f+520urLfGDF1ct X-Received: by 10.36.39.86 with SMTP id g83mr15142264ita.28.1520266021735; Mon, 05 Mar 2018 08:07:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266021; cv=none; d=google.com; s=arc-20160816; b=vrpCUD87xHThtB8qowmRcPWOlAhY0//+Ckqu2I3WnGN33bYqdFpWoovXtrNw73JiaE b0YQp9C3vW/vs5eunmJJ5he10gipMAJD0ajfa2FDimxCxACBKK+yrjcsBuYluSG8LiY5 4kPRwJFM1+rTBz6k6D4PTLNqJGs34qPrNPMqP7AN6e6FojDOXlc0dHGiV8qAfv5RK272 OjaMaQhXAEzffSeajJl03PtKILB6QQiQ+GCAgO81ZiK/OmeN7KX2toVum3yzn/1t/ArI PQzc1PcG50z3TM14TR6A8JPDY4an3NIAi9V94w+KgHLs01p25hnwPJQnH1LJeogIiF0K vOkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=cv2Xb1VRk3StI5YXS57eqQnQYsV7vBhcPUbzsWK5eUM=; b=mv084XN4or1h0MRMmi6RJPB8snkKYolAE4UMvehlT5NUsyXiSY6K8RYhfcq+jLw0/S n43aT8X7XF/N1RRCi371dyxPN0By2xBO+U6fFdVeFD0awf/Hy5tMZ70oKuPRHtCmsMm4 Nu8q6VZekF7eTwSs1LGjdHpwWkZgI1um7fqz9iAScBR1jCgm8QGocrllL8+e9epuxtX4 wSe3SE5t24Gsnm/IDRYVlyqKqSNgzIkTI2ctbzWhtOuXH40ADIa1IVksmQSFxGJOOvtr GDlLLQTJykrvh5CtSiINnrBuZbypxneyIA9qgBX50A9rV1Nt06w5HSjeqi86eAHSU2Nw RQcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=kMqEfKDE; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id f203si5869819itb.0.2018.03.05.08.07.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Mar 2018 08:07:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=kMqEfKDE; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1essbf-0007xK-4k; Mon, 05 Mar 2018 16:04:55 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1essbe-0007wc-UP for xen-devel@lists.xenproject.org; Mon, 05 Mar 2018 16:04:54 +0000 X-Inumbo-ID: c9ab76fb-208e-11e8-ba59-bc764e045a96 Received: from mail-wr0-x242.google.com (unknown [2a00:1450:400c:c0c::242]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id c9ab76fb-208e-11e8-ba59-bc764e045a96; Mon, 05 Mar 2018 17:03:48 +0100 (CET) Received: by mail-wr0-x242.google.com with SMTP id v65so17818036wrc.11 for ; Mon, 05 Mar 2018 08:04:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pRKoe//6FsKFOPzCykYK1wkQdgkYCobMexw0flyLj3A=; b=kMqEfKDE30Ukwl0vQa8BNQho1sRdjFFnXdTM5yrcP6BhRsqECfMwqTzBMYHaGr8LOs FeCdLnGTkQD4uxg09O/vhLBlSjD8sZqGWvJHBzAUon1R9AYDatMU//1LfP55QZ+M1ZPN yjhlkhRYpqNt1q1L40oqBnUcvOOrGhJYuKA6g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pRKoe//6FsKFOPzCykYK1wkQdgkYCobMexw0flyLj3A=; b=AQPFmgCm+Ob9ohtevKjocJj7dnlCCKR1fyHCELdDwx9iOZOCvtrMaC9qJpLHk5LbT0 Bw8MA+M2mwzRCVNkBED4m/JIAqbegXEWvekrHzPMBeEsUv/w/BG24m33a/mfo43QjO/d 8gC/iZXXgHfAQma+u+bpQCkmtE6e3MIX0jS0ahoWVIW7cf089KAga4LqdKifiRMMHG+J Z7GoCt9q95aCo0B5ST5iyH87EbZjLCWuBqOEp01Nm6I2kL79qrCBiiIc/vumHbiH4vKg fj+JvHXms12Bk1DSSmm8thT7m5pJa0t4TxGVlSE2fEIcRn4HDKJq9DL2yEzpv4e3vtPm QPsA== X-Gm-Message-State: APf1xPDSgF+9/MD2e1Fsjqm+dvmfBUWit6a/+HoVFKqXiAM2dbfqTK9M KVZcHSXRz16FMGztcHfP+S6n/w== X-Received: by 10.223.136.164 with SMTP id f33mr12893546wrf.77.1520265892635; Mon, 05 Mar 2018 08:04:52 -0800 (PST) Received: from e104803-lin.lan (mail.andrep.de. [217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:52 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:48 +0000 Message-Id: <20180305160415.16760-31-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 30/57] ARM: new VGIC: Add IRQ sorting X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Adds the sorting function to cover the case where you have more IRQs to consider than you have LRs. We consider their priorities. This pulls in Linux' list_sort.c, which is a merge sort implementation for linked lists. Apart from adding a full featured license header and adjusting the #include file, nothing has been changed in this code. This is based on Linux commit 8e4447457965, written by Christoffer Dall. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - use Linux coding style for list_sort.c xen/arch/arm/vgic/vgic.c | 59 +++++++++++++++++ xen/common/list_sort.c | 157 ++++++++++++++++++++++++++++++++++++++++++++ xen/include/xen/list_sort.h | 11 ++++ 3 files changed, 227 insertions(+) create mode 100644 xen/common/list_sort.c create mode 100644 xen/include/xen/list_sort.h diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index ae922815bd..efa6c67cb7 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -17,6 +17,7 @@ #include #include +#include #include #include "vgic.h" @@ -182,6 +183,64 @@ static struct vcpu *vgic_target_oracle(struct vgic_irq *irq) return NULL; } +/* + * The order of items in the ap_lists defines how we'll pack things in LRs as + * well, the first items in the list being the first things populated in the + * LRs. + * + * A hard rule is that active interrupts can never be pushed out of the LRs + * (and therefore take priority) since we cannot reliably trap on deactivation + * of IRQs and therefore they have to be present in the LRs. + * + * Otherwise things should be sorted by the priority field and the GIC + * hardware support will take care of preemption of priority groups etc. + * + * Return negative if "a" sorts before "b", 0 to preserve order, and positive + * to sort "b" before "a". + */ +static int vgic_irq_cmp(void *priv, struct list_head *a, struct list_head *b) +{ + struct vgic_irq *irqa = container_of(a, struct vgic_irq, ap_list); + struct vgic_irq *irqb = container_of(b, struct vgic_irq, ap_list); + bool penda, pendb; + int ret; + + spin_lock(&irqa->irq_lock); + spin_lock(&irqb->irq_lock); + + if ( irqa->active || irqb->active ) + { + ret = (int)irqb->active - (int)irqa->active; + goto out; + } + + penda = irqa->enabled && irq_is_pending(irqa); + pendb = irqb->enabled && irq_is_pending(irqb); + + if ( !penda || !pendb ) + { + ret = (int)pendb - (int)penda; + goto out; + } + + /* Both pending and enabled, sort by priority */ + ret = irqa->priority - irqb->priority; +out: + spin_unlock(&irqb->irq_lock); + spin_unlock(&irqa->irq_lock); + return ret; +} + +/* Must be called with the ap_list_lock held */ +static void vgic_sort_ap_list(struct vcpu *vcpu) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic; + + ASSERT(spin_is_locked(&vgic_cpu->ap_list_lock)); + + list_sort(NULL, &vgic_cpu->ap_list_head, vgic_irq_cmp); +} + /* * Only valid injection if changing level for level-triggered IRQs or for a * rising edge. diff --git a/xen/common/list_sort.c b/xen/common/list_sort.c new file mode 100644 index 0000000000..af2b2f6519 --- /dev/null +++ b/xen/common/list_sort.c @@ -0,0 +1,157 @@ +/* + * list_sort.c: merge sort implementation for linked lists + * Copied from the Linux kernel (lib/list_sort.c) + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; If not, see . + */ + +#include +#include + +#define MAX_LIST_LENGTH_BITS 20 + +/* + * Returns a list organized in an intermediate format suited + * to chaining of merge() calls: null-terminated, no reserved or + * sentinel head node, "prev" links not maintained. + */ +static struct list_head *merge(void *priv, + int (*cmp)(void *priv, struct list_head *a, + struct list_head *b), + struct list_head *a, struct list_head *b) +{ + struct list_head head, *tail = &head; + + while (a && b) { + /* if equal, take 'a' -- important for sort stability */ + if ((*cmp)(priv, a, b) <= 0) { + tail->next = a; + a = a->next; + } else { + tail->next = b; + b = b->next; + } + tail = tail->next; + } + tail->next = a?:b; + return head.next; +} + +/* + * Combine final list merge with restoration of standard doubly-linked + * list structure. This approach duplicates code from merge(), but + * runs faster than the tidier alternatives of either a separate final + * prev-link restoration pass, or maintaining the prev links + * throughout. + */ +static void merge_and_restore_back_links(void *priv, + int (*cmp)(void *priv, struct list_head *a, + struct list_head *b), + struct list_head *head, + struct list_head *a, struct list_head *b) +{ + struct list_head *tail = head; + u8 count = 0; + + while (a && b) { + /* if equal, take 'a' -- important for sort stability */ + if ((*cmp)(priv, a, b) <= 0) { + tail->next = a; + a->prev = tail; + a = a->next; + } else { + tail->next = b; + b->prev = tail; + b = b->next; + } + tail = tail->next; + } + tail->next = a ? : b; + + do { + /* + * In worst cases this loop may run many iterations. + * Continue callbacks to the client even though no + * element comparison is needed, so the client's cmp() + * routine can invoke cond_resched() periodically. + */ + if (unlikely(!(++count))) + (*cmp)(priv, tail->next, tail->next); + + tail->next->prev = tail; + tail = tail->next; + } while (tail->next); + + tail->next = head; + head->prev = tail; +} + +/** + * list_sort - sort a list + * @priv: private data, opaque to list_sort(), passed to @cmp + * @head: the list to sort + * @cmp: the elements comparison function + * + * This function implements "merge sort", which has O(nlog(n)) + * complexity. + * + * The comparison function @cmp must return a negative value if @a + * should sort before @b, and a positive value if @a should sort after + * @b. If @a and @b are equivalent, and their original relative + * ordering is to be preserved, @cmp must return 0. + */ +void list_sort(void *priv, struct list_head *head, + int (*cmp)(void *priv, struct list_head *a, + struct list_head *b)) +{ + struct list_head *part[MAX_LIST_LENGTH_BITS+1]; /* sorted partial lists + -- last slot is a sentinel */ + int lev; /* index into part[] */ + int max_lev = 0; + struct list_head *list; + + if (list_empty(head)) + return; + + memset(part, 0, sizeof(part)); + + head->prev->next = NULL; + list = head->next; + + while (list) { + struct list_head *cur = list; + list = list->next; + cur->next = NULL; + + for (lev = 0; part[lev]; lev++) { + cur = merge(priv, cmp, part[lev], cur); + part[lev] = NULL; + } + if (lev > max_lev) { + if (unlikely(lev >= ARRAY_SIZE(part)-1)) { + dprintk(XENLOG_DEBUG, + "list too long for efficiency\n"); + lev--; + } + max_lev = lev; + } + part[lev] = cur; + } + + for (lev = 0; lev < max_lev; lev++) + if (part[lev]) + list = merge(priv, cmp, part[lev], list); + + merge_and_restore_back_links(priv, cmp, head, part[max_lev], list); +} +EXPORT_SYMBOL(list_sort); diff --git a/xen/include/xen/list_sort.h b/xen/include/xen/list_sort.h new file mode 100644 index 0000000000..13ce0a55ec --- /dev/null +++ b/xen/include/xen/list_sort.h @@ -0,0 +1,11 @@ +#ifndef _LINUX_LIST_SORT_H +#define _LINUX_LIST_SORT_H + +#include + +struct list_head; + +void list_sort(void *priv, struct list_head *head, + int (*cmp)(void *priv, struct list_head *a, + struct list_head *b)); +#endif From patchwork Mon Mar 5 16:03:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130698 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2855670lja; Mon, 5 Mar 2018 08:08:44 -0800 (PST) X-Google-Smtp-Source: AG47ELtQMjvuqY4dl2fTV99NZNaQJEKjWIB801IMW69QImNv87LqJv3vmXwNXuC7DDcA69BZ951m X-Received: by 10.107.15.8 with SMTP id x8mr18406260ioi.38.1520266039742; Mon, 05 Mar 2018 08:07:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266039; cv=none; d=google.com; s=arc-20160816; b=PEdwRjEcA6bUoDpgQ/WMN1aHUklXsJg+Tr+ZOWdrCfK/sAwRn16U/epmbsTposH4Bx SrADfuCnzNIjJn04crKqboh7JBslw2kghmiGGLAF72cV1frF19S8KNZElEYA9cq5VgKv aYOx0vv2v1LuSyp6arlmNv2zbxhRyKwKfHyAF/23fG33jUX6J6AjVn73ToEo2Kr32Fn4 r7h5IEDgpzKXJnNM7qELntknw/TQXEYh40ghTqv0HEe9UZX8f/ZaF5+93wCz817Ck/K0 a4VDWh9AAbxj6QRyTvEo+PYbDHcT6QMaQZNvNFvCVfjI3UNrG86R3i3PbybEPUd0WRgb i6kQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=QMvX2Qm6+WWu3oDxEGL+az0AUCEVeFEyB++HLwHOgtA=; b=OfUIPsdgQsdZH8XApipcNIDJLYlirbIoQT23vGbS+EDUioTTjdKU1gxee7LkGxrXs5 CVsK+8bNprxkMwyBNh9ZNQDDljOWHHIGPd6HRXDKGqROhPbLvDii2bmI6+cpLvAIzMDI k0tSe12BAu/MU3lGUE0UYeOJH+zX67f3LncxjSlpAT7V9965Q9e455I1NN79LNfximNs uMfkSSEvyzAFgAjPDCEtrxIAAOpL8gBuDRZ8wx3hbNBY7GqxL9U18QT1DXthlpu/UcFu IwEjJzNjPsp9neRFWuBRr1iN7vNDAgV22Uen69X/bil+ZusYNJYjh3fd6i1qw3ZbNq+J ci+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=jM1i0jMB; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id o200si5746638itg.20.2018.03.05.08.07.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Mar 2018 08:07:19 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=jM1i0jMB; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1essbh-00083r-Lc; Mon, 05 Mar 2018 16:04:57 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1essbg-00080D-9L for xen-devel@lists.xenproject.org; Mon, 05 Mar 2018 16:04:56 +0000 X-Inumbo-ID: ca55ba88-208e-11e8-ba59-bc764e045a96 Received: from mail-wm0-x243.google.com (unknown [2a00:1450:400c:c09::243]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id ca55ba88-208e-11e8-ba59-bc764e045a96; Mon, 05 Mar 2018 17:03:49 +0100 (CET) Received: by mail-wm0-x243.google.com with SMTP id i3so16516338wmi.4 for ; Mon, 05 Mar 2018 08:04:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lylzTnPk2FlpLdSzqyizAd7OqXxogX88uOHAh3ylYlw=; b=jM1i0jMBKoAyy7eVA7aQLbTPqhyTRXvbqiGPwwyIR/H4ginAAiGN4cHiBdM5vsin8G BlAB1RQSvlxbagkXyUMeHMpPY63S76shLyx4B4hZMQC/uXH7YqTctPO3Qd3h3sfcRiKc BGba0ZwCGnMXrPPoSGIf3Nrsk441mfshEjMLM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lylzTnPk2FlpLdSzqyizAd7OqXxogX88uOHAh3ylYlw=; b=OylQ0aOD3si2CUroF/dry0rDG4U6Mz2og48Uqx8uj2HKr5VG0D+Vle/8bpl30rpxwC ZVBI6HA9yjvbIVJbOtr4YieVx6G3vSUiCTnmC00bBpdZtTkm8IwvS8rhCwfd9MqmVtcb dquMb2zTLbHp6c9HBncmBxJQy0qhRc5JIfyABqVIBVdzgMBw9V45bZSRIYPZahYjYHfj qRitN/9zD1IXg1Wyj0WuIZDFFSJHHj9W/Ypf3v6mBA49SEXp2IfIGoTNI6kcs1Zz7KDA hEgw40blFWcEt309v9YPSFCCq6nv6HljfNucOpv//xA3ynTj/fw/WgQMakD8nsjSuE4H zKmQ== X-Gm-Message-State: AElRT7FAQZrNLfJjO3SdBWePqDkqLce0GaS7ndj4yyFm87AKfE3BITrV mlhTRYM4PcWMXc4WozF5fwa5ZA== X-Received: by 10.28.50.69 with SMTP id y66mr9337273wmy.133.1520265893735; Mon, 05 Mar 2018 08:04:53 -0800 (PST) Received: from e104803-lin.lan (mail.andrep.de. [217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:53 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:49 +0000 Message-Id: <20180305160415.16760-32-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 31/57] ARM: new VGIC: Add IRQ sync/flush framework X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Implement the framework for syncing IRQs between our emulation and the list registers, which represent the guest's view of IRQs. This is done in kvm_vgic_flush_hwstate and kvm_vgic_sync_hwstate, which gets called on guest entry and exit. The code talking to the actual GICv2/v3 hardware is added in the following patches. This is based on Linux commit 0919e84c0fc1, written by Marc Zyngier. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - extend comments - adapt to former changes - remove gic_clear_lrs() xen/arch/arm/vgic/vgic.c | 239 +++++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic.h | 2 + 2 files changed, 241 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index efa6c67cb7..8e5215a00d 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -400,6 +400,245 @@ int vgic_inject_irq(struct domain *d, struct vcpu *vcpu, unsigned int intid, return 0; } +/** + * vgic_prune_ap_list() - Remove non-relevant interrupts from the ap_list + * + * @vcpu: The VCPU of which the ap_list should be pruned. + * + * Go over the list of interrupts on a VCPU's ap_list, and prune those that + * we won't have to consider in the near future. + * This removes interrupts that have been successfully handled by the guest, + * or that have otherwise became obsolete (not pending anymore). + * Also this moves interrupts between VCPUs, if their affinity has changed. + */ +static void vgic_prune_ap_list(struct vcpu *vcpu) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic; + struct vgic_irq *irq, *tmp; + unsigned long flags; + +retry: + spin_lock_irqsave(&vgic_cpu->ap_list_lock, flags); + + list_for_each_entry_safe( irq, tmp, &vgic_cpu->ap_list_head, ap_list ) + { + struct vcpu *target_vcpu, *vcpuA, *vcpuB; + + spin_lock(&irq->irq_lock); + + BUG_ON(vcpu != irq->vcpu); + + target_vcpu = vgic_target_oracle(irq); + + if ( !target_vcpu ) + { + /* + * We don't need to process this interrupt any + * further, move it off the list. + */ + list_del(&irq->ap_list); + irq->vcpu = NULL; + spin_unlock(&irq->irq_lock); + + /* + * This vgic_put_irq call matches the + * vgic_get_irq_kref in vgic_queue_irq_unlock, + * where we added the LPI to the ap_list. As + * we remove the irq from the list, we drop + * also drop the refcount. + */ + vgic_put_irq(vcpu->domain, irq); + continue; + } + + if ( target_vcpu == vcpu ) + { + /* We're on the right CPU */ + spin_unlock(&irq->irq_lock); + continue; + } + + /* This interrupt looks like it has to be migrated. */ + + spin_unlock(&irq->irq_lock); + spin_unlock_irqrestore(&vgic_cpu->ap_list_lock, flags); + + /* + * Ensure locking order by always locking the smallest + * ID first. + */ + if ( vcpu->vcpu_id < target_vcpu->vcpu_id ) + { + vcpuA = vcpu; + vcpuB = target_vcpu; + } + else + { + vcpuA = target_vcpu; + vcpuB = vcpu; + } + + spin_lock_irqsave(&vcpuA->arch.vgic.ap_list_lock, flags); + spin_lock(&vcpuB->arch.vgic.ap_list_lock); + spin_lock(&irq->irq_lock); + + /* + * If the affinity has been preserved, move the + * interrupt around. Otherwise, it means things have + * changed while the interrupt was unlocked, and we + * need to replay this. + * + * In all cases, we cannot trust the list not to have + * changed, so we restart from the beginning. + */ + if ( target_vcpu == vgic_target_oracle(irq) ) + { + struct vgic_cpu *new_cpu = &target_vcpu->arch.vgic; + + list_del(&irq->ap_list); + irq->vcpu = target_vcpu; + list_add_tail(&irq->ap_list, &new_cpu->ap_list_head); + } + + spin_unlock(&irq->irq_lock); + spin_unlock(&vcpuB->arch.vgic.ap_list_lock); + spin_unlock_irqrestore(&vcpuA->arch.vgic.ap_list_lock, flags); + goto retry; + } + + spin_unlock_irqrestore(&vgic_cpu->ap_list_lock, flags); +} + +static inline void vgic_fold_lr_state(struct vcpu *vcpu) +{ +} + +/* Requires the irq_lock to be held. */ +static inline void vgic_populate_lr(struct vcpu *vcpu, + struct vgic_irq *irq, int lr) +{ + ASSERT(spin_is_locked(&irq->irq_lock)); +} + +static inline void vgic_set_underflow(struct vcpu *vcpu) +{ +} + +/* Requires the ap_list_lock to be held. */ +static int compute_ap_list_depth(struct vcpu *vcpu) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic; + struct vgic_irq *irq; + int count = 0; + + ASSERT(spin_is_locked(&vgic_cpu->ap_list_lock)); + + list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) + { + spin_lock(&irq->irq_lock); + /* GICv2 SGIs can count for more than one... */ + if ( vgic_irq_is_sgi(irq->intid) && irq->source ) + count += hweight8(irq->source); + else + count++; + spin_unlock(&irq->irq_lock); + } + return count; +} + +/* Requires the VCPU's ap_list_lock to be held. */ +static void vgic_flush_lr_state(struct vcpu *vcpu) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic; + struct vgic_irq *irq; + int count = 0; + + ASSERT(spin_is_locked(&vgic_cpu->ap_list_lock)); + + if ( compute_ap_list_depth(vcpu) > gic_get_nr_lrs() ) + vgic_sort_ap_list(vcpu); + + list_for_each_entry( irq, &vgic_cpu->ap_list_head, ap_list ) + { + spin_lock(&irq->irq_lock); + + if ( unlikely(vgic_target_oracle(irq) != vcpu) ) + goto next; + + /* + * If we get an SGI with multiple sources, try to get + * them in all at once. + */ + do + { + vgic_populate_lr(vcpu, irq, count++); + } while ( irq->source && count < gic_get_nr_lrs() ); + +next: + spin_unlock(&irq->irq_lock); + + if ( count == gic_get_nr_lrs() ) + { + if ( !list_is_last(&irq->ap_list, &vgic_cpu->ap_list_head) ) + vgic_set_underflow(vcpu); + break; + } + } + + vcpu->arch.vgic.used_lrs = count; +} + +/** + * vgic_sync_from_lrs() - Update VGIC state from hardware after a guest's run. + * @vcpu: the VCPU for which to transfer from the LRs to the IRQ list. + * + * Sync back the hardware VGIC state after the guest has run, into our + * VGIC emulation structures, It reads the LRs and updates the respective + * struct vgic_irq, taking level/edge into account. + * This is the high level function which takes care of the conditions, + * also bails out early if there were no interrupts queued. + * Was: kvm_vgic_sync_hwstate() + */ +void vgic_sync_from_lrs(struct vcpu *vcpu) +{ + /* An empty ap_list_head implies used_lrs == 0 */ + if ( list_empty(&vcpu->arch.vgic.ap_list_head) ) + return; + + vgic_fold_lr_state(vcpu); + + vgic_prune_ap_list(vcpu); +} + +/** + * vgic_sync_to_lrs() - flush emulation state into the hardware on guest entry + * + * Before we enter a guest, we have to translate the virtual GIC state of a + * VCPU into the GIC virtualization hardware registers, namely the LRs. + * This is the high level function which takes care about the conditions + * and the locking, also bails out early if there are no interrupts queued. + * Was: kvm_vgic_flush_hwstate() + */ +void vgic_sync_to_lrs(void) +{ + /* + * If there are no virtual interrupts active or pending for this + * VCPU, then there is no work to do and we can bail out without + * taking any lock. There is a potential race with someone injecting + * interrupts to the VCPU, but it is a benign race as the VCPU will + * either observe the new interrupt before or after doing this check, + * and introducing additional synchronization mechanism doesn't change + * this. + */ + if ( list_empty(¤t->arch.vgic.ap_list_head) ) + return; + + ASSERT(!local_irq_is_enabled()); + + spin_lock(¤t->arch.vgic.ap_list_lock); + vgic_flush_lr_state(current); + spin_unlock(¤t->arch.vgic.ap_list_lock); +} /* * Local variables: * mode: C diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index 3430955d9f..a495116cb7 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -17,6 +17,8 @@ #ifndef __XEN_ARM_VGIC_VGIC_H__ #define __XEN_ARM_VGIC_VGIC_H__ +#define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS) + static inline bool irq_is_pending(struct vgic_irq *irq) { if ( irq->config == VGIC_CONFIG_EDGE ) From patchwork Mon Mar 5 16:03:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130683 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2854008lja; Mon, 5 Mar 2018 08:07:19 -0800 (PST) X-Google-Smtp-Source: AG47ELuMges7GgtF1kIV7gJVkXxXj8lKhUbSd5lp3ZSVq7RVo/DaRId4jEx3QTZmzO5QMznFCcLw X-Received: by 10.107.84.8 with SMTP id i8mr776303iob.260.1520266039488; Mon, 05 Mar 2018 08:07:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266039; cv=none; d=google.com; s=arc-20160816; b=I99CdCc25zd++gPGBBTFD8ZkoWTNXTATOxUQNzKc/SH4JL26izpWiaITlVnkAQVnhJ qxl9oEmdH9FcH/27qIsQE1lps4wTJs9ruSmkufM+ot+EasJY87HeS5gqu7oNyJm3r2TK UH7voGA4G6kV0uzA5qXrkxneNZiY3vcxpQ6lRVeiERZC40NyTJMjy2hUxbwTW23ngwtr R9l7c1E0c68n1d93bX5zjfF5zO3zttlTzWi8KHjN3k8+cHSSAct7d9h2KAFNnfPx7Epl 6Y26xWkjAwrrCDwNiQPgPpanKFRwdO64voa77N6cPfZC16Ajtw6h1NIP0QBk1klZXVt6 29zA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=qQBj5L3+Tav8R4vlViSyk6j2yQXAUnzSngSBqPd5R70=; b=XqBMEcjqxX1jfRZZscPNqPxkc41bloa2IK0c/4kFdC3SL5lQab2o+swEQ+xiwuZ5KD zj2UkCA++wcGSktb9wrbEqCpws8NuEOElj4FjNKiX4bFCigOSEOfiF0YJQd5CT1svWbI VIYlIChsHhA2SzSoH2zZM1FhMYQ0HzP7k/3RiGKIfVXmo4tX8hmOn8533aBkP3fJlOac w4GuByH9Uz3xfce7cqoDLtTc4om5Er96PF1M7B1C+16o1uAFRiGrDc3vxYjECWGT4aeM kyCUDjXbhPajbslr3TXZX7toMiq0JV6oRz5bnZwqDNnZetASu3nCtMSuKgMsyVAc+392 9Y2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Tlsn6iEF; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:54 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:50 +0000 Message-Id: <20180305160415.16760-33-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 32/57] ARM: new VGIC: Add GICv2 world switch backend X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Processing maintenance interrupts and accessing the list registers are dependent on the host's GIC version. Introduce vgic-v2.c to contain GICv2 specific functions. Implement the GICv2 specific code for syncing the emulation state into the VGIC registers. This also adds the hook to let Xen setup the host GIC addresses. This is based on Linux commit 140b086dd197, written by Marc Zyngier. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - extend comments - adapt to former changes - use existing Xen LR accessor interface (->write_lr, ->read_lr) - merge save_state and restore_state into callers - add vgic_irq_is_mapped_level() helper xen/arch/arm/vgic/vgic-v2.c | 231 ++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic.c | 7 ++ xen/arch/arm/vgic/vgic.h | 9 ++ 3 files changed, 247 insertions(+) create mode 100644 xen/arch/arm/vgic/vgic-v2.c diff --git a/xen/arch/arm/vgic/vgic-v2.c b/xen/arch/arm/vgic/vgic-v2.c new file mode 100644 index 0000000000..4e74ebf7f5 --- /dev/null +++ b/xen/arch/arm/vgic/vgic-v2.c @@ -0,0 +1,231 @@ +/* + * Copyright (C) 2015, 2016 ARM Ltd. + * Imported from Linux ("new" KVM VGIC) and heavily adapted to Xen. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include + +#include "vgic.h" + +static struct { + bool enabled; + paddr_t dbase; /* Distributor interface address */ + paddr_t cbase; /* CPU interface address & size */ + paddr_t csize; + paddr_t vbase; /* Virtual CPU interface address */ + + /* Offset to add to get an 8kB contiguous region if GIC is aliased */ + uint32_t aliased_offset; +} gic_v2_hw_data; + +void vgic_v2_setup_hw(paddr_t dbase, paddr_t cbase, paddr_t csize, + paddr_t vbase, uint32_t aliased_offset) +{ + gic_v2_hw_data.enabled = true; + gic_v2_hw_data.dbase = dbase; + gic_v2_hw_data.cbase = cbase; + gic_v2_hw_data.csize = csize; + gic_v2_hw_data.vbase = vbase; + gic_v2_hw_data.aliased_offset = aliased_offset; +} + +void vgic_v2_set_underflow(struct vcpu *vcpu) +{ + gic_hw_ops->update_hcr_status(GICH_HCR_UIE, 1); +} + +/* + * transfer the content of the LRs back into the corresponding ap_list: + * - active bit is transferred as is + * - pending bit is + * - transferred as is in case of edge sensitive IRQs + * - set to the line-level (resample time) for level sensitive IRQs + */ +void vgic_v2_fold_lr_state(struct vcpu *vcpu) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic; + unsigned int used_lrs = vcpu->arch.vgic.used_lrs; + unsigned long flags; + unsigned int lr; + + if ( !used_lrs ) /* No LRs used, so nothing to sync back here. */ + return; + + gic_hw_ops->update_hcr_status(GICH_HCR_UIE, 0); + + for ( lr = 0; lr < used_lrs; lr++ ) + { + struct gic_lr lr_val; + uint32_t intid; + struct vgic_irq *irq; + + gic_hw_ops->read_lr(lr, &lr_val); + + /* + * TODO: Possible optimization to avoid reading LRs: + * Read the ELRSR to find out which of our LRs have been cleared + * by the guest. We just need to know the IRQ number for those, which + * we could save in an array when populating the LRs. + * This trades one MMIO access (ELRSR) for possibly more than one (LRs), + * but requires some more code to save the IRQ number and to handle + * those finished IRQs according to the algorithm below. + * We need some numbers to justify this: chances are that we don't + * have many LRs in use most of the time, so we might not save much. + */ + gic_hw_ops->clear_lr(lr); + + intid = lr_val.virq; + irq = vgic_get_irq(vcpu->domain, vcpu, intid); + + spin_lock_irqsave(&irq->irq_lock, flags); + + /* Always preserve the active bit */ + irq->active = !!(lr_val.state & GICH_LR_ACTIVE); + + /* Edge is the only case where we preserve the pending bit */ + if ( irq->config == VGIC_CONFIG_EDGE && (lr_val.state & GICH_LR_PENDING) ) + { + irq->pending_latch = true; + + if ( vgic_irq_is_sgi(intid) ) + irq->source |= (1U << lr_val.source); + } + + /* + * Level-triggered mapped IRQs are special because we only + * observe rising edges as input to the VGIC. + * + * If the guest never acked the interrupt we have to sample + * the physical line and set the line level, because the + * device state could have changed or we simply need to + * process the still pending interrupt later. + * + * If this causes us to lower the level, we have to also clear + * the physical active state, since we will otherwise never be + * told when the interrupt becomes asserted again. + */ + if ( vgic_irq_is_mapped_level(irq) && (lr_val.state & GICH_LR_PENDING) ) + { + struct irq_desc *irqd; + + ASSERT(irq->hwintid >= VGIC_NR_PRIVATE_IRQS); + + irqd = irq_to_desc(irq->hwintid); + irq->line_level = gic_read_pending_state(irqd); + + if ( !irq->line_level ) + gic_set_active_state(irqd, false); + } + + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(vcpu->domain, irq); + } + + gic_hw_ops->update_hcr_status(GICH_HCR_EN, 0); + vgic_cpu->used_lrs = 0; +} + +/** + * vgic_v2_populate_lr() - Populates an LR with the state of a given IRQ. + * @vcpu: The VCPU which the given @irq belongs to. + * @irq: The IRQ to convert into an LR. The irq_lock must be held already. + * @lr: The LR number to transfer the state into. + * + * This moves a virtual IRQ, represented by its vgic_irq, into a list register. + * Apart from translating the logical state into the LR bitfields, it also + * changes some state in the vgic_irq. + * For an edge sensitive IRQ the pending state is cleared in struct vgic_irq, + * for a level sensitive IRQ the pending state value is unchanged, as it is + * dictated directly by the input line level. + * + * If @irq describes an SGI with multiple sources, we choose the + * lowest-numbered source VCPU and clear that bit in the source bitmap. + * + * The irq_lock must be held by the caller. + */ +void vgic_v2_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr) +{ + struct gic_lr lr_val = {0}; + + lr_val.virq = irq->intid; + + if ( irq_is_pending(irq) ) + { + lr_val.state |= GICH_LR_PENDING; + + if ( irq->config == VGIC_CONFIG_EDGE ) + irq->pending_latch = false; + + if ( vgic_irq_is_sgi(irq->intid) ) + { + u32 src = ffs(irq->source); + + BUG_ON(!src); + lr_val.source = (src - 1); + irq->source &= ~(1 << (src - 1)); + if ( irq->source ) + irq->pending_latch = true; + } + } + + if ( irq->active ) + lr_val.state |= GICH_LR_ACTIVE; + + if ( irq->hw ) + { + lr_val.hw_status = 1; + lr_val.pirq = irq->hwintid; + /* + * Never set pending+active on a HW interrupt, as the + * pending state is kept at the physical distributor + * level. + */ + if ( irq->active && irq_is_pending(irq) ) + lr_val.state &= ~GICH_LR_PENDING; + } + else + { + if ( irq->config == VGIC_CONFIG_LEVEL ) + lr_val.eoi = 1; + } + + /* + * Level-triggered mapped IRQs are special because we only observe + * rising edges as input to the VGIC. We therefore lower the line + * level here, so that we can take new virtual IRQs. See + * vgic_v2_fold_lr_state for more info. + */ + if ( vgic_irq_is_mapped_level(irq) && (lr_val.state & GICH_LR_PENDING) ) + irq->line_level = false; + + /* The GICv2 LR only holds five bits of priority. */ + lr_val.priority = irq->priority >> 3; + + gic_hw_ops->write_lr(lr, &lr_val); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 8e5215a00d..85e39f6f42 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -511,6 +511,7 @@ retry: static inline void vgic_fold_lr_state(struct vcpu *vcpu) { + vgic_v2_fold_lr_state(vcpu); } /* Requires the irq_lock to be held. */ @@ -518,10 +519,13 @@ static inline void vgic_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr) { ASSERT(spin_is_locked(&irq->irq_lock)); + + vgic_v2_populate_lr(vcpu, irq, lr); } static inline void vgic_set_underflow(struct vcpu *vcpu) { + vgic_v2_set_underflow(vcpu); } /* Requires the ap_list_lock to be held. */ @@ -638,7 +642,10 @@ void vgic_sync_to_lrs(void) spin_lock(¤t->arch.vgic.ap_list_lock); vgic_flush_lr_state(current); spin_unlock(¤t->arch.vgic.ap_list_lock); + + gic_hw_ops->update_hcr_status(GICH_HCR_EN, 1); } + /* * Local variables: * mode: C diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index a495116cb7..116b26544e 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -27,6 +27,11 @@ static inline bool irq_is_pending(struct vgic_irq *irq) return irq->pending_latch || irq->line_level; } +static inline bool vgic_irq_is_mapped_level(struct vgic_irq *irq) +{ + return irq->config == VGIC_CONFIG_LEVEL && irq->hw; +} + struct vgic_irq *vgic_get_irq(struct domain *d, struct vcpu *vcpu, u32 intid); void vgic_put_irq(struct domain *d, struct vgic_irq *irq); @@ -41,6 +46,10 @@ static inline void vgic_get_irq_kref(struct vgic_irq *irq) atomic_inc(&irq->refcount); } +void vgic_v2_fold_lr_state(struct vcpu *vcpu); +void vgic_v2_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr); +void vgic_v2_set_underflow(struct vcpu *vcpu); + #endif /* From patchwork Mon Mar 5 16:03:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130665 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853677lja; Mon, 5 Mar 2018 08:07:05 -0800 (PST) X-Google-Smtp-Source: AG47ELv+p8ZogQ1deuR/1sq4dNbJYK3Oo8ICKEvZ0oHrKXqK5J3ksmiJqQ7lVlSWZw3mNrAPMPfk X-Received: by 10.107.163.78 with SMTP id m75mr14602437ioe.26.1520266025001; Mon, 05 Mar 2018 08:07:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266024; cv=none; d=google.com; s=arc-20160816; b=WvzgL0TgcTwENC2+imxClPpRCnPDa3HNLQlltbHXlCBL4KIS2OCXP653aJ7X1KrMQx h8zsWqZwJRqIuksm22V0sSnEiEr2ohI+6j00LGaXXVcyqcy++bTFM7/HFEy5JampU9lM WK8Uijrv0VUwwwGX1JMTUHDZVjdYvERE7fiwdx9xDErz2wQJ2zeUQz1V24V5Y21u3cht Bp5L7uCBS/bM44KCtctc4DR/OAB1XwBKUnyWLdF/Azn1HCoKpcNCr0nXbMYqOgM9G7wn jyejWVAJpdRrBTc9mcZbX15fZYUL9wf7JoosVld+KynKh6YkTett7TbqGHdAvxY/HDUN 1tKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=N9T7JNdo7esTvBEr47nPRDOYsrHfQJ6mTLJ0+FblZyw=; b=ZSYl1chYw4i9kegLhetCMWxvi071e4ohJ1gdTlcr+qrUPhwQsnmcpazD9kb8JKlG/R hGwOfqCfJnqnsdZj+vPUOFioBPtquEuZgSFo6wEGf7TlmeEuL2BH0FLqQVfEBvEAHfGF x4d3ERM2ttvYO8YNQMA0bDem2ufEX+ki09sUsOMiW00IxKeS54yYVYnZrP2iOu79bn+i q3/QPBg3B0WKdxAvdRZw4ygVABjIhHYrTd2J+l9AEw7v8kK2RXqrYr7nIwky7M5YuM4S AsDKZd1ZFaESYbUPV8E4hAvX+EAQiCzWpGX3t4C7l59kbMEcuUQY47ENKSwvg8E+GYK5 UpgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=SfepsSdU; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:55 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:51 +0000 Message-Id: <20180305160415.16760-34-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 33/57] ARM: new VGIC: Implement vgic_vcpu_pending_irq X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Tell Xen whether a particular VCPU has an IRQ that needs handling in the guest. This is used to decide whether a VCPU is runnable or if a hypercall should be preempted to let the guest handle the IRQ. This is based on Linux commit 90eee56c5f90, written by Eric Auger. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - extend commit message - use new function name xen/arch/arm/vgic/vgic.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 85e39f6f42..66a366176a 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -646,6 +646,43 @@ void vgic_sync_to_lrs(void) gic_hw_ops->update_hcr_status(GICH_HCR_EN, 1); } +static int vgic_vcpu_pending_irq(struct vcpu *vcpu) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic; + struct vgic_irq *irq; + bool pending = false; + unsigned long flags; + + if ( !vcpu->domain->arch.vgic.enabled ) + return false; + + spin_lock_irqsave(&vgic_cpu->ap_list_lock, flags); + + list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) + { + spin_lock(&irq->irq_lock); + pending = irq_is_pending(irq) && irq->enabled; + spin_unlock(&irq->irq_lock); + + if ( pending ) + break; + } + + spin_unlock_irqrestore(&vgic_cpu->ap_list_lock, flags); + + return pending; +} + +/** + * vgic_pending_irq() - determine if interrupts need to be injected + * + * Returns: 1 if the guest should run to handle interrupts, 0 otherwise. + */ +int vgic_pending_irq(void) +{ + return vgic_vcpu_pending_irq(current); +} + /* * Local variables: * mode: C From patchwork Mon Mar 5 16:03:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130675 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853844lja; Mon, 5 Mar 2018 08:07:12 -0800 (PST) X-Google-Smtp-Source: AG47ELtkiDl0SHGS3D7qhYW0Rm2UjuO38h8aRkS9WPHJXm32M9oxHbIooqvB2CS3T28D8Ul4X/sk X-Received: by 10.107.156.81 with SMTP id f78mr18350830ioe.68.1520266032635; Mon, 05 Mar 2018 08:07:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266032; cv=none; d=google.com; s=arc-20160816; b=nXGiOkkbZPeruz0wCj1IS+YJQUG/uinshlz9hEdwI0bEyw05ZZl6EKZt6uLQIRmGTy Ou/30BGan3jPS4+x1EhnXtE6e9qdAZl10YnoUlFhlY6LDs/ww4XPgMePXuSohgCeG4tT /Obrxi1GBKqIRMKfFoRNbjEd1vQSJVHLtbRwUXvbwS4KlucN/7prRVqoZtGT+vbC35Yh kkjsn89UuHBJunZnXRnC/1bcOzzWA8r1O+NF5RSTU0b8d0ta38GQmjiopMhhCJwnb/qM cqCrGvT7Nj2hZE96sRKVtTRVXtGhMu5nvqbZA6OaqQNtrkBKPMPd8yMl0ub1LBrPZjGf kIwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=ojN+ev9RKFGyabCukCSnsPZJhHJq65HHvOEcAvFJfyg=; b=Ob7SaTvZtY4CdTgOm7cr2LJK0T0XzTPP7kseunGoWa4MYCqkWBY5Fu8giJFZkmSya5 eE4Yv8Gk4IelWpZchZQP7PJuwjjl0LpKr4sGZeRfWd38zGgwHQMmiX2aCBUBq3kxCsvu zZct2AgRyUrjUCZhbr42u+pWqv9v08qYUBfujlDWUS/7SZoj21/0SGBE5ksgkBnSNWoD 0OSfZRy3ZnOk9wAd2Y99/aDygmCvu/S9+lClMD5043x54+lJtwcrSTVVkk3XEFCZ/ABq ALrji76JRbuQJqHreKaModNNDRdw7sDQChnpCHUdhen2HKJQaZpYEo0Uzte1hLSfjHQL 7+PQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=GuSZn5XX; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:56 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:52 +0000 Message-Id: <20180305160415.16760-35-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 34/57] ARM: new VGIC: Add MMIO handling framework X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Add an MMIO handling framework to the VGIC emulation: Each register is described by its offset, size (or number of bits per IRQ, if applicable) and the read/write handler functions. We provide initialization macros to describe each GIC register later easily. Separate dispatch functions for read and write accesses are connected to Xen's MMIO handling framework and binary-search for the responsible register handler based on the offset address within the region. The register handler prototype are courtesy of Christoffer Dall. This is based on Linux commit 4493b1c4866a, written by Marc Zyngier. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - adapt to former changes - whitespace fixes - use C99 data types - drop unneeded regions support (ITS, CPU i/f) xen/arch/arm/vgic/vgic-mmio.c | 180 ++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic-mmio.h | 99 +++++++++++++++++++++++ 2 files changed, 279 insertions(+) create mode 100644 xen/arch/arm/vgic/vgic-mmio.c create mode 100644 xen/arch/arm/vgic/vgic-mmio.h diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c new file mode 100644 index 0000000000..393460d25a --- /dev/null +++ b/xen/arch/arm/vgic/vgic-mmio.c @@ -0,0 +1,180 @@ +/* + * VGIC MMIO handling functions + * Imported from Linux ("new" KVM VGIC) and heavily adapted to Xen. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#include "vgic.h" +#include "vgic-mmio.h" + +unsigned long vgic_mmio_read_raz(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + return 0; +} + +unsigned long vgic_mmio_read_rao(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + return -1UL; +} + +void vgic_mmio_write_wi(struct vcpu *vcpu, paddr_t addr, + unsigned int len, unsigned long val) +{ + /* Ignore */ +} + +static int match_region(const void *key, const void *elt) +{ + const unsigned int offset = (unsigned long)key; + const struct vgic_register_region *region = elt; + + if ( offset < region->reg_offset ) + return -1; + + if ( offset >= region->reg_offset + region->len ) + return 1; + + return 0; +} + +static const struct vgic_register_region * +vgic_find_mmio_region(const struct vgic_register_region *regions, + int nr_regions, unsigned int offset) +{ + return bsearch((void *)(uintptr_t)offset, regions, nr_regions, + sizeof(regions[0]), match_region); +} + +static bool check_region(const struct domain *d, + const struct vgic_register_region *region, + paddr_t addr, int len) +{ + int flags, nr_irqs = d->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS; + + switch ( len ) + { + case sizeof(uint8_t): + flags = VGIC_ACCESS_8bit; + break; + case sizeof(uint32_t): + flags = VGIC_ACCESS_32bit; + break; + case sizeof(uint64_t): + flags = VGIC_ACCESS_64bit; + break; + default: + return false; + } + + if ( (region->access_flags & flags) && IS_ALIGNED(addr, len) ) + { + if ( !region->bits_per_irq ) + return true; + + /* Do we access a non-allocated IRQ? */ + return VGIC_ADDR_TO_INTID(addr, region->bits_per_irq) < nr_irqs; + } + + return false; +} + +static const struct vgic_register_region * +vgic_get_mmio_region(struct vcpu *vcpu, struct vgic_io_device *iodev, + paddr_t addr, unsigned int len) +{ + const struct vgic_register_region *region; + + region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions, + addr - gfn_to_gaddr(iodev->base_fn)); + if ( !region || !check_region(vcpu->domain, region, addr, len) ) + return NULL; + + return region; +} + +static int dispatch_mmio_read(struct vcpu *vcpu, mmio_info_t *info, + register_t *r, void *priv) +{ + struct vgic_io_device *iodev = priv; + const struct vgic_register_region *region; + unsigned long data = 0; + paddr_t addr = info->gpa; + int len = 1U << info->dabt.size; + + region = vgic_get_mmio_region(vcpu, iodev, addr, len); + if ( !region ) + { + memset(r, 0, len); + return 0; + } + + switch (iodev->iodev_type) + { + case IODEV_DIST: + data = region->read(vcpu, addr, len); + break; + case IODEV_REDIST: + data = region->read(iodev->redist_vcpu, addr, len); + break; + } + + memcpy(r, &data, len); + + return 1; +} + +static int dispatch_mmio_write(struct vcpu *vcpu, mmio_info_t *info, + register_t r, void *priv) +{ + struct vgic_io_device *iodev = priv; + const struct vgic_register_region *region; + unsigned long data = r; + paddr_t addr = info->gpa; + int len = 1U << info->dabt.size; + + region = vgic_get_mmio_region(vcpu, iodev, addr, len); + if ( !region ) + return 0; + + switch (iodev->iodev_type) + { + case IODEV_DIST: + region->write(vcpu, addr, len, data); + break; + case IODEV_REDIST: + region->write(iodev->redist_vcpu, addr, len, data); + break; + } + + return 1; +} + +struct mmio_handler_ops vgic_io_ops = { + .read = dispatch_mmio_read, + .write = dispatch_mmio_write, +}; + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h new file mode 100644 index 0000000000..9219142732 --- /dev/null +++ b/xen/arch/arm/vgic/vgic-mmio.h @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2015, 2016 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __XEN_ARM_VGIC_VGIC_MMIO_H__ +#define __XEN_ARM_VGIC_VGIC_MMIO_H__ + +struct vgic_register_region { + unsigned int reg_offset; + unsigned int len; + unsigned int bits_per_irq; + unsigned int access_flags; + unsigned long (*read)(struct vcpu *vcpu, paddr_t addr, + unsigned int len); + void (*write)(struct vcpu *vcpu, paddr_t addr, + unsigned int len, unsigned long val); +}; + +extern struct mmio_handler_ops vgic_io_ops; + +#define VGIC_ACCESS_8bit 1 +#define VGIC_ACCESS_32bit 2 +#define VGIC_ACCESS_64bit 4 + +/* + * Generate a mask that covers the number of bytes required to address + * up to 1024 interrupts, each represented by bits. This assumes + * that is a power of two. + */ +#define VGIC_ADDR_IRQ_MASK(bits) (((bits) * 1024 / 8) - 1) + +/* + * (addr & mask) gives us the _byte_ offset for the INT ID. + * We multiply this by 8 the get the _bit_ offset, then divide this by + * the number of bits to learn the actual INT ID. + * But instead of a division (which requires a "long long div" implementation), + * we shift by the binary logarithm of . + * This assumes that is a power of two. + */ +#define VGIC_ADDR_TO_INTID(addr, bits) (((addr) & VGIC_ADDR_IRQ_MASK(bits)) * \ + 8 >> LOG_2(bits)) + +/* + * Some VGIC registers store per-IRQ information, with a different number + * of bits per IRQ. For those registers this macro is used. + * The _WITH_LENGTH version instantiates registers with a fixed length + * and is mutually exclusive with the _PER_IRQ version. + */ +#define REGISTER_DESC_WITH_BITS_PER_IRQ(off, rd, wr, bpi, acc) \ + { \ + .reg_offset = off, \ + .bits_per_irq = bpi, \ + .len = bpi * 1024 / 8, \ + .access_flags = acc, \ + .read = rd, \ + .write = wr, \ + } + +#define REGISTER_DESC_WITH_LENGTH(off, rd, wr, length, acc) \ + { \ + .reg_offset = off, \ + .bits_per_irq = 0, \ + .len = length, \ + .access_flags = acc, \ + .read = rd, \ + .write = wr, \ + } + +#define REGISTER_DESC_WITH_LENGTH_UACCESS(off, rd, wr, length, acc) \ + { \ + .reg_offset = off, \ + .bits_per_irq = 0, \ + .len = length, \ + .access_flags = acc, \ + .read = rd, \ + .write = wr, \ + } + +unsigned long vgic_mmio_read_raz(struct vcpu *vcpu, + paddr_t addr, unsigned int len); + +unsigned long vgic_mmio_read_rao(struct vcpu *vcpu, + paddr_t addr, unsigned int len); + +void vgic_mmio_write_wi(struct vcpu *vcpu, paddr_t addr, + unsigned int len, unsigned long val); + +#endif From patchwork Mon Mar 5 16:03:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130659 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853601lja; Mon, 5 Mar 2018 08:07:02 -0800 (PST) X-Google-Smtp-Source: AG47ELvqW5aCWMRIj5MIQYnx8s8atBPnU+pQ0SWweYyyhR0Gv8QpdJ+0D1dJVzltuuKxiAGxCLz7 X-Received: by 10.36.227.142 with SMTP id d136mr13934313ith.94.1520266021903; Mon, 05 Mar 2018 08:07:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266021; cv=none; d=google.com; s=arc-20160816; b=sAzgs3Bh8sH/8J9J4HBOJBTIO8ONDukeh42hC1cmaky6o6KLVPRRIIBrA3MsB7mFXC r/PKUvLAPhuV3g8Fi4ZTbR2Hl8JvPwq6d4+EfMyWIlL80/CvEPJr/DjfwwN88P7wqGNX ymj+SyAZ1Nc/PdjccadxtSzXegj4R9jWgokrVI0uAtrl6IjziJABhuc6iZ5ZK0CWgITb bW+/i7+ZGBiKNvbuv5EtJj1JqQ+suoo0HOxgZpHrCA54VOAbcf/VWPamNkx3YEdgnAwb vCVI4enVsY/8d5tj/bAfkTHzp2Rbp1RfKo5x5ZLh+KcCcZ+FHDwOstI+rxT3MVG8q5wQ vn3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=EYf02ZSNKRQMXbnHu3p34Eb4gQPcfV6QaOmkIpLwawU=; b=lCrHpvQgQyWmVZIHDSsowagGx8EOUqGKDlin4ScJGzKqJ5OLYvZsQDYlxJmkWqnqWj deuj5PyHQqeogsa85hKQPNQdLLKnCtv6lkSBnINSfdQ5/BBfdp1mLjslCbcZrU5UjNM9 YErFAIst+KawVJtiOIK/D7AYK+dPMrMvxJrnKfJNgsJPLOI/fB6NRItwdwUDy3fRn7zK XrObd0+g0mWbTUnWGCEVTvCSxfzRTqS/W2R7UKy1ILhAkS+DqTqpolnFk0UbIt/7fF8E LIijhb08BBXJQWr/U7ENjgmVWRSkZKC/x8QNGD647VtB6Nz2LgLP+LLxNvQLJctr3LDg 1yCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Zf9IIMH6; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:57 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:53 +0000 Message-Id: <20180305160415.16760-36-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 35/57] ARM: new VGIC: Add GICv2 MMIO handling framework X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Create vgic-mmio-v2.c to describe GICv2 emulation specific handlers using the initializer macros provided by the VGIC MMIO framework. Provide a function to register the GICv2 distributor registers to the Xen MMIO framework. The actual handler functions are still stubs in this patch. This is based on Linux commit fb848db39661, written by Andre Przywara. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- Changelog RFC ... v1: - drop (dummy) user interface entries - use frame number instead of physical address xen/arch/arm/vgic/vgic-mmio-v2.c | 83 ++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic-mmio.c | 25 ++++++++++++ xen/arch/arm/vgic/vgic-mmio.h | 2 + xen/arch/arm/vgic/vgic.h | 2 + 4 files changed, 112 insertions(+) create mode 100644 xen/arch/arm/vgic/vgic-mmio-v2.c diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c new file mode 100644 index 0000000000..6f10cf16ca --- /dev/null +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -0,0 +1,83 @@ +/* + * VGICv2 MMIO handling functions + * Imported from Linux ("new" KVM VGIC) and heavily adapted to Xen. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "vgic.h" +#include "vgic-mmio.h" + +static const struct vgic_register_region vgic_v2_dist_registers[] = { + REGISTER_DESC_WITH_LENGTH(GICD_CTLR, + vgic_mmio_read_raz, vgic_mmio_write_wi, 12, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_IGROUPR, + vgic_mmio_read_rao, vgic_mmio_write_wi, 1, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISENABLER, + vgic_mmio_read_raz, vgic_mmio_write_wi, 1, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICENABLER, + vgic_mmio_read_raz, vgic_mmio_write_wi, 1, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISPENDR, + vgic_mmio_read_raz, vgic_mmio_write_wi, 1, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICPENDR, + vgic_mmio_read_raz, vgic_mmio_write_wi, 1, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISACTIVER, + vgic_mmio_read_raz, vgic_mmio_write_wi, 1, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICACTIVER, + vgic_mmio_read_raz, vgic_mmio_write_wi, 1, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_IPRIORITYR, + vgic_mmio_read_raz, vgic_mmio_write_wi, 8, + VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ITARGETSR, + vgic_mmio_read_raz, vgic_mmio_write_wi, 8, + VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICFGR, + vgic_mmio_read_raz, vgic_mmio_write_wi, 2, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_LENGTH(GICD_SGIR, + vgic_mmio_read_raz, vgic_mmio_write_wi, 4, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_LENGTH(GICD_CPENDSGIR, + vgic_mmio_read_raz, vgic_mmio_write_wi, 16, + VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), + REGISTER_DESC_WITH_LENGTH(GICD_SPENDSGIR, + vgic_mmio_read_raz, vgic_mmio_write_wi, 16, + VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), +}; + +unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev) +{ + dev->regions = vgic_v2_dist_registers; + dev->nr_regions = ARRAY_SIZE(vgic_v2_dist_registers); + + return SZ_4K; +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c index 393460d25a..284a92d288 100644 --- a/xen/arch/arm/vgic/vgic-mmio.c +++ b/xen/arch/arm/vgic/vgic-mmio.c @@ -170,6 +170,31 @@ struct mmio_handler_ops vgic_io_ops = { .write = dispatch_mmio_write, }; +int vgic_register_dist_iodev(struct domain *d, gfn_t dist_base_fn, + enum vgic_type type) +{ + struct vgic_io_device *io_device = &d->arch.vgic.dist_iodev; + unsigned int len; + + switch ( type ) + { + case VGIC_V2: + len = vgic_v2_init_dist_iodev(io_device); + break; + default: + BUG(); + } + + io_device->base_fn = dist_base_fn; + io_device->iodev_type = IODEV_DIST; + io_device->redist_vcpu = NULL; + + register_mmio_handler(d, &vgic_io_ops, gfn_to_gaddr(dist_base_fn), len, + io_device); + + return 0; +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h index 9219142732..621b9a281c 100644 --- a/xen/arch/arm/vgic/vgic-mmio.h +++ b/xen/arch/arm/vgic/vgic-mmio.h @@ -96,4 +96,6 @@ unsigned long vgic_mmio_read_rao(struct vcpu *vcpu, void vgic_mmio_write_wi(struct vcpu *vcpu, paddr_t addr, unsigned int len, unsigned long val); +unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev); + #endif diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index 116b26544e..632b246e93 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -49,6 +49,8 @@ static inline void vgic_get_irq_kref(struct vgic_irq *irq) void vgic_v2_fold_lr_state(struct vcpu *vcpu); void vgic_v2_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr); void vgic_v2_set_underflow(struct vcpu *vcpu); +int vgic_register_dist_iodev(struct domain *d, gfn_t dist_base_fn, + enum vgic_type); #endif From patchwork Mon Mar 5 16:03:54 2018 Content-Type: text/plain; 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[192.237.175.120]) by mx.google.com with ESMTPS id x5si5917654itg.162.2018.03.05.08.07.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Mar 2018 08:07:02 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=KLxStyjQ; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1essbn-0008IN-7p; Mon, 05 Mar 2018 16:05:03 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1essbl-0008Dv-NV for xen-devel@lists.xenproject.org; Mon, 05 Mar 2018 16:05:01 +0000 X-Inumbo-ID: cd76e7b3-208e-11e8-ba59-bc764e045a96 Received: from mail-wr0-x242.google.com (unknown [2a00:1450:400c:c0c::242]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id cd76e7b3-208e-11e8-ba59-bc764e045a96; Mon, 05 Mar 2018 17:03:54 +0100 (CET) Received: by mail-wr0-x242.google.com with SMTP id v18so17184802wrv.0 for ; Mon, 05 Mar 2018 08:05:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5qsL0uhpwbjeVrZ9xeFHiFqNlNmS28Fur0CQo/2i9Ck=; b=KLxStyjQ0h4Ma2yXe+iHLxAY9ss50FCnKWN/Q1HspsH5muTSNYTWj8mR1PE/rbGEGz 8YSr83L36/UPiSvwzEef6eO+bCFAVbnYoGa5mpUhnWbytprrIVztHucaSd5h4jnpGyJV CWzsqAlHa+TfoOgMdwTm3oC1pqwAVvAKtWFO4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5qsL0uhpwbjeVrZ9xeFHiFqNlNmS28Fur0CQo/2i9Ck=; b=sknYsZ96hMCVcoV2JssGih3k7VLlNuS9UC8nZBekcILoClulHoGazBfoFbxiV+9I3j vrG+TmMs959PFpDdawR/kNiD0wUz6JZxp5jHCvZqGNoSnFKpsIsowRhGmhTt+LXPd8jA Pjhwpk0x17RgGWr0mBOZFzJ2NcxAKztW93GJLsUVj9/fp8NtK5F9PAWryDY4nOaV6Nmg QKRmnntX3GajZ50ut8SBEnF0exTUKziS8ZLNjmePL7L8clnYlBySxcF0oVurJUKeFeT9 wG/oW6Qb29hm3KwdpxAvUxjUkhExsY+tnbft0y0fM5TFaeaUGAVVJoecpBhdP02Uvy7r xH6g== X-Gm-Message-State: APf1xPC/LugWXEzlusYs/O6w44NNkDiIfTnb0EgBV+iAnlX9sM4WWCPo m7fKf4gut6CerY65VE+Y2L3seg== X-Received: by 10.223.156.208 with SMTP id h16mr14045527wre.123.1520265899130; Mon, 05 Mar 2018 08:04:59 -0800 (PST) Received: from e104803-lin.lan (mail.andrep.de. [217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:58 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:54 +0000 Message-Id: <20180305160415.16760-37-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 36/57] ARM: new VGIC: Add CTLR, TYPER and IIDR handlers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Those three registers are v2 emulation specific, so their implementation lives entirely in vgic-mmio-v2.c. Also they are handled in one function, as their implementation is pretty simple. When the guest enables the distributor, we kick all VCPUs to get potentially pending interrupts serviced. This is based on Linux commit 2b0cda878965, written by Marc Zyngier. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - use PRODUCT_ID_XEN - use proper locking on enabling VGIC - use kick_vcpu() xen/arch/arm/vgic/vgic-mmio-v2.c | 54 +++++++++++++++++++++++++++++++++++++++- xen/arch/arm/vgic/vgic.c | 15 +++++++++++ xen/arch/arm/vgic/vgic.h | 4 +++ 3 files changed, 72 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index 6f10cf16ca..2e015ed0b1 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -20,9 +20,61 @@ #include "vgic.h" #include "vgic-mmio.h" +static unsigned long vgic_mmio_read_v2_misc(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + uint32_t value; + + switch ( addr & 0x0c ) /* filter for the 4 registers handled here */ + { + case GICD_CTLR: + value = vcpu->domain->arch.vgic.enabled ? GICD_CTL_ENABLE : 0; + break; + case GICD_TYPER: + value = vcpu->domain->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS; + value = (value >> 5) - 1; + value |= (vcpu->domain->max_vcpus - 1) << 5; + break; + case GICD_IIDR: + value = (PRODUCT_ID_XEN << 24) | (IMPLEMENTER_ARM << 0); + break; + default: + return 0; + } + + return value; +} + +static void vgic_mmio_write_v2_misc(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + struct vgic_dist *dist = &vcpu->domain->arch.vgic; + bool enabled; + + switch ( addr & 0x0c ) /* filter for the 4 registers handled here */ + { + case GICD_CTLR: + domain_lock(vcpu->domain); + enabled = dist->enabled; + dist->enabled = val & GICD_CTL_ENABLE; + enabled = !enabled && dist->enabled; + domain_unlock(vcpu->domain); + + if (enabled) + vgic_kick_vcpus(vcpu->domain); + + break; + case GICD_TYPER: + case GICD_IIDR: + /* read-only, writes ignored */ + return; + } +} + static const struct vgic_register_region vgic_v2_dist_registers[] = { REGISTER_DESC_WITH_LENGTH(GICD_CTLR, - vgic_mmio_read_raz, vgic_mmio_write_wi, 12, + vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc, 12, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_IGROUPR, vgic_mmio_read_rao, vgic_mmio_write_wi, 1, diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 66a366176a..465a95f415 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -683,6 +683,21 @@ int vgic_pending_irq(void) return vgic_vcpu_pending_irq(current); } +void vgic_kick_vcpus(struct domain *d) +{ + struct vcpu *vcpu; + + /* + * We've injected an interrupt, time to find out who deserves + * a good kick... + */ + for_each_vcpu( d, vcpu ) + { + if ( vgic_vcpu_pending_irq(vcpu) ) + kick_vcpu(vcpu); + } +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index 632b246e93..588bd067b7 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -17,6 +17,9 @@ #ifndef __XEN_ARM_VGIC_VGIC_H__ #define __XEN_ARM_VGIC_VGIC_H__ +#define PRODUCT_ID_XEN 0x58 /* ASCII code X */ +#define IMPLEMENTER_ARM 0x43b + #define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS) static inline bool irq_is_pending(struct vgic_irq *irq) @@ -37,6 +40,7 @@ struct vgic_irq *vgic_get_irq(struct domain *d, struct vcpu *vcpu, void vgic_put_irq(struct domain *d, struct vgic_irq *irq); void vgic_queue_irq_unlock(struct domain *d, struct vgic_irq *irq, unsigned long flags); +void vgic_kick_vcpus(struct domain *d); static inline void vgic_get_irq_kref(struct vgic_irq *irq) { From patchwork Mon Mar 5 16:03:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130691 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2854376lja; Mon, 5 Mar 2018 08:07:35 -0800 (PST) X-Google-Smtp-Source: AG47ELu5307w7UPnSAiQCW8YpI+sUpj8bhisq7t5jFNgvwaVB/5ahjDbzf7SzjAGC/6tviRbK6/9 X-Received: by 10.107.174.155 with SMTP id n27mr17739803ioo.256.1520266055504; Mon, 05 Mar 2018 08:07:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266055; cv=none; d=google.com; s=arc-20160816; b=Wy+F1Uzdexwfp4ana2AdNJzH4eo84Y3MDKxaiZ2LIoiI7wzdmYQEWYUaTrXbBo8h5a +oM7+fZaOIKhluSp1xku4dYgJvxdhupR7FeKHSEkVYjuPUOP3tCmFQPpcAgXElWE4EA0 ZVNel2vJxHI+jxmJYGHE0SpFVyPgObBR78yxh+3wzrnpoa4CONtmTz1nJSajWQWiC4x9 vNOwsr9gY2jA/ln9/jVvYgmv7RZhOH2ap3KqNkCsPeXGMJo6rXNWZLK4pJ0oNbDsN1AP xWi9MAYcOivY6Ashavd8fu+EDRJhda6PMC8vVT0qqjC9GfxnhuF3cdT7TOKAyiRLlHKQ TfLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=3eQQVP9HRpIG4wAjLcACq/MBnxX13fONk1BA8x5dxGU=; b=JHcZzK2tVP1TjN3TxVJTEyiJU7Cjf6pwKlmTGMM4hsaIRJ5XR13d9oavdGwDIm2VN/ R9YyIgzL/4eSAFWyuhP2hTAbS/69SvaMn1Gk421phGi1sslQUhs2TfzwgDn/j1DEVI+q 0VwKom1WVyveCMsl3L/4E/ShmRpwK7zlXtczeLrGGVNK0suaaIq/bd2r5M1QQBMaW00p zOaSw7F21B4INI9l7LbpGsmPkfbXTXyeQgMDJKjQnMZZOGFdqPrUKy8jGgg4L9aJd1Jm ZRpYLu9WMBl5Bct5f5s3P/D/T2ujhtY+wtpDfergN8iarGgtbVDYSe4+Oj4DIfqv70Py QqyQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=GbuaY3zp; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:59 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:55 +0000 Message-Id: <20180305160415.16760-38-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 37/57] ARM: new VGIC: Add ENABLE registers handlers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" As the enable register handlers are shared between the v2 and v3 emulation, their implementation goes into vgic-mmio.c, to be easily referenced from the v3 emulation as well later. This introduces a vgic_sync_hardware_irq() function, which updates the physical side of a hardware mapped virtual IRQ. Because the existing locking order between vgic_irq->irq_lock and irq_desc->lock dictates so, we drop the irq_lock and retake them in the proper order. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - extend and move vgic_sync_hardware_irq() - do proper locking sequence - skip already disabled/enabled IRQs xen/arch/arm/vgic/vgic-mmio-v2.c | 4 +- xen/arch/arm/vgic/vgic-mmio.c | 117 +++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic-mmio.h | 11 ++++ xen/arch/arm/vgic/vgic.c | 38 +++++++++++++ xen/arch/arm/vgic/vgic.h | 3 + 5 files changed, 171 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index 2e015ed0b1..3dd983f885 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -80,10 +80,10 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { vgic_mmio_read_rao, vgic_mmio_write_wi, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISENABLER, - vgic_mmio_read_raz, vgic_mmio_write_wi, 1, + vgic_mmio_read_enable, vgic_mmio_write_senable, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICENABLER, - vgic_mmio_read_raz, vgic_mmio_write_wi, 1, + vgic_mmio_read_enable, vgic_mmio_write_cenable, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISPENDR, vgic_mmio_read_raz, vgic_mmio_write_wi, 1, diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c index 284a92d288..f8f0252eff 100644 --- a/xen/arch/arm/vgic/vgic-mmio.c +++ b/xen/arch/arm/vgic/vgic-mmio.c @@ -39,6 +39,123 @@ void vgic_mmio_write_wi(struct vcpu *vcpu, paddr_t addr, /* Ignore */ } +/* + * Read accesses to both GICD_ICENABLER and GICD_ISENABLER return the value + * of the enabled bit, so there is only one function for both here. + */ +unsigned long vgic_mmio_read_enable(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 1); + uint32_t value = 0; + unsigned int i; + + /* Loop over all IRQs affected by this read */ + for ( i = 0; i < len * 8; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + if ( irq->enabled ) + value |= (1U << i); + + vgic_put_irq(vcpu->domain, irq); + } + + return value; +} + +void vgic_mmio_write_senable(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 1); + unsigned int i; + + for_each_set_bit( i, &val, len * 8 ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + unsigned long flags; + irq_desc_t *desc; + + spin_lock_irqsave(&irq->irq_lock, flags); + + if ( irq->enabled ) /* skip already enabled IRQs */ + { + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(vcpu->domain, irq); + continue; + } + + irq->enabled = true; + if ( irq->hw ) + { + /* + * The irq cannot be a PPI, we only support delivery + * of SPIs to guests. + */ + ASSERT(irq->hwintid >= VGIC_NR_PRIVATE_IRQS); + + desc = irq_to_desc(irq->hwintid); + } + else + desc = NULL; + + vgic_queue_irq_unlock(vcpu->domain, irq, flags); + + if ( desc ) + vgic_sync_hardware_irq(vcpu->domain, desc, irq); + + vgic_put_irq(vcpu->domain, irq); + } +} + +void vgic_mmio_write_cenable(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 1); + unsigned int i; + + for_each_set_bit( i, &val, len * 8 ) + { + struct vgic_irq *irq; + unsigned long flags; + irq_desc_t *desc; + + irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + spin_lock_irqsave(&irq->irq_lock, flags); + + if ( !irq->enabled ) /* skip already disabled IRQs */ + { + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(vcpu->domain, irq); + continue; + } + + irq->enabled = false; + + if ( irq->hw ) + { + /* + * The irq cannot be a PPI, we only support delivery + * of SPIs to guests. + */ + ASSERT(irq->hwintid >= VGIC_NR_PRIVATE_IRQS); + + desc = irq_to_desc(irq->hwintid); + } + else + desc = NULL; + + spin_unlock_irqrestore(&irq->irq_lock, flags); + + if ( desc ) + vgic_sync_hardware_irq(vcpu->domain, desc, irq); + + vgic_put_irq(vcpu->domain, irq); + } +} + static int match_region(const void *key, const void *elt) { const unsigned int offset = (unsigned long)key; diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h index 621b9a281c..2ddcbbf58d 100644 --- a/xen/arch/arm/vgic/vgic-mmio.h +++ b/xen/arch/arm/vgic/vgic-mmio.h @@ -96,6 +96,17 @@ unsigned long vgic_mmio_read_rao(struct vcpu *vcpu, void vgic_mmio_write_wi(struct vcpu *vcpu, paddr_t addr, unsigned int len, unsigned long val); +unsigned long vgic_mmio_read_enable(struct vcpu *vcpu, + paddr_t addr, unsigned int len); + +void vgic_mmio_write_senable(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + +void vgic_mmio_write_cenable(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev); #endif diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 465a95f415..5246d7c2e7 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -698,6 +698,44 @@ void vgic_kick_vcpus(struct domain *d) } } +static unsigned int translate_irq_type(bool is_level) +{ + return is_level ? IRQ_TYPE_LEVEL_HIGH : IRQ_TYPE_EDGE_RISING; +} + +void vgic_sync_hardware_irq(struct domain *d, + irq_desc_t *desc, struct vgic_irq *irq) +{ + unsigned long flags; + + spin_lock_irqsave(&desc->lock, flags); + spin_lock(&irq->irq_lock); + + /* Is that association actually still valid? (we entered with no locks) */ + if ( desc->irq == irq->hwintid ) + { + if ( irq->enabled ) + { + /* + * We might end up from various callers, so check that the + * interrrupt is disabled before trying to change the config. + */ + if ( irq_type_set_by_domain(d) && + test_bit(_IRQ_DISABLED, &desc->status) ) + gic_set_irq_type(desc, translate_irq_type(irq->config)); + + if ( irq->target_vcpu ) + irq_set_affinity(desc, cpumask_of(irq->target_vcpu->processor)); + desc->handler->enable(desc); + } + else + desc->handler->disable(desc); + } + + spin_unlock(&irq->irq_lock); + spin_unlock_irqrestore(&desc->lock, flags); +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index 588bd067b7..68e205d10a 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -50,6 +50,9 @@ static inline void vgic_get_irq_kref(struct vgic_irq *irq) atomic_inc(&irq->refcount); } +void vgic_sync_hardware_irq(struct domain *d, + irq_desc_t *desc, struct vgic_irq *irq); + void vgic_v2_fold_lr_state(struct vcpu *vcpu); void vgic_v2_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr); void vgic_v2_set_underflow(struct vcpu *vcpu); From patchwork Mon Mar 5 16:03:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130666 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853679lja; Mon, 5 Mar 2018 08:07:05 -0800 (PST) X-Google-Smtp-Source: AG47ELvARAzWPgida83Y0NEW4/yBRDCN01qsn8lDiG2JuHqRCDHJpITc4hOwICIWziY++0Ya0usQ X-Received: by 10.107.150.1 with SMTP id y1mr18986438iod.100.1520266025118; Mon, 05 Mar 2018 08:07:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266025; cv=none; d=google.com; s=arc-20160816; b=R336s+X2vo3VmlTydiDoKq/4mq+Kw0pG7YPow5p+PEQhr5LvN3B7uNn5ybFiVCbidY xdnR/Xv7ZXahZ/WNdB96Q/D+sZdvZTxYuWPNIya1cr+AOKNP6CoOYNFBpb0eim3sH+Z9 1aCtPxISzjP1GPxtYbyL0ExvXf5RIhtRONSQt/8OA42NFCAJaUamNR7R+e6cqawn7yq4 33R/NmLvLiDMOzZ6K6vAD/bo2kIZD0fiZGVT0aNEslAei93kWnTyJD2bY2lyDVvMljUz +S5zg0RxzATtSG3yIQFThFvcDVcUKrFvM7Z/O4gndkU/6Ed+h0GVu18W1YEoLkfed994 iUxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=bqjUwxJbCYJ9zEvpLhyk12ilH3PYClZscgljljTttzw=; b=JftHvDlfSbFlPj488XqrHliRQ8nvYbGcO+pb6F9J0MDIhmR/tfuwhcr7hbFG83OcY3 1yVJBZgzqYnacjlHC0K2cNKy5v069C3lv+DjO5UaKFbg7jKddbNs5Lkbt38Jsq4E0gB7 FBJCibk0BDROpQv+fajIrtS0BP0XdIGhUw9RhyutBm01VG3lDBTj+nzLl5S161CxR854 3r49osOc/tUJkz6lJnOIBVH7Y/v5Wdwt5UrK6lx0pikx/rKCtKswR2OYVjNtgQn0JyXS u5Uqp+D7XMF8/LPs5/Z7XWwObCngBBcXAUd1rN+y6gRT04EIWB99Y3TzFqs+qprnxwcE Gs9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ETvCXKUZ; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id q188si6984113iof.230.2018.03.05.08.07.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Mar 2018 08:07:05 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ETvCXKUZ; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1essbo-0008Md-Ok; Mon, 05 Mar 2018 16:05:04 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1essbo-0008Kx-Bo for xen-devel@lists.xenproject.org; Mon, 05 Mar 2018 16:05:04 +0000 X-Inumbo-ID: cee96562-208e-11e8-ba59-bc764e045a96 Received: from mail-wr0-x241.google.com (unknown [2a00:1450:400c:c0c::241]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id cee96562-208e-11e8-ba59-bc764e045a96; Mon, 05 Mar 2018 17:03:57 +0100 (CET) Received: by mail-wr0-x241.google.com with SMTP id n7so17840686wrn.5 for ; Mon, 05 Mar 2018 08:05:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/z/fCBw4rHZ3uf73t5NFU3sqmPK3GG+fBL/6gpaVUCw=; b=ETvCXKUZ5OI7doYTh17tHtJ4BL7e74xjxomdEjxnEnMsTENZRoKtPgaD712/9TGM3J KPduUesfXhH0bSN/zp+9Y6F0VVVGm1rpfmJdT1Bst6mCBrN8qLZUh2bA3ezXKTfj/k7X 5/0tPhpu2sWNZD1aiNbBwBS2rAM62F0vJgh8o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/z/fCBw4rHZ3uf73t5NFU3sqmPK3GG+fBL/6gpaVUCw=; b=aIuCv+F6Ke8hr9hrbv03JVKsp7BCb40TzlWnhSIVKJiwLraELSxNNIbuAU/Njrsoz1 A0TrvFftDbGQFHg82bYwZ41Qkp4/p99keGWpRq5pULzFKtgjri4yiXVhlwq1szdtEKfg jtXnbZs7gN463yQsbicBpQpzQSR4FC7sNcXeyOFjYEVSag8V5cu5Ls+9m958oxV5lui0 ce6oagSxoC1QKwF8KHiWvKYLmjSpI0DdVhT3reOu/7157oco2uIgECRiU3hhcKStl34w NS9MmuMg5w/gKtTQTqM7GNytfo/kKuRm2HvssApV7l6iTPvnCr9mjjfE6viWqg1W54wk CsDQ== X-Gm-Message-State: APf1xPAoqbnN60CV3fLr7XFILuXK9ygiN4IDaQEC1GCK47STO1nTZulR noPuXN4bHJJW7/hNPTd1XG4tJA== X-Received: by 10.223.151.204 with SMTP id t12mr14027605wrb.156.1520265901546; Mon, 05 Mar 2018 08:05:01 -0800 (PST) Received: from e104803-lin.lan (mail.andrep.de. [217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.05.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:05:01 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:56 +0000 Message-Id: <20180305160415.16760-39-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 38/57] ARM: new VGIC: Add PENDING registers handlers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The pending register handlers are shared between the v2 and v3 emulation, so their implementation goes into vgic-mmio.c, to be easily referenced from the v3 emulation as well later. For level triggered interrupts the real line level is unaffected by this write, so we keep this state separate and combine it with the device's level to get the actual pending state. Hardware mapped IRQs need some special handling, as their hardware state has to be coordinated with the virtual pending bit to avoid hanging or masked interrupts. This is based on Linux commit 96b298000db4, written by Andre Przywara. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - propagate SET/CLEAR_PENDING requests to hardware xen/arch/arm/vgic/vgic-mmio-v2.c | 4 +- xen/arch/arm/vgic/vgic-mmio.c | 125 +++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic-mmio.h | 11 ++++ 3 files changed, 138 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index 3dd983f885..efdd73301d 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -86,10 +86,10 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { vgic_mmio_read_enable, vgic_mmio_write_cenable, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISPENDR, - vgic_mmio_read_raz, vgic_mmio_write_wi, 1, + vgic_mmio_read_pending, vgic_mmio_write_spending, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICPENDR, - vgic_mmio_read_raz, vgic_mmio_write_wi, 1, + vgic_mmio_read_pending, vgic_mmio_write_cpending, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISACTIVER, vgic_mmio_read_raz, vgic_mmio_write_wi, 1, diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c index f8f0252eff..2e939d5e39 100644 --- a/xen/arch/arm/vgic/vgic-mmio.c +++ b/xen/arch/arm/vgic/vgic-mmio.c @@ -156,6 +156,131 @@ void vgic_mmio_write_cenable(struct vcpu *vcpu, } } +unsigned long vgic_mmio_read_pending(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 1); + uint32_t value = 0; + unsigned int i; + + /* Loop over all IRQs affected by this read */ + for ( i = 0; i < len * 8; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + if ( irq_is_pending(irq) ) + value |= (1U << i); + + vgic_put_irq(vcpu->domain, irq); + } + + return value; +} + +void vgic_mmio_write_spending(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 1); + unsigned int i; + unsigned long flags; + irq_desc_t *desc; + + for_each_set_bit( i, &val, len * 8 ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + spin_lock_irqsave(&irq->irq_lock, flags); + irq->pending_latch = true; + + /* To observe the locking order, just take the irq_desc pointer here. */ + if ( irq->hw ) + desc = irq_to_desc(irq->hwintid); + else + desc = NULL; + + vgic_queue_irq_unlock(vcpu->domain, irq, flags); + + /* + * When the VM sets the pending state for a HW interrupt on the virtual + * distributor we set the active state on the physical distributor, + * because the virtual interrupt can become active and then the guest + * can deactivate it. + */ + if ( desc ) + { + spin_lock_irqsave(&desc->lock, flags); + spin_lock(&irq->irq_lock); + + /* Is this h/w IRQ still assigned to the virtual IRQ? */ + if ( irq->hw && desc->irq == irq->hwintid ) + gic_set_active_state(desc, true); + + spin_unlock(&irq->irq_lock); + spin_unlock_irqrestore(&desc->lock, flags); + } + + vgic_put_irq(vcpu->domain, irq); + } +} + +void vgic_mmio_write_cpending(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 1); + unsigned int i; + unsigned long flags; + irq_desc_t *desc; + + for_each_set_bit( i, &val, len * 8 ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + spin_lock_irqsave(&irq->irq_lock, flags); + irq->pending_latch = false; + + /* To observe the locking order, just take the irq_desc pointer here. */ + if ( irq->hw ) + desc = irq_to_desc(irq->hwintid); + else + desc = NULL; + + spin_unlock_irqrestore(&irq->irq_lock, flags); + + /* + * We don't want the guest to effectively mask the physical + * interrupt by doing a write to SPENDR followed by a write to + * CPENDR for HW interrupts, so we clear the active state on + * the physical side if the virtual interrupt is not active. + * This may lead to taking an additional interrupt on the + * host, but that should not be a problem as the worst that + * can happen is an additional vgic injection. We also clear + * the pending state to maintain proper semantics for edge HW + * interrupts. + */ + if ( desc ) + { + spin_lock_irqsave(&desc->lock, flags); + spin_lock(&irq->irq_lock); + + /* Is this h/w IRQ still assigned to the virtual IRQ? */ + if ( irq->hw && desc->irq == irq->hwintid ) + { + gic_set_pending_state(desc, false); + if (!irq->active) + gic_set_active_state(desc, false); + } + + spin_unlock(&irq->irq_lock); + spin_unlock_irqrestore(&desc->lock, flags); + } + + + vgic_put_irq(vcpu->domain, irq); + } +} + static int match_region(const void *key, const void *elt) { const unsigned int offset = (unsigned long)key; diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h index 2ddcbbf58d..4465f3b7e5 100644 --- a/xen/arch/arm/vgic/vgic-mmio.h +++ b/xen/arch/arm/vgic/vgic-mmio.h @@ -107,6 +107,17 @@ void vgic_mmio_write_cenable(struct vcpu *vcpu, paddr_t addr, unsigned int len, unsigned long val); +unsigned long vgic_mmio_read_pending(struct vcpu *vcpu, + paddr_t addr, unsigned int len); + +void vgic_mmio_write_spending(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + +void vgic_mmio_write_cpending(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev); #endif From patchwork Mon Mar 5 16:03:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130674 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853824lja; Mon, 5 Mar 2018 08:07:12 -0800 (PST) X-Google-Smtp-Source: AG47ELtf9j6ym421nsLF8bhUKIkF/5Mg5/oxZ+6CHcCAzhIibVZioHI2yB4UgPf8WUdD5v7bU2lZ X-Received: by 10.107.8.2 with SMTP id 2mr17175458ioi.167.1520266031850; Mon, 05 Mar 2018 08:07:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266031; cv=none; d=google.com; s=arc-20160816; b=jkD/NXWnHYq7gBbewSF3V3AIDGoOTpwf+xQa/PxF8kuMGd/E39lp3MT+3fgBaPlz9R 5FCwv8X8bTscZ9izp4X8+FMxEHN/xFxhYopneCzPj4YiYkmH8zHYfdPK7h4fJ6IhArln y307qNwGf7nDmieKT6rIk/HcRBvhAwoHCeLsi6EwhYsXU6cCEn/tFmB7zDMyjjrJ2gs1 6+EMnKN1bDm79yMDOwV3uxMx2HXrZKPi4CmtqTqrQaYWcMblNyQ0gEJn7TItMLHrqWgA blaBhCFnfTsEzh9GHx/3ecrQfbnnFsAK/bvcz1yACLTUG60G/QVU4ydobSEOgb7q9pQf c6OQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=J+6jUhigkNZNPYpli0XwFX5aieVBPsQWeR6v9oCCUMA=; b=GqCWRTlJBZf5lzanfb65AgDWMDCVz4WLECjAE20pbJLkEnblci4XrFrlDXxLSB9Q3D CSfgJD4jUuJVXmS2hFo94kMRtLm9iUJWg5+tT1604cMnM2iLu1TQmAzP2U2mMZYGJUJe tpcOZ4ep4ev9MeS3Vmj//RMpoBTGfnH0dWl6ANdcZSA8WdiWsqiGJjY32c3Ognu2AZF4 NtIqHwUrQTVQzauHJFbzKMGryIw8IPjZZq8KS9utquy8TQ4NyLBi9BlRt6pXMwvZqGHh DWPjg0svJLxRFGa7A2yaxzqG00dqArLy8qAE0VfsspSU6rgKLU2NpRhcQIMV9WemfswK C2Zg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=TUJ6UmdD; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.05.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:05:02 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:57 +0000 Message-Id: <20180305160415.16760-40-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 39/57] ARM: new VGIC: Add ACTIVE registers handlers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The active register handlers are shared between the v2 and v3 emulation, so their implementation goes into vgic-mmio.c, to be easily referenced from the v3 emulation as well later. Since activation/deactivation of an interrupt may happen entirely in the guest without it ever exiting, we need some extra logic to properly track the active state. For clearing the active state, we would basically have to halt the guest to make sure this is properly propagated into the respective VCPUs. This is not yet implemented in Xen. Fortunately this feature is mostly used to reset a just in initialised GIC, so chances are we are tasked to clear bits that are already zero. Add some simple check to avoid a pointless warning in this case. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - remove premature "proper ACTIVE" handler stub - avoid unnecessary warnings on NO-OP register writes - extend comments xen/arch/arm/vgic/vgic-mmio-v2.c | 4 +- xen/arch/arm/vgic/vgic-mmio.c | 103 +++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic-mmio.h | 11 +++++ 3 files changed, 116 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index efdd73301d..c93455fbb2 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -92,10 +92,10 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { vgic_mmio_read_pending, vgic_mmio_write_cpending, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISACTIVER, - vgic_mmio_read_raz, vgic_mmio_write_wi, 1, + vgic_mmio_read_active, vgic_mmio_write_sactive, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICACTIVER, - vgic_mmio_read_raz, vgic_mmio_write_wi, 1, + vgic_mmio_read_active, vgic_mmio_write_cactive, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_IPRIORITYR, vgic_mmio_read_raz, vgic_mmio_write_wi, 8, diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c index 2e939d5e39..c44d67082f 100644 --- a/xen/arch/arm/vgic/vgic-mmio.c +++ b/xen/arch/arm/vgic/vgic-mmio.c @@ -281,6 +281,109 @@ void vgic_mmio_write_cpending(struct vcpu *vcpu, } } +/* + * The actual active bit for a virtual IRQ is held in the LR. Our shadow + * copy in struct vgic_irq is only synced when needed and may not be + * up-to-date all of the time. + * Returning the actual active state is quite costly (stopping all + * VCPUs processing any affected vIRQs), so we use a simple implementation + * to get the best possible answer. + */ +unsigned long vgic_mmio_read_active(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 1); + uint32_t value = 0; + unsigned int i; + + /* Loop over all IRQs affected by this read */ + for ( i = 0; i < len * 8; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + if ( irq->active ) + value |= (1U << i); + + vgic_put_irq(vcpu->domain, irq); + } + + return value; +} + +/* + * We don't actually support clearing the active state of an IRQ (yet). + * However there is a chance that most guests use this for initialization. + * We check whether this MMIO access would actually affect any active IRQ, + * and only print our warning in this case. So clearing already non-active + * IRQs would not be moaned about in the logs. + */ +void vgic_mmio_write_cactive(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 1); + unsigned int i; + bool bail_out = false; + + for_each_set_bit( i, &val, len * 8 ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + /* + * If we know that the IRQ is active or we can't be sure about + * it (because it is currently in a CPU), log the not properly + * emulated MMIO access. + */ + if ( irq->active || irq->vcpu ) + { + gdprintk(XENLOG_ERR, + "%pv: vGICD: IRQ%d: clearing active state not supported\n", + vcpu, irq->intid); + bail_out = true; + } + + vgic_put_irq(vcpu->domain, irq); + if ( bail_out ) + return; + } +} + +/* + * We don't actually support setting the active state of an IRQ (yet). + * We check whether this MMIO access would actually affect any non-active IRQ, + * and only print our warning in this case. + */ +void vgic_mmio_write_sactive(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 1); + unsigned int i; + bool bail_out = false; + + for_each_set_bit( i, &val, len * 8 ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + /* + * If we know that the IRQ is not active or we can't be sure about + * it (because it is currently in a CPU), log the not properly + * emulated MMIO access. + */ + if ( !irq->active || irq->vcpu ) + { + gdprintk(XENLOG_ERR, + "%pv: vGICD: IRQ%d: setting active state not supported\n", + vcpu, irq->intid); + bail_out = true; + } + + vgic_put_irq(vcpu->domain, irq); + if ( bail_out ) + return; + } +} + static int match_region(const void *key, const void *elt) { const unsigned int offset = (unsigned long)key; diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h index 4465f3b7e5..8604720628 100644 --- a/xen/arch/arm/vgic/vgic-mmio.h +++ b/xen/arch/arm/vgic/vgic-mmio.h @@ -118,6 +118,17 @@ void vgic_mmio_write_cpending(struct vcpu *vcpu, paddr_t addr, unsigned int len, unsigned long val); +unsigned long vgic_mmio_read_active(struct vcpu *vcpu, + paddr_t addr, unsigned int len); + +void vgic_mmio_write_cactive(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + +void vgic_mmio_write_sactive(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev); #endif From patchwork Mon Mar 5 16:03:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130694 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2854963lja; Mon, 5 Mar 2018 08:08:07 -0800 (PST) X-Google-Smtp-Source: AG47ELuEokd30lsGRHEv+/wsH7oJx7mLI4CLmFzXVHR5QZAZ68ieBnHE+3O9/pczGrU0LNmEEHXP X-Received: by 10.107.163.78 with SMTP id m75mr14606829ioe.26.1520266087624; Mon, 05 Mar 2018 08:08:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266087; cv=none; d=google.com; s=arc-20160816; b=S4IMXM3nZM8q111LMX7C6+0mLI9Kij4huhj2WSdoFr7Y7bRM81w3TfG11EvZzBRtFM l55RCAm5jEmo6N1cNPKAdH0b8GY8ZM1YrHCPw2hPPzubr2EIauYbNibcu9Fb3sHUsJwW MSdcr+JbnSXP7TupQoNnmsniR6KbP/vCCkeVAUU5p3ckKNN3kBVGlXv7sVGtVpAv95Er mXuopnfbD6JSYzAhpmDxwUG9kfrYxHP+/mwTUp15pCIMrZdNFK/HQjElZz5cVtZjY3Xk yOtdhj8N2ZbWPfcrLKcQdN9fzptVMLP3wBRq6xxXfNNx06ECaBj+HBGnUORW4rKmjYGS umhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=sP0HsF5EZcDA4uksKZliXStgY6KSy1CyXWk4I0kFEPk=; b=mRCDhqIoCDxEMQK6JDVEb1sc6US3IU8qNz0LlqOY5cLCEzoLMOz4xHCg2eCUK+OIoC cN1uEi7I/YJMDOkMMho4Q4+z5nJcF+J0lDY6cblLuuvdIVM5lhfL+fcErBL0/RMH4p8m P6CrKnYFnGxd+/KItNEBzP+w1cSCbT+M0ZNrE5WoUtum3a0J185h2A4HfoeqolIi0j72 FhFyhqUIbLAoaTKus/NPsDlCGFz7kyqKJR4afM/pKXJKS9JeCasvlPGW94zyNjN7E9wl B/3azNAbr29wZClDHlxY1nUkLq2amf6lR5SKi7ng/RMt4bxK/KUcRCpr8lCKYqaPk0gb g1dQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Y2VWGj7t; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.05.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:05:03 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:58 +0000 Message-Id: <20180305160415.16760-41-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 40/57] ARM: new VGIC: Add PRIORITY registers handlers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The priority register handlers are shared between the v2 and v3 emulation, so their implementation goes into vgic-mmio.c, to be easily referenced from the v3 emulation as well later. There is a corner case when we change the priority of a pending interrupt which we don't handle at the moment. This is based on Linux commit dd238ec2b87b, written by Andre Przywara. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - use 32 bit register types xen/arch/arm/vgic/vgic-mmio-v2.c | 2 +- xen/arch/arm/vgic/vgic-mmio.c | 47 ++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic-mmio.h | 7 ++++++ xen/arch/arm/vgic/vgic.h | 2 ++ 4 files changed, 57 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index c93455fbb2..29db9dec6f 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -98,7 +98,7 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { vgic_mmio_read_active, vgic_mmio_write_cactive, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_IPRIORITYR, - vgic_mmio_read_raz, vgic_mmio_write_wi, 8, + vgic_mmio_read_priority, vgic_mmio_write_priority, 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ITARGETSR, vgic_mmio_read_raz, vgic_mmio_write_wi, 8, diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c index c44d67082f..538f08bc66 100644 --- a/xen/arch/arm/vgic/vgic-mmio.c +++ b/xen/arch/arm/vgic/vgic-mmio.c @@ -384,6 +384,53 @@ void vgic_mmio_write_sactive(struct vcpu *vcpu, } } +unsigned long vgic_mmio_read_priority(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 8); + unsigned int i; + uint32_t val = 0; + + for ( i = 0; i < len; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + val |= (uint32_t)irq->priority << (i * 8); + + vgic_put_irq(vcpu->domain, irq); + } + + return val; +} + +/* + * We currently don't handle changing the priority of an interrupt that + * is already pending on a VCPU. If there is a need for this, we would + * need to make this VCPU exit and re-evaluate the priorities, potentially + * leading to this interrupt getting presented now to the guest (if it has + * been masked by the priority mask before). + */ +void vgic_mmio_write_priority(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 8); + unsigned int i; + unsigned long flags; + + for ( i = 0; i < len; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + spin_lock_irqsave(&irq->irq_lock, flags); + /* Narrow the priority range to what we actually support */ + irq->priority = (val >> (i * 8)) & GENMASK(7, 8 - VGIC_PRI_BITS); + spin_unlock_irqrestore(&irq->irq_lock, flags); + + vgic_put_irq(vcpu->domain, irq); + } +} + static int match_region(const void *key, const void *elt) { const unsigned int offset = (unsigned long)key; diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h index 8604720628..e3f9029344 100644 --- a/xen/arch/arm/vgic/vgic-mmio.h +++ b/xen/arch/arm/vgic/vgic-mmio.h @@ -129,6 +129,13 @@ void vgic_mmio_write_sactive(struct vcpu *vcpu, paddr_t addr, unsigned int len, unsigned long val); +unsigned long vgic_mmio_read_priority(struct vcpu *vcpu, + paddr_t addr, unsigned int len); + +void vgic_mmio_write_priority(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev); #endif diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index 68e205d10a..b294b04391 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -20,6 +20,8 @@ #define PRODUCT_ID_XEN 0x58 /* ASCII code X */ #define IMPLEMENTER_ARM 0x43b +#define VGIC_PRI_BITS 5 + #define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS) static inline bool irq_is_pending(struct vgic_irq *irq) From patchwork Mon Mar 5 16:03:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130664 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853668lja; Mon, 5 Mar 2018 08:07:04 -0800 (PST) X-Google-Smtp-Source: AG47ELtdVLMGMEbHubdI6JGVy1lM4OOvRfdhUmcAG1Zlr/1Ojj6p9ukr4mmccwtKVN2Y2a5DJVZl X-Received: by 10.36.148.204 with SMTP id j195mr13944018ite.1.1520266024666; Mon, 05 Mar 2018 08:07:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266024; cv=none; d=google.com; s=arc-20160816; b=pG6YOxHEP6QJX184PI79ipx8iraDccTlCBZXnxJykK9r9c7ZgXFQ9mQjwiHWUfZA6K w8rDfbqwA6ErcCNJIwV7RPA1Qc1mTyy4cPoY1+2t+Q80O2KebME30tve+42VK0RVUxqo VcUmMaIzFIv04hRTtEFI04X8IZlTdPHPs248s6jN3GPXuGUALPmXGIt2VKIwRuF2lCoL hL5Oem7MKwJqcoue7/QavcE1PGCtuRtt5x7XNNILCBt6gonockZo9/Ni6ok5KUHHBatL g2LRflLmWCJ+JqflRB8GQoI9yDQBFAgEMkE4orhtwMGWhqgOs8+2CJ3kpa/YfG3dcSEX 2eNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=xehEk7WoXV7zjtZMCoH1iIjhrXUSSDLwv4ipI89d+8U=; b=VA0V0sHkJAI+XOwZDOkL0BiC7gzuuOd0W+1cVzEsHC7jT/e/j/taCz10ocFasn87Wu QdaDqqbYMvdP4w3Neg/q50ErbtghLUCuqPkQowjYkYHm3pr2QOu8UnDGfYbcQrvcepLe uv55BuXKgx0ACxjDHeRljSElSmS1hS+jTbK/yeWF3z8uiJ0wVjsU3UocmPzw6eyEVEm+ 2varG9hcuDOU1nWBUlxznfqf0yGahcFceVm76PGOZEh3KwEM8Avf67Pj++NgWEW/CixF niOxwqEVXsEjV/JyfSUw2PIN8KxYfJGQmgM3C/DL0jSbqThYoP+G1eD/ghzDCNpxlrk0 LZHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=EariiYjc; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.05.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:05:04 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:59 +0000 Message-Id: <20180305160415.16760-42-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 41/57] ARM: new VGIC: Add CONFIG registers handlers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The config register handlers are shared between the v2 and v3 emulation, so their implementation goes into vgic-mmio.c, to be easily referenced from the v3 emulation as well later. This is based on Linux commit 79717e4ac09c, written by Andre Przywara. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- Changelog RFC ... v1: - use C99 data types xen/arch/arm/vgic/vgic-mmio-v2.c | 2 +- xen/arch/arm/vgic/vgic-mmio.c | 54 ++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic-mmio.h | 7 ++++++ 3 files changed, 62 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index 29db9dec6f..d19ddd3f1e 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -104,7 +104,7 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { vgic_mmio_read_raz, vgic_mmio_write_wi, 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICFGR, - vgic_mmio_read_raz, vgic_mmio_write_wi, 2, + vgic_mmio_read_config, vgic_mmio_write_config, 2, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_LENGTH(GICD_SGIR, vgic_mmio_read_raz, vgic_mmio_write_wi, 4, diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c index 538f08bc66..31f7cf706b 100644 --- a/xen/arch/arm/vgic/vgic-mmio.c +++ b/xen/arch/arm/vgic/vgic-mmio.c @@ -431,6 +431,60 @@ void vgic_mmio_write_priority(struct vcpu *vcpu, } } +unsigned long vgic_mmio_read_config(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 2); + uint32_t value = 0; + int i; + + for ( i = 0; i < len * 4; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + if ( irq->config == VGIC_CONFIG_EDGE ) + value |= (2U << (i * 2)); + + vgic_put_irq(vcpu->domain, irq); + } + + return value; +} + +void vgic_mmio_write_config(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 2); + int i; + unsigned long flags; + + for ( i = 0; i < len * 4; i++ ) + { + struct vgic_irq *irq; + + /* + * The configuration cannot be changed for SGIs in general, + * for PPIs this is IMPLEMENTATION DEFINED. The arch timer + * code relies on PPIs being level triggered, so we also + * make them read-only here. + */ + if ( intid + i < VGIC_NR_PRIVATE_IRQS ) + continue; + + irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + spin_lock_irqsave(&irq->irq_lock, flags); + + if ( test_bit(i * 2 + 1, &val) ) + irq->config = VGIC_CONFIG_EDGE; + else + irq->config = VGIC_CONFIG_LEVEL; + + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(vcpu->domain, irq); + } +} + static int match_region(const void *key, const void *elt) { const unsigned int offset = (unsigned long)key; diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h index e3f9029344..bbf0d181ae 100644 --- a/xen/arch/arm/vgic/vgic-mmio.h +++ b/xen/arch/arm/vgic/vgic-mmio.h @@ -136,6 +136,13 @@ void vgic_mmio_write_priority(struct vcpu *vcpu, paddr_t addr, unsigned int len, unsigned long val); +unsigned long vgic_mmio_read_config(struct vcpu *vcpu, + paddr_t addr, unsigned int len); + +void vgic_mmio_write_config(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev); #endif From patchwork Mon Mar 5 16:04:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130681 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853994lja; Mon, 5 Mar 2018 08:07:19 -0800 (PST) X-Google-Smtp-Source: AG47ELu5qkoK/RNYvjMY46K0ZKFqysmKsh4xxks6nOipHea3CF0kEu1TopLRxOu7o5rf4REEOw2E X-Received: by 10.36.222.214 with SMTP id d205mr14044412itg.125.1520266038915; Mon, 05 Mar 2018 08:07:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266038; cv=none; d=google.com; s=arc-20160816; b=yCDlxzTOt214ves07H3NjfeGa57GkWLmPcCykygfdiTs4xTC3B9FEswoSt4K4va1WI rb0XP5f9BTFTR461xHpX4mNYsSVOpL2PhpmHXqs4uZLHVdcvb7FaI8rIgHdTvyjjbBT/ jR1ssUThHsuG1WqTOZ/27vJCDowvpRrp4txQnKM+jFZwl1iDpjz/OWdSgk4nt2wwuar7 dnETuL9MsAXogsyb45DrZEgu8ylZay2qA1a9v3KikiFVqmi6jCQGbVBg2eC73CqfRxf8 oqq8uM+genCU6qJMvCLMyKCCnnWVSuSL8FyyxCoS9l0SL9ZlhYxmmPTvHzP+bI9Kennv Z18A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=oQkhcdV24sOForAsrsJHyezf+pcLeeuc58Q0SUTqGmg=; b=yrRnJAVSAukkabra2ov6NtUpbevX9jqn3jy7sbT0vhZEKLxd/K61dXk/I+/Dn5uJau +Bu19/e11l3azTgRHsPSI5l01VnG54FNXyGW4OVBxK9kUAvZyPOCtJFKH7CnKKtrouQo L4FI9gdbx6Yw6nI3ONMSz94eUhSF5UfqHDgFJY+hpTRcs/wH1b//MWEEi4D66Voi8a5/ fLI9VMeaDZFc33jXGzU2TYK0c0e09qi5/GPvtybb7qgLzP0+f18zYfZGhqmgSYz1m/1c TiTezZrbTpBuYyVErp1annyq25odwJ6SK1seavLyCm9Sc2G4P4gz5F46nwZWoQNmb13x HpBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=WpXgrbzA; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.05.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:05:05 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:04:00 +0000 Message-Id: <20180305160415.16760-43-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 42/57] ARM: new VGIC: Add TARGET registers handlers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The target register handlers are v2 emulation specific, so their implementation lives entirely in vgic-mmio-v2.c. We copy the old VGIC behaviour of assigning an IRQ to the first VCPU set in the target mask instead of making it possibly pending on multiple VCPUs. We update the physical affinity of a hardware mapped vIRQ on the way. This is based on Linux commit 2c234d6f1826, written by Andre Przywara. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - propagate affinity changes to hardware mapped IRQs xen/arch/arm/vgic/vgic-mmio-v2.c | 64 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 63 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index d19ddd3f1e..01c6a7198c 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -72,6 +72,68 @@ static void vgic_mmio_write_v2_misc(struct vcpu *vcpu, } } +static unsigned long vgic_mmio_read_target(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 8); + uint32_t val = 0; + unsigned int i; + + for ( i = 0; i < len; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + val |= (uint32_t)irq->targets << (i * 8); + + vgic_put_irq(vcpu->domain, irq); + } + + return val; +} + +static void vgic_mmio_write_target(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 8); + uint8_t cpu_mask = GENMASK(vcpu->domain->max_vcpus - 1, 0); + unsigned int i; + unsigned long flags; + + /* GICD_ITARGETSR[0-7] are read-only */ + if ( intid < VGIC_NR_PRIVATE_IRQS ) + return; + + for ( i = 0; i < len; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, NULL, intid + i); + struct irq_desc *desc; + + spin_lock_irqsave(&irq->irq_lock, flags); + + irq->targets = (val >> (i * 8)) & cpu_mask; + if ( irq->targets ) + { + irq->target_vcpu = vcpu->domain->vcpu[ffs(irq->targets) - 1]; + if ( irq->hw ) + desc = irq_to_desc(irq->hwintid); + else + desc = NULL; + } + else { + irq->target_vcpu = NULL; + desc = NULL; + } + + spin_unlock_irqrestore(&irq->irq_lock, flags); + + if ( desc ) + vgic_update_hardware_irq(desc, irq); + + vgic_put_irq(vcpu->domain, irq); + } +} + static const struct vgic_register_region vgic_v2_dist_registers[] = { REGISTER_DESC_WITH_LENGTH(GICD_CTLR, vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc, 12, @@ -101,7 +163,7 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { vgic_mmio_read_priority, vgic_mmio_write_priority, 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ITARGETSR, - vgic_mmio_read_raz, vgic_mmio_write_wi, 8, + vgic_mmio_read_target, vgic_mmio_write_target, 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICFGR, vgic_mmio_read_config, vgic_mmio_write_config, 2, From patchwork Mon Mar 5 16:04:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130663 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853658lja; Mon, 5 Mar 2018 08:07:04 -0800 (PST) X-Google-Smtp-Source: AG47ELu3O5s1vwN6tIfzm4q3NRFODwEbDKp47/vodBHekELD0Sm71WD86OGaxgNK5YTUtZGo/LE4 X-Received: by 10.36.13.8 with SMTP id 8mr15137495itx.42.1520266024227; Mon, 05 Mar 2018 08:07:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266024; cv=none; d=google.com; s=arc-20160816; b=yQEQYrw5jChbYQOG1+gs+BDNIt3n/rSuujvd0XtfA6UY39yvDc+3MmujU5wSF8PuSM m/Qf/lAnLQRIo5GfjNlsxTvmRNBiUadPvZR6G6v3YcdA52a8rd10uy5bYo8VHMJa/95y bvLGiBLHWhDS6iH+hl+YJc/O3B46M3mHQ3jOQmEPelaAOwFNQNqUsMka0BDtWjtDKUk+ TJ7vZORgmq+KnglLa15V05ameo5Ic8VeUw9q/bVRtP2cO70I57VISnFGRpin8K+09tGw BgaVnGdDsAJoH4aey+5u6dp45NbTE7qIr1fmeF21Ffj+5defxKHbPf3LYtFrv6/HdEk+ KZFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=dTTJRwvoGxv+dOM1FSKM4HfxcjvakQXIoqsfRfgXeJA=; b=JMc8I/vXe2LudlLhlfZ13tyeClDbXNq8JnSCnqYkrMKVSiGXSydqeAGR5sErVN/sOT aHop4Ttn5kdywEY0GzSrviCq/f6jeSjPWa/H00E2GHosgagvhlzCjYuUcqlrfNPpRrdU 1NXDgs1aP64LGw3ExiDOS0e7dDglgwJ9DtcHtwNODMvVj/lhVrCV2b9vK8QP3UJd1ZZX wsHtrG+7cjLGI7Axttl8H/GLNNqx1C84kEEn3p+00aV+TAxA2WMD3vr0KtVACV9GSDzx oPPThd5voNIYmyIyIG7Ma1lBWejzyZbaGL7jkFAQFifB5S0J/S6mTL73aNK3cNTtH3za wyFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=H9bYIpwF; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.05.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:05:06 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:04:01 +0000 Message-Id: <20180305160415.16760-44-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 43/57] ARM: new VGIC: Add SGIR register handler X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Triggering an IPI via this register is v2 specific, so the implementation lives entirely in vgic-mmio-v2.c. This is based on Linux commit 55cc01fb9004, written by Andre Przywara. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - use symbolic names instead of magic values - iterates over set bits instead of every VCPU xen/arch/arm/vgic/vgic-mmio-v2.c | 47 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 45 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index 01c6a7198c..5f1fdb9a70 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -72,6 +72,49 @@ static void vgic_mmio_write_v2_misc(struct vcpu *vcpu, } } +static void vgic_mmio_write_sgir(struct vcpu *source_vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + struct domain *d = source_vcpu->domain; + unsigned int nr_vcpus = d->max_vcpus; + unsigned int intid = val & GICD_SGI_INTID_MASK; + unsigned long targets = (val & GICD_SGI_TARGET_MASK) >> + GICD_SGI_TARGET_SHIFT; + unsigned int vcpu_id; + + switch ( val & GICD_SGI_TARGET_LIST_MASK ) + { + case GICD_SGI_TARGET_LIST: /* as specified by targets */ + targets &= GENMASK(nr_vcpus, 0); /* limit to existing VCPUs */ + break; + case GICD_SGI_TARGET_OTHERS: + targets = GENMASK(nr_vcpus, 0); /* all, ... */ + targets &= ~(1U << source_vcpu->vcpu_id); /* but self */ + break; + case GICD_SGI_TARGET_SELF: /* this very vCPU only */ + targets = (1U << source_vcpu->vcpu_id); + break; + case 0x3: /* reserved */ + return; + } + + for_each_set_bit( vcpu_id, &targets, 8 ) + { + struct vcpu *vcpu = d->vcpu[vcpu_id]; + struct vgic_irq *irq = vgic_get_irq(d, vcpu, intid); + unsigned long flags; + + spin_lock_irqsave(&irq->irq_lock, flags); + + irq->pending_latch = true; + irq->source |= 1U << source_vcpu->vcpu_id; + + vgic_queue_irq_unlock(d, irq, flags); + vgic_put_irq(d, irq); + } +} + static unsigned long vgic_mmio_read_target(struct vcpu *vcpu, paddr_t addr, unsigned int len) { @@ -128,7 +171,7 @@ static void vgic_mmio_write_target(struct vcpu *vcpu, spin_unlock_irqrestore(&irq->irq_lock, flags); if ( desc ) - vgic_update_hardware_irq(desc, irq); + vgic_sync_hardware_irq(vcpu->domain, desc, irq); vgic_put_irq(vcpu->domain, irq); } @@ -169,7 +212,7 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { vgic_mmio_read_config, vgic_mmio_write_config, 2, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_LENGTH(GICD_SGIR, - vgic_mmio_read_raz, vgic_mmio_write_wi, 4, + vgic_mmio_read_raz, vgic_mmio_write_sgir, 4, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_LENGTH(GICD_CPENDSGIR, vgic_mmio_read_raz, vgic_mmio_write_wi, 16, From patchwork Mon Mar 5 16:04:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130657 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853593lja; Mon, 5 Mar 2018 08:07:01 -0800 (PST) X-Google-Smtp-Source: AG47ELvBx5lvJ+PohJV57L6mnh586H0sc8pOkfYPvoEx2wQa8eFTD8pVjgnw4gqTeWWu+lyeYvLI X-Received: by 10.36.105.84 with SMTP id e81mr13739345itc.123.1520266021381; Mon, 05 Mar 2018 08:07:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266021; cv=none; d=google.com; s=arc-20160816; b=gK70yjHe9YHWuxU3lJSyqEcVcRb1jy0mLMe68ZERau6HnVdtphbqebAMxr+/bqW/Kw v57AM9fkO68BeSPqQBB1sahu0RXCE5XSvUwfYP9OLIsjVWm9SUJ7bGYNdSZMmA/G7muF UtqJ4NYIsDEZqnRs9sutLA/mJmB9IVSAyEQwbJREqX8KPHBD8DoULXdXIkr/z6j1dMt9 9jqF2Qw1USgW1Sqaf020fQ5BkX/AdwXmudcyVhXmjHO8+hzBaqvrspnTx+Amge41sxdy ZDSCsaggX2sCENvYwppO/Y3kdgKU9Fz8VjzxMkZi8EPtbl09hZ/tuOfubAzJu5X3TaZZ jBVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=4SnVu72MZ08Bhfrxk5wLWDaoS6Uj2MonlN+ikPNRpGc=; b=M29C6v4JVYgwXxIo6PVd8EjBfuiNY/Jwi/GxuDG4Yw3Rj8riMlCmWTfBz/RMhLMVtE 3NW1KNKwaIzXZkcJCl68O6poSMXyZtCa0XvNJv5rzz3MMHee5+FdYTWhKRTJwoLuCpyu 44hOJxxwOVVmoUwqWzgCUIWprhM+FvETENpWW4ey8yiXzHDMfj+Wn2kVv0J74k9yTQCN cFt05b2Hh5swYJhP92A4To3LvWQNqX8E95bxzYYzBnsgF4yZYF3pIuz1qfu/N8mxNGFv HYxU0R7pq5p1EPt/RFJ/05flL+1rJj6xsV2m1CawVPVnjjx9hZqM4Qzemecq8AVNn7z3 WUnA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=BZ4QhB0U; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.05.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:05:07 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:04:02 +0000 Message-Id: <20180305160415.16760-45-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 44/57] ARM: new VGIC: Add SGIPENDR register handlers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" As this register is v2 specific, its implementation lives entirely in vgic-mmio-v2.c. This register allows setting the source mask of an IPI. This is based on Linux commit ed40213ef9b0, written by Andre Przywara. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- Changelog RFC ... v1: - use C99 and unsigned data types xen/arch/arm/vgic/vgic-mmio-v2.c | 81 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index 5f1fdb9a70..dd9857e8a6 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -177,6 +177,83 @@ static void vgic_mmio_write_target(struct vcpu *vcpu, } } +static unsigned long vgic_mmio_read_sgipend(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 8); + uint32_t val = 0; + unsigned int i; + + ASSERT(intid < VGIC_NR_SGIS); + + for ( i = 0; i < len; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + val |= (uint32_t)irq->source << (i * 8); + + vgic_put_irq(vcpu->domain, irq); + } + + return val; +} + +static void vgic_mmio_write_sgipendc(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 8); + unsigned int i; + unsigned long flags; + + ASSERT(intid < VGIC_NR_SGIS); + + for ( i = 0; i < len; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + spin_lock_irqsave(&irq->irq_lock, flags); + + irq->source &= ~((val >> (i * 8)) & 0xff); + if ( !irq->source ) + irq->pending_latch = false; + + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(vcpu->domain, irq); + } +} + +static void vgic_mmio_write_sgipends(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 8); + unsigned int i; + unsigned long flags; + + ASSERT(intid < VGIC_NR_SGIS); + + for ( i = 0; i < len; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + spin_lock_irqsave(&irq->irq_lock, flags); + + irq->source |= (val >> (i * 8)) & 0xff; + + if ( irq->source ) + { + irq->pending_latch = true; + vgic_queue_irq_unlock(vcpu->domain, irq, flags); + } + else + { + spin_unlock_irqrestore(&irq->irq_lock, flags); + } + vgic_put_irq(vcpu->domain, irq); + } +} + static const struct vgic_register_region vgic_v2_dist_registers[] = { REGISTER_DESC_WITH_LENGTH(GICD_CTLR, vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc, 12, @@ -215,10 +292,10 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { vgic_mmio_read_raz, vgic_mmio_write_sgir, 4, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_LENGTH(GICD_CPENDSGIR, - vgic_mmio_read_raz, vgic_mmio_write_wi, 16, + vgic_mmio_read_sgipend, vgic_mmio_write_sgipendc, 16, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), REGISTER_DESC_WITH_LENGTH(GICD_SPENDSGIR, - vgic_mmio_read_raz, vgic_mmio_write_wi, 16, + vgic_mmio_read_sgipend, vgic_mmio_write_sgipends, 16, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), }; From patchwork Mon Mar 5 16:04:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130699 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2855779lja; 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.05.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:05:08 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:04:03 +0000 Message-Id: <20180305160415.16760-46-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 45/57] ARM: new VGIC: Handle hardware mapped IRQs X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The VGIC supports virtual IRQs to be connected to a hardware IRQ, so when a guest EOIs the virtual interrupt, it affects the state of that corresponding interrupt on the hardware side at the same time. Implement the interface that the Xen arch/core code expects to connect the virtual and the physical world. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- Changelog RFC ... v1: - add ASSERT for hardware mapped IRQs being SPI only - check h/w IRQ matches before disconnecting xen/arch/arm/vgic/vgic.c | 71 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 5246d7c2e7..5bbf55da21 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -698,6 +698,77 @@ void vgic_kick_vcpus(struct domain *d) } } +struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, + unsigned int virq) +{ + struct irq_desc *desc = NULL; + struct vgic_irq *irq = vgic_get_irq(d, v, virq); + unsigned long flags; + + if ( !irq ) + return NULL; + + spin_lock_irqsave(&irq->irq_lock, flags); + if ( irq->hw ) + { + ASSERT(irq->hwintid >= VGIC_NR_PRIVATE_IRQS); + desc = irq_to_desc(irq->hwintid); + } + spin_unlock_irqrestore(&irq->irq_lock, flags); + + vgic_put_irq(d, irq); + + return desc; +} + +/* + * was: + * int kvm_vgic_map_phys_irq(struct vcpu *vcpu, u32 virt_irq, u32 phys_irq) + * int kvm_vgic_unmap_phys_irq(struct vcpu *vcpu, unsigned int virt_irq) + */ +int vgic_connect_hw_irq(struct domain *d, struct vcpu *vcpu, + unsigned int virt_irq, struct irq_desc *desc, + bool connect) +{ + struct vgic_irq *irq = vgic_get_irq(d, vcpu, virt_irq); + unsigned long flags; + int ret = 0; + + if ( !irq ) + return -EINVAL; + + spin_lock_irqsave(&irq->irq_lock, flags); + + if ( connect ) /* assign a mapped IRQ */ + { + /* The VIRQ should not be already enabled by the guest */ + if ( !irq->hw && !irq->enabled ) + { + irq->hw = true; + irq->hwintid = desc->irq; + } + else + ret = -EBUSY; + } + else /* remove a mapped IRQ */ + { + if ( desc && irq->hwintid != desc->irq ) + { + ret = -EINVAL; + } + else + { + irq->hw = false; + irq->hwintid = 0; + } + } + + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(d, irq); + + return ret; +} + static unsigned int translate_irq_type(bool is_level) { return is_level ? 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.05.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:05:09 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:04:04 +0000 Message-Id: <20180305160415.16760-47-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 46/57] ARM: new VGIC: Add event channel IRQ handling X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The Xen core/arch code relies on two abstracted functions to inject an event channel IRQ and to query its pending state. Implement those to query the state of the new VGIC implementation. Signed-off-by: Andre Przywara Acked-by: Julien Grall --- Changelog RFC ... v1: - add locking xen/arch/arm/vgic/vgic.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 5bbf55da21..0bf257c865 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -698,6 +698,29 @@ void vgic_kick_vcpus(struct domain *d) } } +void arch_evtchn_inject(struct vcpu *v) +{ + vgic_inject_irq(v->domain, v, v->domain->arch.evtchn_irq, true); +} + +bool vgic_evtchn_irq_pending(struct vcpu *v) +{ + struct vgic_irq *irq; + unsigned long flags; + bool pending; + + /* Does not work for LPIs. */ + ASSERT(!is_lpi(v->domain->arch.evtchn_irq)); + + irq = vgic_get_irq(v->domain, v, v->domain->arch.evtchn_irq); + spin_lock_irqsave(&irq->irq_lock, flags); + pending = irq_is_pending(irq); + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(v->domain, irq); + + return pending; +} + struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, unsigned int virq) { From patchwork Mon Mar 5 16:04:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130680 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853957lja; Mon, 5 Mar 2018 08:07:17 -0800 (PST) X-Google-Smtp-Source: AG47ELuBoDtqS04lglH0dZCrY3gZJNFbCBEV2DJrFAnCCVUFwfP63ORel0dB8odpJ19Z77+Cq8O9 X-Received: by 10.36.200.3 with SMTP id w3mr13702949itf.12.1520266037527; Mon, 05 Mar 2018 08:07:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266037; cv=none; d=google.com; s=arc-20160816; b=ez6OGEcu5amJGEsHcpitwyc+7YeXyhwiqNn1Q5LAhpmoig/QLgHysrtcP9hBA35Xog fOlkUBpRCD7yA5vgghafFCuJZ8heR8fW0IrqL83nLQfRDFyFmrZKQEB8NsRVX/oV8EKI GHm7OlWU0/6NEyfj7MZnxLTO+Uv+56kxbfwjcazlqRcYmyCNjKw/kypsF9CA2fdkCWLg xy3vRaLi5zdrfBmP39etntIIDl3mr0QczkBDcekDr+DalwXHTew+axjNB1RVhwAktpVu cNvfaBjFOWBs8VUVZOCZePQaWXJzcPUw5uXk60f/O0HCsNv9RC7r5TQ37R+nVR/Grs24 mgtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=TpVQ39BIvPgz8j//v0s7MwIOtPv74licmWAxj8Dxza0=; b=xNH6uUm/39uvti9/SokiaF70A7E5LMBv3spoQnUohBS74ykpgZE4JnCfUfSHnSx0xX FS5FBIlyv97CV59UaZ2kehdfdD66tFOluBGgJDstYSoHJT/OwmjB4ejpxZdSxoguqGdm Zxy5M6Ad0owEmqzeyDGH83NWw9Ofp6M/ygb69LyC1GHcKKqF+dgw/HXTnGJWRMhnRaLl zyiQxmviqvOI1gDWjjSt08/oWf/wPljrbNn01oRV0w+qfSQqcR90t3AirGV7fl1SNOOL ogwo8xxKgezguXUas4mNO4lB7qbDd+WysmnP/w2S574w5q9HBqmpNVgtjJ0GD/7PN8ze 85jw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=E1DU951m; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.05.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:05:10 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:04:05 +0000 Message-Id: <20180305160415.16760-48-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 47/57] ARM: new VGIC: Handle virtual IRQ allocation/reservation X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" To find an unused virtual IRQ number Xen uses a scheme to track used virtual IRQs. Implement this interface in the new VGIC to make the Xen core/arch code happy. This is actually somewhat VGIC agnostic, so is mostly a copy of the code from the old VGIC. But it has to live in the VGIC files, so we can't easily reuse the existing implementation. Signed-off-by: Andre Przywara Acked-by: Julien Grall --- Changelog RFC ... v1: - no changes xen/arch/arm/vgic/vgic.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 0bf257c865..e9ef992e1e 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -721,6 +721,50 @@ bool vgic_evtchn_irq_pending(struct vcpu *v) return pending; } +bool vgic_reserve_virq(struct domain *d, unsigned int virq) +{ + if ( virq >= vgic_num_irqs(d) ) + return false; + + return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs); +} + +int vgic_allocate_virq(struct domain *d, bool spi) +{ + int first, end; + unsigned int virq; + + if ( !spi ) + { + /* We only allocate PPIs. SGIs are all reserved */ + first = 16; + end = 32; + } + else + { + first = 32; + end = vgic_num_irqs(d); + } + + /* + * There is no spinlock to protect allocated_irqs, therefore + * test_and_set_bit may fail. If so retry it. + */ + do + { + virq = find_next_zero_bit(d->arch.vgic.allocated_irqs, end, first); + if ( virq >= end ) + return -1; + } while ( test_and_set_bit(virq, d->arch.vgic.allocated_irqs) ); + + return virq; +} + +void vgic_free_virq(struct domain *d, unsigned int virq) +{ + clear_bit(virq, d->arch.vgic.allocated_irqs); +} + struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, unsigned int virq) { From patchwork Mon Mar 5 16:04:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130690 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2854362lja; Mon, 5 Mar 2018 08:07:35 -0800 (PST) X-Google-Smtp-Source: AG47ELuYdU5cKjzmb3xA8dY7BTXZHh68znj/DRlJKmUIxuNAy5mhq90JynABkkwix0T5ofUAfOIx X-Received: by 10.107.21.131 with SMTP id 125mr17157312iov.74.1520266054887; Mon, 05 Mar 2018 08:07:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266054; cv=none; d=google.com; s=arc-20160816; b=NlwAVaNHK/HHsLG1okJ15hh5BSc2NDqedfmE8BoLlKKTgANFamnJ9XdsB6C9YPJO3M QmwAV8F3XchYoOMrJAs1ngQoGk0DJ+lSKNOZ1KS+Vlu2h+Bd3IUb8Dn/TQUdehvE4zmA ZtW+q4SHKgfxQ94loD8Yrplrc3Vd1mx/obbsFyOzNbotDiIXVa4DIgLCTY0sK2sHjYKh IMuU2t/uYXroWo5si9iTUr6m+uzIMnDvYlnLDvIufgU8mm5vsUmL55eilkqDcdml+4vm rppHaE1QVjzMeJU5Xzu+XCO/vHDGAlxhB0qbtZQ8LwMCOY+rs6/f+oX93PbytlbDBWMp YKPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=0MsOxb4eUekEUYDL0bFK3qSziM05CA8HtYhfZjr0Bho=; b=b0PRKg1Vt6+ozZSY2ardJlyDRN7PnSUNuijB8ZYAEipq0pLA1S4QmgO3LPnjdsObLx RnKywfFa04DLZb2CZiM3Ps9bBlYodB+OjHTo/NTfixDOedOwKgWQoXJc7saJXCfG+IOa cWe16bFM4zi4M8bMnaSt0OiDC72sxrMGwuYDW37fpnureLMhTp7AhGoLv5Qs/5kjQdyd xnM+ppH6ognjPSpKdxnint543J5+OMw5hy8h2+SzS27lyIvbML0PA7l0+v3iec09SGXu waPMoHov21xVwLDz7rOTS5Bdm+POzpvncUOVVmuyXiCaRJMWncmHiFvm5/kFKXDW8tdt U67g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=YugAoaCW; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.05.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:05:11 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:04:06 +0000 Message-Id: <20180305160415.16760-49-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 48/57] ARM: new VGIC: Dump virtual IRQ info X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" When we dump guest state on the Xen console, we also print the state of IRQs that are on a VCPU. Add the code to dump the state of an IRQ handled by the new VGIC. Signed-off-by: Andre Przywara Acked-by: Julien Grall --- Changelog RFC ... v1: - use proper locking - use one header line to announce active or pending IRQs xen/arch/arm/vgic/vgic.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index e9ef992e1e..2a2b8fd1eb 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -765,6 +765,31 @@ void vgic_free_virq(struct domain *d, unsigned int virq) clear_bit(virq, d->arch.vgic.allocated_irqs); } +void gic_dump_vgic_info(struct vcpu *v) +{ + struct vgic_cpu *vgic_cpu = &v->arch.vgic; + struct vgic_irq *irq; + unsigned long flags; + + spin_lock_irqsave(&v->arch.vgic.ap_list_lock, flags); + + if ( !list_empty(&vgic_cpu->ap_list_head) ) + printk(" active or pending interrupts queued:\n"); + + list_for_each_entry ( irq, &vgic_cpu->ap_list_head, ap_list ) + { + spin_lock(&irq->irq_lock); + printk(" %s %s irq %u: %spending, %sactive, %senabled\n", + irq->hw ? "hardware" : "virtual", + irq->config == VGIC_CONFIG_LEVEL ? "level" : "edge", + irq->intid, irq_is_pending(irq) ? "" : "not ", + irq->active ? "" : "not ", irq->enabled ? "" : "not "); + spin_unlock(&irq->irq_lock); + } + + spin_unlock_irqrestore(&v->arch.vgic.ap_list_lock, flags); +} + struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, unsigned int virq) { From patchwork Mon Mar 5 16:04:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130695 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2855386lja; Mon, 5 Mar 2018 08:08:28 -0800 (PST) X-Google-Smtp-Source: AG47ELsvjIchQMrCzWvAC8k6yaeTvTqkbhoVFnlJdaeh/+OrptKUM2zUCMVpkaokFKMwmGZpKi4H X-Received: by 10.36.31.21 with SMTP id d21mr5700302itd.71.1520266026500; Mon, 05 Mar 2018 08:07:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266026; cv=none; d=google.com; s=arc-20160816; b=vGrJPr8VItCOPsEG8DsufoyHs2uAjBvpYCoCOsv1p0w2gouDgY4V145Rt+eWC3gctz 5WujVCNp7V0YIu7igolkiCmIVFZLT2eXR2qLXCKlbfyjKYar1oLuHTdxai15X87mY3Lh Bblco6GLR9xU9lQiTThf561SwB2FeYLzY56qiP1cLvA8f7rXIt+2TEjDdIudwbRyJlGN iYOGg8FsS4ufp1G8+CHxhZDFHU5CLCOTGutosj6pHV8GPqgcHapXP4Wg6D1qaZxwB40a 2fnX0ggzWnVbCIxwMHuz6g5kaKgLDtpEUNbYj96xaEFgzqO291JcFDFMkAE7F3P9xP/x ydqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=KCXVxJDvKL90xACrmARlC9021RAT7aiEPeZVYo9cGUk=; b=NE4WeYGGoH4ZGOBMpOSNsfO9j9ilMMSpkrsAiqZEHcGvev5BQUxwaD1tipcvxpVRZz khsR8gI9n8RMEqDLhPnwzfoMSQKjiOk/y2ANVgwme6rpQ/TfQv04+Qvv0mAG4NoJgtt/ Gzm1WpV3BVKsHp5gexjlXpX3bMMHoh5queRL4gfaAsXQIP5ToR9I49LRK0ndGF3C5SRr M0OMSQK/GbrYruC5n+7M2aH8y5EIQGTgBvqr3iR+3KygXVQ+DSR1H7kBCLUOG+uCSvDS Z0JtA9jI1rfxyG5/sa7zHZdQ4zDwD7kZgOgnnNpp/abd/nu7KxWVlIZuD8dQwY148m+z 0LnQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=j9It5gZV; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.05.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:05:12 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:04:07 +0000 Message-Id: <20180305160415.16760-50-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 49/57] ARM: new VGIC: provide system register emulation stub X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The Xen arch code traps system registers writes from the guest and will relay anything GIC related to the VGIC. Since this affects only GICv3 (which we don't yet emulate), provide a stub implementation of vgic_emulate() for now. Signed-off-by: Andre Przywara Acked-by: Julien Grall --- Changelog RFC ... v1: - no changes xen/arch/arm/vgic/vgic.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 2a2b8fd1eb..e1952c872d 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -813,6 +813,13 @@ struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, return desc; } +bool vgic_emulate(struct cpu_user_regs *regs, union hsr hsr) +{ + ASSERT(current->domain->arch.vgic.version == GIC_V3); + + return false; +} + /* * was: * int kvm_vgic_map_phys_irq(struct vcpu *vcpu, u32 virt_irq, u32 phys_irq) From patchwork Mon Mar 5 16:04:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130670 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853758lja; Mon, 5 Mar 2018 08:07:08 -0800 (PST) X-Google-Smtp-Source: AG47ELsipWjWVnytMfYde8+RoAOin2NibmEKFT2en2IulSf6Cqmvt4GShoKxXKtAM+9iJwKEZNGa X-Received: by 10.107.24.194 with SMTP id 185mr18438691ioy.157.1520266028726; Mon, 05 Mar 2018 08:07:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266028; cv=none; d=google.com; s=arc-20160816; b=dXyGKNS/nPOFCAdvkh6ObBFYViT/qZnGa1ZhikjeBinqI0wPWHVy/SiJyWTdwj9dPr so59fqDF3pK70PCWwGzas9wVOqKedCbDmQQH7wxlLbz5eUr0MhfZZqMALkN8u5ztZP4d pQQZGb+IBp7G1TMQ0OOoV0J5LYu/gT2LjYQZBC0zn8U247oRRvNTix8MW0Gs6bDotl+o Zx2y8OOOB++jhYGph6g4mBKoBjGMWaM1KqpNsDHzsb01ueY5oifyzxGjJgPTLKOB8XjE VArDBWU/R1mGbQVjzvK2OwuqonY5Vf0QykwJEsXKxRDTXvXSG0bNy7ycHVk4az9BBQ0J HvSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=QPTMiWNLsbTDR4QUnJ6IynvcoDoz+90NPNhSTwkRlvs=; b=FWV27xSw9C895eAxoVwJk6ewGHJYLDJaCUNCR9eg9effZr+Uzlj7SsermlrjxroZqx Dc228V86sFWaTGeQPDMKc4+4/SN5W8vHbDtt42VAX1oHG9Xsal6pBqSeZpsmxj26Cuea Zjyay3tOlOAdAYJQ/ub3hgMDpbr8BcylRaLT7Vcq+f7FUQFUC1cUmfnEoSxbsw5L+Pm2 l119LVqkZQssGjd9rJRzNyiUZikZJpnykxRDCQOpozFkZK6BUOEXIcej6w/GgvqnZoMG BLxgHYiRF+WBooZ06aHMFWEOyeb1qi2Eq6fj+JNhxHUsy02JDPRQv2hiewnNR4+G5vwb IAUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=hSXm4arY; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.05.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:05:13 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:04:08 +0000 Message-Id: <20180305160415.16760-51-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 50/57] ARM: new VGIC: Implement arch_move_irqs() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" When a VCPU moves to another CPU, we need to adjust the target affinity of any hardware mapped vIRQs, to observe our "physical-follows-virtual" policy. Implement arch_move_irqs() to adjust the physical affinity of all hardware mapped vIRQs targetting this VCPU. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - actually implement arch_move_irqs() (instead of just stubbing it) xen/arch/arm/vgic/vgic.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index e1952c872d..5e767927c0 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -790,6 +790,48 @@ void gic_dump_vgic_info(struct vcpu *v) spin_unlock_irqrestore(&v->arch.vgic.ap_list_lock, flags); } +/** + * arch_move_irqs() - migrate the physical affinity of hardware mapped vIRQs + * @v: the vCPU, already assigned to the new pCPU + * + * arch_move_irqs() updates the physical affinity of all virtual IRQs + * targetting this given vCPU. This only affects hardware mapped IRQs. The + * new pCPU to target is already set in v->processor. + * This is called by the core code after a vCPU has been migrated to a new + * physical CPU. + */ +void arch_move_irqs(struct vcpu *v) +{ + struct domain *d = v->domain; + unsigned int i; + + /* We only target SPIs with this function */ + for ( i = 0; i < d->arch.vgic.nr_spis; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(d, NULL, i + VGIC_NR_PRIVATE_IRQS); + unsigned long flags; + irq_desc_t *desc; + + if ( !irq ) + continue; + + spin_lock_irqsave(&irq->irq_lock, flags); + + /* only vIRQs that are not on a vCPU yet , but targetting this vCPU */ + if ( irq->hw && !irq->vcpu && irq->target_vcpu == v) + desc = irq_to_desc(irq->hwintid); + else + desc = NULL; + + spin_unlock_irqrestore(&irq->irq_lock, flags); + + if ( desc ) + vgic_sync_hardware_irq(d, desc, irq); + + vgic_put_irq(d, irq); + } +} + struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, unsigned int virq) { From patchwork Mon Mar 5 16:04:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130673 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853811lja; Mon, 5 Mar 2018 08:07:11 -0800 (PST) X-Google-Smtp-Source: AG47ELup9AnWtwzqGFWcuH2hfRjT7Piom+I8orIZVEylB7RVe7HuGowvc9sVbV30bVbelGqYBE3X X-Received: by 10.36.221.212 with SMTP id t203mr13870194itf.54.1520266031182; Mon, 05 Mar 2018 08:07:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266031; cv=none; d=google.com; s=arc-20160816; b=yaoMiVtTeIfgyKCTAENyQTYg0hFcj3kB2nbdA1WNhUSKg6j+kanLxk4v1agjN1JF/P eoBCk1WvWWu8WF7hSl0tnCzGdkE/Fo8X7d7fSwjvnuB6KuBc4WiXbLcDp7BkIFrA4EMG gw2rmY65Uz7syl3oR3A2BEbTmYa3UnTt+FEzhoukcnZfyptN9cfr29GjjOz3r5YLP7vx 0OU35PWHCK6Nv8nZNf7iRMOchQMvrj+9S0foeuAca5jOai9ZLfUmaDmL+YPedxnbFDs+ zbNQ1suD3Z06T6bU1nIRk+x/ep/grYRVA7iVK/banME+I7Q4r9dgK/JReDi37w1yZywr eD+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=g0El2dypr6i1vWa1XndgR9lNb5q1DoLIBrNLgORtwr8=; b=0nisej4rMrvPBNSOZ0UOkiwrC3i7GSx3I6YpMKRo2EHMt3/RCD6nH8Te+Qk8tKtt21 3C4iWcmlTH1owE1O5yiyohZFB11cgx4Yp3vNGtv+G64Qm5V7ukhIwG7PtpJxFfVW3MYf Ghh23Vz1yeJ1xWK+27tdiUWtu7Z7idZHjP7xiP6/qoqyx7FOL08FQWnO9HVhYexau3PP bznGr5gDpTL0+JkMFjLi8SmTp2vhxh86xdm7C7I2nPldCn/rd9jqAtRbtQmztsLH2cuH ioOfWhR3enUQxe8hMnmtms0o1RlhEIBii4xeFpaVhB0TtO2vUiooMtWR3de4MSQhqfnB ntoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Yyxgpcce; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.05.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:05:13 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:04:09 +0000 Message-Id: <20180305160415.16760-52-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 51/57] ARM: new VGIC: Add preliminary stub implementation X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The ARM arch code requires an interrupt controller emulation to implement vgic_clear_pending_irqs(), although it is suspected that it is actually not necessary. Go with a stub for now to make the linker happy. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - split off from former patch, otherwise unchanged xen/arch/arm/vgic/vgic.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 5e767927c0..5d84a4d81a 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -790,6 +790,14 @@ void gic_dump_vgic_info(struct vcpu *v) spin_unlock_irqrestore(&v->arch.vgic.ap_list_lock, flags); } +void vgic_clear_pending_irqs(struct vcpu *v) +{ + /* + * TODO: It is unclear whether we really need this, so we might instead + * remove it on the caller site. + */ +} + /** * arch_move_irqs() - migrate the physical affinity of hardware mapped vIRQs * @v: the vCPU, already assigned to the new pCPU From patchwork Mon Mar 5 16:04:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130689 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2854347lja; Mon, 5 Mar 2018 08:07:34 -0800 (PST) X-Google-Smtp-Source: AG47ELtxiDqYxKpgsvpSa6SpVQlri1mMBP5dAGSRY+EtX+1dUXIOllgzESFPfeyslEf9npIqfsF7 X-Received: by 10.107.58.139 with SMTP id h133mr18518575ioa.250.1520266054149; Mon, 05 Mar 2018 08:07:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266054; cv=none; d=google.com; s=arc-20160816; b=YbfQ5YRfJ7TkxWn3VErxY4lguESft2S+qRJG0xOlbCZUsLACZ8SLZ7+YxJsIIQeo1P W5uPIebAqqfU/b90WrKsOOwjz9XN8i+jH235qoLglYjabu0ExmQaRnptMEVXwEcEKvsu XPyaDS6WVJuyj94jrd6VuECKndtx5cVXqMA6ee2wrLczu8wtVMbbGYbnKYP5QxareJaq ywJuLS6Bs14ftAj8hKuZJw9FKflPK+vuXP1TlsU2B6o4qMzg9S5FoZoGzn5MyRwGk2il qMk8ppjlZOt2i+m/5hMAQyS1V9bQrl3uRqxFEpIGMYHaHYX9G1aVy0zb+OB5rtCMpNqW w/Aw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=2Y3HCBAmFWb7ZVM0ylCSvVQ9O4upxQatDnbsXhcefRI=; b=xdEM9QolO52S+S+QffO0nJau++G5BjHuSQUCi0iTKRts5NrqlvaSusT5ML/8U4lysQ lj+UqYNHfbwt6rScJ3BwfN5+DxuJGEjp6oRgb8sWK1KsqKsu9gAEWp6JybK9g6v6XSOP J1iS/348xMxPWB/ZQBJjOoYbXApPNi20Oe1t6bTFD4CD5+9F+mMyCmyNVDy6YELVHXt/ 9Og3zi3ACUQSEvY1xoSlp6OM4WZEIELLxBhhquh1UmQhMgHZzGTq+O8tjPD3THanD9MA uBld5FxcnzQQbWD5FW3ej6bYHgU+nUBieqO3c/zcy1jnmBKhLt1Hj5TUFM0gAKiUXk/Q pMDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=QbbsL4fC; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.05.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:05:14 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:04:10 +0000 Message-Id: <20180305160415.16760-53-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 52/57] ARM: new VGIC: vgic-init: register VGIC X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" This patch implements the function which is called by Xen when it wants to register the virtual GIC. This also implements domain_max_vcpus() for the new VGIC, which reports back the maximum number of VCPUs a certain GIC model supports. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - split off definition of domain_max_vcpus() xen/arch/arm/vgic/vgic-init.c | 60 +++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic.c | 22 ++++++++++++++++ xen/arch/arm/vgic/vgic.h | 3 +++ 3 files changed, 85 insertions(+) create mode 100644 xen/arch/arm/vgic/vgic-init.c diff --git a/xen/arch/arm/vgic/vgic-init.c b/xen/arch/arm/vgic/vgic-init.c new file mode 100644 index 0000000000..d091c92ed0 --- /dev/null +++ b/xen/arch/arm/vgic/vgic-init.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2015, 2016 ARM Ltd. + * Imported from Linux ("new" KVM VGIC) and heavily adapted to Xen. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +#include "vgic.h" + +/* CREATION */ + +/** + * domain_vgic_register: create a virtual GIC + * @d: domain pointer + * @mmio_count: pointer to add number of required MMIO regions + * + * was: kvm_vgic_create + */ +int domain_vgic_register(struct domain *d, int *mmio_count) +{ + switch ( d->arch.vgic.version ) + { + case GIC_V2: + *mmio_count = 1; + break; + default: + BUG(); + } + + if ( d->max_vcpus > domain_max_vcpus(d) ) + return -E2BIG; + + d->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF; + d->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF; + d->arch.vgic.vgic_redist_base = VGIC_ADDR_UNDEF; + + return 0; +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 5d84a4d81a..f42092fec3 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -956,6 +956,28 @@ void vgic_sync_hardware_irq(struct domain *d, spin_unlock_irqrestore(&desc->lock, flags); } +unsigned int domain_max_vcpus(const struct domain *d) +{ + unsigned int vgic_vcpu_limit; + + switch ( d->arch.vgic.version ) + { +#ifdef CONFIG_HAS_GICV3 + case GIC_V3: + vgic_vcpu_limit = VGIC_V3_MAX_CPUS; + break; +#endif + case GIC_V2: + vgic_vcpu_limit = VGIC_V2_MAX_CPUS; + break; + default: + vgic_vcpu_limit = MAX_VIRT_CPUS; + break; + } + + return min_t(unsigned int, MAX_VIRT_CPUS, vgic_vcpu_limit); +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index b294b04391..f19dc9502f 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -20,6 +20,9 @@ #define PRODUCT_ID_XEN 0x58 /* ASCII code X */ #define IMPLEMENTER_ARM 0x43b +#define VGIC_ADDR_UNDEF INVALID_PADDR +#define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF) + #define VGIC_PRI_BITS 5 #define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS) From patchwork Mon Mar 5 16:04:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130693 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2854540lja; Mon, 5 Mar 2018 08:07:44 -0800 (PST) X-Google-Smtp-Source: AG47ELsDe6ucqe/8/A1mDzD8xZHXT/ttCuWQn1EDCTLa33nYVyMpG1SfExbaneCyfTWdrSWOz692 X-Received: by 10.107.22.1 with SMTP id 1mr18414599iow.238.1520266064744; Mon, 05 Mar 2018 08:07:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266064; cv=none; d=google.com; s=arc-20160816; b=QelkPgylye9AsXAIXTToJ/1CyOLlk3n9W4SeWm9j23mVEGeWXHWWCCOtz3KvIqZ2yA NyYzwr6Z0/R0Mc2J36WDQF0oJn8JOcblDf2tDB2RiP45tio7JxSg+mAu7LZRF47jGYPF +2dPXed/f23Twsq+8dbhn0Et+LO6sTZWEmC4CDGQtZgJbdNNAklotU96kRIvsaH3YNBZ cUdWYEfbFnpR8qN2Nw1LUFIZBRtxZK42xsiRXiAHfuuTdPqccuVj5M04h3zR+je7yf5s WE1BAO+N2Sv3HUsIbr76Nu1DPht6yhvPCLBJeIU8icbt7JgLcZ6Yo5KtcObYo5YKLLg9 7nyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=Vx1rX7UQIWllo21zxKR0t8G3vbfvw4CKJmWtb+FYMAA=; b=pnLXgzxBjsOgXln6XEkbkzMb3sgS7quDovewegms0KC6PT2I5ZzocVzUMmqzrv12U0 TQOoKb9YpVZaew0Ds7aoQZl5RcVuMpFQ6QZT/kR8MwhjLArEHs/fspd6MKCou5sadM25 k2IrL+P7ZaPLXeAtbUXB4WZ4pB/PBJgVoRlxPcOuMOm1/Afm+XgikQuhHO445STF3bUN C5+fjlqJBh5KYHiG1VGDV2iQcnsC0I0NkAa0wNfr+wFErVlSifj1IoNGdBRyoIHanKiC 6mzz8SabXqXsMa1CUA8oXkd2vA9QtKTPb9xBEReaNMv3cFURZ7rnk5mgBcgU7eUvXGhl A/5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ddqDt3ra; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.05.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:05:16 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:04:11 +0000 Message-Id: <20180305160415.16760-54-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 53/57] ARM: new VGIC: vgic-init: implement vgic_init X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" This patch allocates and initializes the data structures used to model the vgic distributor and virtual cpu interfaces. At that stage the number of IRQs and number of virtual CPUs is frozen. Implement the various functions that the Xen arch code is expecting to call during domain and VCPU setup to initialize the VGIC. Their prototypes are already in existing header files. This is based on Linux commit ad275b8bb1e6, written by Eric Auger. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - adapt to former changes - add missing comment line - extend commit message xen/arch/arm/vgic/vgic-init.c | 196 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 196 insertions(+) diff --git a/xen/arch/arm/vgic/vgic-init.c b/xen/arch/arm/vgic/vgic-init.c index d091c92ed0..8bc83f677b 100644 --- a/xen/arch/arm/vgic/vgic-init.c +++ b/xen/arch/arm/vgic/vgic-init.c @@ -20,6 +20,77 @@ #include "vgic.h" +/* + * Initialization rules: there are multiple stages to the vgic + * initialization, both for the distributor and the CPU interfaces. The basic + * idea is that even though the VGIC is not functional or not requested from + * user space, the critical path of the run loop can still call VGIC functions + * that just won't do anything, without them having to check additional + * initialization flags to ensure they don't look at uninitialized data + * structures. + * + * Distributor: + * + * - vgic_early_init(): initialization of static data that doesn't + * depend on any sizing information or emulation type. No allocation + * is allowed there. + * + * - vgic_init(): allocation and initialization of the generic data + * structures that depend on sizing information (number of CPUs, + * number of interrupts). Also initializes the vcpu specific data + * structures. Can be executed lazily for GICv2. + * + * CPU Interface: + * + * - kvm_vgic_vcpu_early_init(): initialization of static data that + * doesn't depend on any sizing information or emulation type. No + * allocation is allowed there. + */ + +/** + * vgic_vcpu_early_init() - Initialize static VGIC VCPU data structures + * @vcpu: The VCPU whose VGIC data structures whould be initialized + * + * Only do initialization, but do not actually enable the VGIC CPU interface + * yet. + */ +static void vgic_vcpu_early_init(struct vcpu *vcpu) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic; + int i; + + INIT_LIST_HEAD(&vgic_cpu->ap_list_head); + spin_lock_init(&vgic_cpu->ap_list_lock); + + /* + * Enable and configure all SGIs to be edge-triggered and + * configure all PPIs as level-triggered. + */ + for ( i = 0; i < VGIC_NR_PRIVATE_IRQS; i++ ) + { + struct vgic_irq *irq = &vgic_cpu->private_irqs[i]; + + INIT_LIST_HEAD(&irq->ap_list); + spin_lock_init(&irq->irq_lock); + irq->intid = i; + irq->vcpu = NULL; + irq->target_vcpu = vcpu; + irq->targets = 1U << vcpu->vcpu_id; + atomic_set(&irq->refcount, 0); + if ( vgic_irq_is_sgi(i) ) + { + /* SGIs */ + irq->enabled = 1; + irq->config = VGIC_CONFIG_EDGE; + } + else + { + /* PPIs */ + irq->config = VGIC_CONFIG_LEVEL; + } + } +} + /* CREATION */ /** @@ -50,6 +121,131 @@ int domain_vgic_register(struct domain *d, int *mmio_count) return 0; } +/* INIT/DESTROY */ + +/** + * domain_vgic_init: initialize the dist data structures + * @d: domain pointer + * @nr_spis: number of SPIs + */ +int domain_vgic_init(struct domain *d, unsigned int nr_spis) +{ + struct vgic_dist *dist = &d->arch.vgic; + int i, ret; + + /* Limit the number of virtual SPIs supported to (1020 - 32) = 988 */ + if ( nr_spis > (1020 - NR_LOCAL_IRQS) ) + return -EINVAL; + + dist->nr_spis = nr_spis; + dist->spis = xzalloc_array(struct vgic_irq, nr_spis); + if ( !dist->spis ) + return -ENOMEM; + + /* + * In the following code we do not take the irq struct lock since + * no other action on irq structs can happen while the VGIC is + * not initialized yet: + * If someone wants to inject an interrupt or does a MMIO access, we + * require prior initialization in case of a virtual GICv3 or trigger + * initialization when using a virtual GICv2. + */ + for ( i = 0; i < nr_spis; i++ ) + { + struct vgic_irq *irq = &dist->spis[i]; + + irq->intid = i + VGIC_NR_PRIVATE_IRQS; + INIT_LIST_HEAD(&irq->ap_list); + spin_lock_init(&irq->irq_lock); + irq->vcpu = NULL; + irq->target_vcpu = NULL; + atomic_set(&irq->refcount, 0); + if ( dist->version == GIC_V2 ) + irq->targets = 0; + else + irq->mpidr = 0; + } + + INIT_LIST_HEAD(&dist->lpi_list_head); + spin_lock_init(&dist->lpi_list_lock); + + if ( dist->version == GIC_V2 ) + ret = vgic_v2_map_resources(d); + else + ret = -ENXIO; + + if ( ret ) + return ret; + + /* allocated_irqs() is used by Xen to find available vIRQs */ + d->arch.vgic.allocated_irqs = + xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_irqs(d))); + if ( !d->arch.vgic.allocated_irqs ) + return -ENOMEM; + + /* vIRQ0-15 (SGIs) are reserved */ + for ( i = 0; i < NR_GIC_SGI; i++ ) + set_bit(i, d->arch.vgic.allocated_irqs); + + return 0; +} + +/** + * vcpu_vgic_init() - Register VCPU-specific KVM iodevs + * was: kvm_vgic_vcpu_init() + * Xen: adding vgic_vx_enable() call + * @vcpu: pointer to the VCPU being created and initialized + */ +int vcpu_vgic_init(struct vcpu *vcpu) +{ + int ret = 0; + + vgic_vcpu_early_init(vcpu); + + if ( gic_hw_version() == GIC_V2 ) + vgic_v2_enable(vcpu); + else + ret = -ENXIO; + + return ret; +} + +void domain_vgic_free(struct domain *d) +{ + struct vgic_dist *dist = &d->arch.vgic; + int i, ret; + + for ( i = 0; i < dist->nr_spis; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(d, NULL, 32 + i); + + if ( !irq->hw ) + continue; + + ret = release_guest_irq(d, irq->hwintid); + if ( ret ) + dprintk(XENLOG_G_WARNING, + "d%u: Failed to release virq %u ret = %d\n", + d->domain_id, 32 + i, ret); + } + + dist->ready = false; + dist->initialized = false; + + xfree(dist->spis); + xfree(dist->allocated_irqs); + dist->nr_spis = 0; +} + +int vcpu_vgic_free(struct vcpu *vcpu) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic; + + INIT_LIST_HEAD(&vgic_cpu->ap_list_head); + + return 0; +} + /* * Local variables: * mode: C From patchwork Mon Mar 5 16:04:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130679 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2853933lja; 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.05.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:05:16 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:04:12 +0000 Message-Id: <20180305160415.16760-55-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 54/57] ARM: new VGIC: vgic-init: implement map_resources X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" map_resources is the last initialization step needed before the first VCPU is run. At that stage the code stores the MMIO base addresses used. Also it registers the respective register frames with the MMIO framework. This is based on Linux commit cbae53e663ea, written by Eric Auger. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - adapting to previous changes xen/arch/arm/vgic/vgic-v2.c | 66 +++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic.h | 1 + 2 files changed, 67 insertions(+) diff --git a/xen/arch/arm/vgic/vgic-v2.c b/xen/arch/arm/vgic/vgic-v2.c index 4e74ebf7f5..da64b4758c 100644 --- a/xen/arch/arm/vgic/vgic-v2.c +++ b/xen/arch/arm/vgic/vgic-v2.c @@ -221,6 +221,72 @@ void vgic_v2_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr) gic_hw_ops->write_lr(lr, &lr_val); } +int vgic_v2_map_resources(struct domain *d) +{ + struct vgic_dist *dist = &d->arch.vgic; + paddr_t cbase, csize; + paddr_t vbase; + int ret; + + /* + * The hardware domain gets the hardware address. + * Guests get the virtual platform layout. + */ + if ( is_hardware_domain(d) ) + { + d->arch.vgic.vgic_dist_base = gic_v2_hw_data.dbase; + /* + * For the hardware domain, we always map the whole HW CPU + * interface region in order to match the device tree (the "reg" + * properties is copied as it is). + * Note that we assume the size of the CPU interface is always + * aligned to PAGE_SIZE. + */ + cbase = gic_v2_hw_data.cbase; /* was: dist->vgic_cpu_base */ + csize = gic_v2_hw_data.csize; + vbase = gic_v2_hw_data.vbase; /* was: kvm_vgic_global_state.vcpu_base */ + } + else + { + d->arch.vgic.vgic_dist_base = GUEST_GICD_BASE; + /* + * The CPU interface exposed to the guest is always 8kB. We may + * need to add an offset to the virtual CPU interface base + * address when in the GIC is aliased to get a 8kB contiguous + * region. + */ + BUILD_BUG_ON(GUEST_GICC_SIZE != SZ_8K); + cbase = GUEST_GICC_BASE; + csize = GUEST_GICC_SIZE; + vbase = gic_v2_hw_data.vbase + gic_v2_hw_data.aliased_offset; + } + + + ret = vgic_register_dist_iodev(d, gaddr_to_gfn(dist->vgic_dist_base), + VGIC_V2); + if ( ret ) + { + gdprintk(XENLOG_ERR, "Unable to register VGIC MMIO regions\n"); + return ret; + } + + /* + * Map the gic virtual cpu interface in the gic cpu interface + * region of the guest. + */ + ret = map_mmio_regions(d, gaddr_to_gfn(cbase), csize / PAGE_SIZE, + maddr_to_mfn(vbase)); + if ( ret ) + { + gdprintk(XENLOG_ERR, "Unable to remap VGIC CPU to VCPU\n"); + return ret; + } + + dist->ready = true; + + return 0; +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index f19dc9502f..6fab994b9c 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -61,6 +61,7 @@ void vgic_sync_hardware_irq(struct domain *d, void vgic_v2_fold_lr_state(struct vcpu *vcpu); void vgic_v2_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr); void vgic_v2_set_underflow(struct vcpu *vcpu); +int vgic_v2_map_resources(struct domain *d); int vgic_register_dist_iodev(struct domain *d, gfn_t dist_base_fn, enum vgic_type); From patchwork Mon Mar 5 16:04:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130692 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2854378lja; Mon, 5 Mar 2018 08:07:35 -0800 (PST) X-Google-Smtp-Source: AG47ELtVZ9v/qWyJg7lFkq0/4HVaBq6Z0QmInXCkcQp03yN0SfjFUedOsm98l29tYqdxD5Z+zCMq X-Received: by 10.107.46.37 with SMTP id i37mr10477309ioo.161.1520266055528; Mon, 05 Mar 2018 08:07:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266055; cv=none; d=google.com; s=arc-20160816; b=xEREMQMsy6LM8K0aWohTX97vbO3KVyCKqvyI8LDDCu2fSYiGSoQBJGMxdbYXrm/5mD Io2x7gLGmHDeIr5p/MABZ5IATgT1a5h1WbopvhkcFa/wthfxR0r0ODmChoaX/vrcGp+4 P+/A+VcNNvCpkg0oUbYr8ggaG33mUz91A/urph3Jv2q0P+kn7UtbULR7/eoMUnfxYbox +nOmMV92w52QuW74I4QRq7Z6XR9J1txn8xlXtGfGC+5l1dWHDUl6LdblLhve/6/AYJc4 vmivy5ePgdNehZGWv7EqakqMv3mLvZratETO+IcNh8PZpzWNGabuDSb0PzcYDZ2VXqba zxYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=N+vXPsrSNCXgdR2myT1vXw4uuM877zqkya9Rzk+dMTs=; b=Yesk10A39arDaNZ6ATVSt/YowX+k5SEw2KDXDxfoVIP3C8uLiYQQI1F+EeVOTJPq0F Q8LJ0jmf5eymQVAan4K8U4sJzyYl68HR0ZT2IPFZkWadTKMaI3fwt3DbyAGzBGwcbT1T lJcfLaqQepiFpujjarFUYYrE7riOduyKHrVkkBPDr0TpTjFFq4krd+qgTS94B1DGgC6g 9hBQQ1swr93pGPD+nohGDpqP9egCA5jnxNzjbYVgUu+gQ6IMmVvErt4cGTOyGSqGnWdj p9vfLFuGh3gBKEIAzWDRN5Bb+fFhYli23ZJAtfPVj9H/E65dY369wLlDDiWWXZ9TGoEV 10dw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=NhF8bmgx; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.05.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:05:17 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:04:13 +0000 Message-Id: <20180305160415.16760-56-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 55/57] ARM: new VGIC: Add vgic_v2_enable X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Enable the VGIC operation by properly initialising the registers in the hypervisor GIC interface. This is based on Linux commit f7b6985cc3d0, written by Eric Auger. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - drop unneeded vgic_vmcr initialization - use update_hcr_status wrapper xen/arch/arm/vgic/vgic-v2.c | 6 ++++++ xen/arch/arm/vgic/vgic.h | 1 + 2 files changed, 7 insertions(+) diff --git a/xen/arch/arm/vgic/vgic-v2.c b/xen/arch/arm/vgic/vgic-v2.c index da64b4758c..b7d6493e5a 100644 --- a/xen/arch/arm/vgic/vgic-v2.c +++ b/xen/arch/arm/vgic/vgic-v2.c @@ -221,6 +221,12 @@ void vgic_v2_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr) gic_hw_ops->write_lr(lr, &lr_val); } +void vgic_v2_enable(struct vcpu *vcpu) +{ + /* Get the show on the road... */ + gic_hw_ops->update_hcr_status(GICH_HCR_EN, 1); +} + int vgic_v2_map_resources(struct domain *d) { struct vgic_dist *dist = &d->arch.vgic; diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index 6fab994b9c..bd0c3fe5ab 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -61,6 +61,7 @@ void vgic_sync_hardware_irq(struct domain *d, void vgic_v2_fold_lr_state(struct vcpu *vcpu); void vgic_v2_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr); void vgic_v2_set_underflow(struct vcpu *vcpu); +void vgic_v2_enable(struct vcpu *vcpu); int vgic_v2_map_resources(struct domain *d); int vgic_register_dist_iodev(struct domain *d, gfn_t dist_base_fn, enum vgic_type); From patchwork Mon Mar 5 16:04:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130687 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2854240lja; Mon, 5 Mar 2018 08:07:29 -0800 (PST) X-Google-Smtp-Source: AG47ELsj1eLe4F66f/ptV2sigOPzJ5zLPRtrZKCqDWT+BlU1R3sQNiMSrEm2QGED/P92jqHD3/Co X-Received: by 10.36.211.145 with SMTP id n139mr13509500itg.29.1520266049582; Mon, 05 Mar 2018 08:07:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266049; cv=none; d=google.com; s=arc-20160816; b=Awlle5y/IuAXYF//JHkqCDTC3fc5+Fs1UsZeckVCircAD4rwNw4YR7/CO+UUwrK0tX CsctY0a7AysnimvXIBMpc/zbwWmkedYL2ZhEFD1DsxhQMMTHIdU22/jgWd+vDHVpLdbw kH/Ga2I3pMACdi+z/cRNjAFMvE2tuvI65x20QJ+FgQreLM4HLXwmCPBIJLRUTXTYELr4 JU1K9YGprWA2MQf8tWxieawFdupVMclXzpRqBqbDgkIEChKGRvCKVeKD0bWpo1h3bcKk RNnUFShaYiL2s0yp8EvZBSWoqgaB+dPjMzXsQ4OZXLXRhz3ygt+1PW3gVQTwVGYjMKsz 4tgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=9x1FyZxIvL8J8lI1vcF97T9qkDVqOMxrYE33WthGfBA=; b=j4nPCG+/qPPKfh1HkCy57NhpV2bMADKhcXkGq7SMrzx5bpVhvcUbPqSZ1qrKxYjVaf IXzqg0MujhzmSS1GmD2MloP90BfcRM8FzPSPnda/gMj4tW11PjIQ94ewZxWBOQg8g3NV qOOEaHU0bLGFbc87lpselgUR5jpEl6Tyf3/Vc/iajNgwxwfDgiSNgEUHAIunrgBRO64/ U973CTDymXpOsZlcK5i2ZaEZr4smhRUhTpOpQIweINoXRS8l+yFxv9rLOqK95QmaUqqE DQCqdG0fqScKo9lXfoyKjsqki1IC+dT2ARouDGF2c/xAFQJLFhQp0xrJfIFEnDuQbcdA EDfg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=DjeEcJgf; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.05.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:05:18 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:04:14 +0000 Message-Id: <20180305160415.16760-57-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 56/57] ARM: allocate two pages for struct vcpu X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment we allocate exactly one page for struct vcpu on ARM, also have a check in place to prevent it growing beyond 4KB. As the struct includes the state of all 32 private (per-VCPU) interrupts, we are at 3840 bytes on arm64 at the moment already. Growing the per-IRQ VGIC structure even slightly makes the VCPU quickly exceed the 4K limit. The new VGIC will need more space per virtual IRQ. I spent a few hours trying to trim this down, but couldn't get it below 4KB, even with the nasty hacks piling up to save some bytes here and there. It turns out that beyond efficiency, maybe, there is no real technical reason this struct has to fit in one page, so lifting the limit to two pages seems like the most pragmatic solution. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - no changes xen/arch/arm/domain.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 11a46aa27f..0bec6aad17 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -502,10 +502,13 @@ void dump_pageframe_info(struct domain *d) struct vcpu *alloc_vcpu_struct(void) { struct vcpu *v; - BUILD_BUG_ON(sizeof(*v) > PAGE_SIZE); - v = alloc_xenheap_pages(0, 0); - if ( v != NULL ) + + BUILD_BUG_ON(sizeof(*v) > 2 * PAGE_SIZE); + v = alloc_xenheap_pages(1, 0); + if ( v != NULL ) { clear_page(v); + clear_page((void *)v + PAGE_SIZE); + } return v; } From patchwork Mon Mar 5 16:04:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 130688 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp2854325lja; Mon, 5 Mar 2018 08:07:32 -0800 (PST) X-Google-Smtp-Source: AG47ELuC45kvBKToF6PZeLMq6opQcLxmEryQhGnKfGO4Czettb+1Wm4QATYxI7Gp+s8aAk/tqOBi X-Received: by 10.36.2.75 with SMTP id 72mr14368110itu.83.1520266052260; Mon, 05 Mar 2018 08:07:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520266052; cv=none; d=google.com; s=arc-20160816; b=Jq60YdopBmNdRIf2lttL8XLrPlSqBXiSi8XY+uZdnx4q69dU7kSmvDDISjIMTtJhxe M8lrI5B5LFud6vbF/4OmjJjiDZPYovkMUgSSztCf7Hl8fD58ix14BaY5cMjEJoCG8U6S fTCV7e/cOQOFEI9nczF/nTd5D6BDuCjIPLMLoFn1sAKjwtY00iLFnFWMTCGZvPo1qI31 /0r6LIBE8EM52BqjbCbrjHOea4VR6OUqqstWZhuNGz9dpv7qO7eJVoRT1nLJz1ucxqSv 0MhQ6Of9ATAlrgne0VQszwnN+Fx5P8WZ/ADFq5bNFlQJKtRXOvGF4+51+E0IGJov8aYH vmgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=nz71jaeAw9Yds48R7bLCOzGMZMURcrCoxrEd6t2cHI8=; b=zUf753hBByQ1VShdyzipJrkoasL8o2nRQTdpL2dgaBSaz2LcxVWL0dyFtB6s3DK5g9 cD6U4amMKdr/d/0ccu7RkluDmzgleVyRCw9kW1yjTQrflJFAPj/9UsMTyJWUcJ/UMN5H dQiDiS+d6dILt3OcrkGcu576kNFB5aaApSS2zkCOQOcm3F/VaPmvjT95IyfkA8eRDe75 HLr8PpaPNA0TAm5nSf0qQfR0WOXEeso7W5y3hF09bw0w2Qa1ui7NGjRo6djdD8JvDYc8 8aZnP6Xc12ye/J2mlizgPYhtUW2MJstTasvPmA0jqyexDupxt1uOBvGoTJyZ9khlTdM5 rgSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=WDfe+rdo; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.05.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:05:19 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:04:15 +0000 Message-Id: <20180305160415.16760-58-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 57/57] ARM: VGIC: wire new VGIC(-v2) files into Xen build system X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Now that we have both the old VGIC prepared to cope with a sibling and the code for the new VGIC in place, lets add a Kconfig option to enable the new code and wire it into the Xen build system. This will add a compile time option to use either the "old" or the "new" VGIC. In the moment this is restricted to a vGIC-v2. To make the build system happy, we provide a temporary dummy implementation of vgic_v3_setup_hw() to allow building for now. Signed-off-by: Andre Przywara --- Changelog RFC ... v1: - no changes xen/arch/arm/Kconfig | 6 +++++- xen/arch/arm/Makefile | 10 +++++++++- xen/arch/arm/vgic/vgic.c | 8 ++++++++ xen/common/Makefile | 1 + 4 files changed, 23 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 2782ee6589..aad19927ce 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -48,7 +48,11 @@ config HAS_GICV3 config HAS_ITS bool prompt "GICv3 ITS MSI controller support" if EXPERT = "y" - depends on HAS_GICV3 + depends on HAS_GICV3 && !NEW_VGIC + +config NEW_VGIC + bool + prompt "Use new VGIC implementation" config SBSA_VUART_CONSOLE bool "Emulated SBSA UART console support" diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index 41d7366527..2a3ec94a18 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -16,7 +16,6 @@ obj-y += domain_build.o obj-y += domctl.o obj-$(EARLY_PRINTK) += early_printk.o obj-y += gic.o -obj-y += gic-vgic.o obj-y += gic-v2.o obj-$(CONFIG_HAS_GICV3) += gic-v3.o obj-$(CONFIG_HAS_ITS) += gic-v3-its.o @@ -47,10 +46,19 @@ obj-y += sysctl.o obj-y += time.o obj-y += traps.o obj-y += vcpreg.o +ifeq ($(CONFIG_NEW_VGIC),y) +obj-y += vgic/vgic.o +obj-y += vgic/vgic-v2.o +obj-y += vgic/vgic-mmio.o +obj-y += vgic/vgic-mmio-v2.o +obj-y += vgic/vgic-init.o +else +obj-y += gic-vgic.o obj-y += vgic.o obj-y += vgic-v2.o obj-$(CONFIG_HAS_GICV3) += vgic-v3.o obj-$(CONFIG_HAS_ITS) += vgic-v3-its.o +endif obj-y += vm_event.o obj-y += vtimer.o obj-$(CONFIG_SBSA_VUART_CONSOLE) += vpl011.o diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index f42092fec3..f7b4779a71 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -978,6 +978,14 @@ unsigned int domain_max_vcpus(const struct domain *d) return min_t(unsigned int, MAX_VIRT_CPUS, vgic_vcpu_limit); } +void vgic_v3_setup_hw(paddr_t dbase, + unsigned int nr_rdist_regions, + const struct rdist_region *regions, + unsigned int intid_bits) +{ + /* Dummy implementation to allow building without actual vGICv3 support. */ +} + /* * Local variables: * mode: C diff --git a/xen/common/Makefile b/xen/common/Makefile index 3a349f478b..92a1d1fa58 100644 --- a/xen/common/Makefile +++ b/xen/common/Makefile @@ -19,6 +19,7 @@ obj-y += keyhandler.o obj-$(CONFIG_KEXEC) += kexec.o obj-$(CONFIG_KEXEC) += kimage.o obj-y += lib.o +obj-$(CONFIG_NEW_VGIC) += list_sort.o obj-$(CONFIG_LIVEPATCH) += livepatch.o livepatch_elf.o obj-y += lzo.o obj-$(CONFIG_HAS_MEM_ACCESS) += mem_access.o