From patchwork Thu Mar 8 01:01:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 130924 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp5851777lja; Wed, 7 Mar 2018 17:02:49 -0800 (PST) X-Google-Smtp-Source: AG47ELursjA7jzV97O6lJUlejvfwJFP1maa4mzJnjATD8j1SAwqh+VPtfJ0Cb8MUBlRMHqBlfrX3 X-Received: by 2002:a17:902:8602:: with SMTP id f2-v6mr12505266plo.6.1520470969428; Wed, 07 Mar 2018 17:02:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520470969; cv=none; d=google.com; s=arc-20160816; b=PcsomFUZB/no7LW4G6SwynS3H78WRlnOiYmVQdLXqQSgoi5a5w0iqh74ctYAywk+i8 U6OOXDEKebqilSJI2ZcyeoUyVbf6q9x+uot3FiWWEpi0Rn1xBVbYgWDqnULVDgCPCC9K k/pOngy1qdB0p96MJpyszkuVAuHgP/OP5LVRS+KLjO6LjjLkBo/tdj3GmsI6+xLoJUTj uf5/XogQjW0ETjPF9u6Nz3T2O5BuitLJQGM5BAdGON611nHYDn1U4ByAMDWIZumOOo3O JASp/kum3bBXy0BOrxQArdcLUaGfeDR2SZQ+ZftyMn7msPSgphs2aEr9YcbvhXdeKDLb ikaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=Ww+lBFHfN3e1h1TOExchhUtNsA2Y7r3fMy1dm9X6R0I=; b=v6r47mjKovwx/WPvOiJPbeqYo2vC27qeCK1Bxg6eUzCotm/KLws4FMMHWAmioyJyvq Xm1I43jzZG+CAxO/vtL1PzGDgHb1GZx6hh0hKqRI4hQBh7Qg5whP9PeOn2BBZdRDMQDX PBaZG76Nwh+K5wMp4j1fA4/Ql9yErGITSe+Z1W+CNSliFnJ0RSvs5bmbmyMtfe7g8jms vJC2lIw1B9CIxVhVvANNidLEH70cBfsBYpA5tevCiz/yD349Sla6xMfriKzWzu/mwMgn nnI6Zb6TgPlq0oSup+47qYFKHPAWFnW/dEDzSqaF0LzLG+GOtXfQBieQLifWFKPXSsRS 5ejQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=GMZ8nApl; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l3-v6si13983255pld.519.2018.03.07.17.02.49; Wed, 07 Mar 2018 17:02:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=GMZ8nApl; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754967AbeCHBCs (ORCPT + 6 others); Wed, 7 Mar 2018 20:02:48 -0500 Received: from mail-pf0-f194.google.com ([209.85.192.194]:42149 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754946AbeCHBCr (ORCPT ); Wed, 7 Mar 2018 20:02:47 -0500 Received: by mail-pf0-f194.google.com with SMTP id a16so1682040pfn.9 for ; Wed, 07 Mar 2018 17:02:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BaQpGtQ9A+jYcLhaNDpr0FaAMTTP4fInrxCsJEaSh5c=; b=GMZ8nAplNICyuCvLbVrpux0PUFmx6nirRa0AS/weD5ZIcqtmYnXFHsDbYM7qOZ67+Y BtEEfl/+84WOlHLNxOfdy8zOCCEg3cru8gCyeQqlSUAGL5eCewdVU6CGu8pkdqvKDyPJ FSdjefmXN4m7Yr82RgxIuno1+QOWGUWBP91B0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BaQpGtQ9A+jYcLhaNDpr0FaAMTTP4fInrxCsJEaSh5c=; b=XL8hXf45Warb+65W5h2rED75fmAF7agioLlq44yyjML8fhVgEjitokjwnS3TUY2lv0 KNzbraAgq3CTFZEwVaYtoFSgT+aUyh7Bjm6+Iv3z0Z+3xMzEMuX2lD59rARIdeowve4z bv62bCnoU2xR/vJrbFAtlL9yKY8ysWC0+rBnNZUP5ado1nZ2kjJoCARIeA2DUQWnDzfs GahUHejr6zAItBOXkNciijk7qE7Vq7PsYFzk2BF8Le+8PD+5EqefROXbLAbrX+ZrN+bD aALBNOJtnPquCDN2Nd2Md/CaecPxQ6DQAjc74h0Bw2Q07mkggZZytkOjLOOzCfFBtgNu JBKw== X-Gm-Message-State: APf1xPA+DI7gCrzw1/It3jJ1tQFdqtUoykiG1OwsYkDvXyHEdCgn1+NV pJZ/wJz6Dkc328vxQCCF+zLd1Q== X-Received: by 10.99.96.18 with SMTP id u18mr20184923pgb.124.1520470966940; Wed, 07 Mar 2018 17:02:46 -0800 (PST) Received: from localhost.localdomain ([104.237.91.63]) by smtp.gmail.com with ESMTPSA id l12sm39459131pfb.35.2018.03.07.17.02.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 07 Mar 2018 17:02:45 -0800 (PST) From: Shawn Guo To: Ulf Hansson Cc: Jaehoon Chung , Shawn Lin , Rob Herring , tianshuliang , Jiancheng Xue , devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, Shawn Guo Subject: [PATCH v3 1/2] dt-bindings: mmc: add bindings for hi3798cv200-dw-mshc Date: Thu, 8 Mar 2018 09:01:33 +0800 Message-Id: <1520470894-9114-2-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1520470894-9114-1-git-send-email-shawn.guo@linaro.org> References: <1520470894-9114-1-git-send-email-shawn.guo@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: tianshuliang Hisilicon hi3798cv200 SoC extends the dw-mshc controller for additional clock control. Add device tree bindings for hi3798cv200-dw-mshc. Signed-off-by: tianshuliang Signed-off-by: Jiancheng Xue Signed-off-by: Shawn Guo Reviewed-by: Rob Herring --- .../bindings/mmc/hi3798cv200-dw-mshc.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/hi3798cv200-dw-mshc.txt -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/mmc/hi3798cv200-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/hi3798cv200-dw-mshc.txt new file mode 100644 index 000000000000..a0693b7145f2 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/hi3798cv200-dw-mshc.txt @@ -0,0 +1,40 @@ +* Hisilicon Hi3798CV200 specific extensions to the Synopsys Designware Mobile + Storage Host Controller + +Read synopsys-dw-mshc.txt for more details + +The Synopsys designware mobile storage host controller is used to interface +a SoC with storage medium such as eMMC or SD/MMC cards. This file documents +differences between the core Synopsys dw mshc controller properties described +by synopsys-dw-mshc.txt and the properties used by the Hisilicon Hi3798CV200 +specific extensions to the Synopsys Designware Mobile Storage Host Controller. + +Required Properties: +- compatible: Should contain "hisilicon,hi3798cv200-dw-mshc". +- clocks: A list of phandle + clock-specifier pairs for the clocks listed + in clock-names. +- clock-names: Should contain the following: + "ciu" - The ciu clock described in synopsys-dw-mshc.txt. + "biu" - The biu clock described in synopsys-dw-mshc.txt. + "ciu-sample" - Hi3798CV200 extended phase clock for ciu sampling. + "ciu-drive" - Hi3798CV200 extended phase clock for ciu driving. + +Example: + + emmc: mmc@9830000 { + compatible = "hisilicon,hi3798cv200-dw-mshc"; + reg = <0x9830000 0x10000>; + interrupts = ; + clocks = <&crg HISTB_MMC_CIU_CLK>, + <&crg HISTB_MMC_BIU_CLK>, + <&crg HISTB_MMC_SAMPLE_CLK>, + <&crg HISTB_MMC_DRV_CLK>; + clock-names = "ciu", "biu", "ciu-sample", "ciu-drive"; + fifo-depth = <256>; + clock-frequency = <200000000>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + bus-width = <8>; + }; From patchwork Thu Mar 8 01:01:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 130925 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp5851863lja; Wed, 7 Mar 2018 17:02:53 -0800 (PST) X-Google-Smtp-Source: AG47ELtDxtK3PRuMjfH9TnorjkeBgUaTFTL4O5PtkRy+DXRKv4n4rGa79N2u+xXfi9aFautHvQgW X-Received: by 2002:a17:902:51ee:: with SMTP id y101-v6mr22565809plh.157.1520470973609; Wed, 07 Mar 2018 17:02:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520470973; cv=none; d=google.com; s=arc-20160816; b=uJykHUGwYKLeFdCqM4x/FV+ui6nU2nr5R4BPA/UcCoFD1TK41oOkkXEGeMAuBSLpuM goVNM86NP+X8mwbfzSLwB3Vienlrcqh5cjDgsj2JWwK7/jTlcxbiVjeL5igNJrxC882W RuKUI1rMgcIzNrmh9IWMjgsNHNmbJyK8IqxPXjP8Mx5OjQDnWnTaSQLxvMHE6U2Obg8j ERdoDAXdxU6o5Y35R6glUQRjsr8ul7uYzRp/WQ6Oj1T6gPWWzXuj1PmiiaTKtD2VPjs/ hJmlO0YJFZ/NuC0dHvPqvdIzcM/KelEdbsNA/cS3ZzunDUKdUo/bVj5zsN4Ro8JrFtc/ IhjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=kihj8vKyKDZQyf+FdVxGMr1A/L8bY5I+3EeDhDppLo8=; b=gfbf22fZhR53B6dWn8SxBxtVW/m5waTOvYwzDfj6Tsof8LNPadIX78NuwTZEcM1qup fSresVSZNUM4c8ySBQkv43q6ut1CepJlamrTuptfq0622beH2bMDDvWnUTIPKK/Qw/9j 2gBYqp5Vhk1ZTh1vzJJPNoJDEncT9nZrOjRSer4eHnlXSQBECaO1uN/6gpXVWq+fZ6av 8MfFAFhre+Vxv15uafauyJDMEY/4a96fhYELiCn1uZ6qab87E9voC5ghhFlWNdI/t5TD 7eqF9nQjgk5ujrOWXGirc1xuzrc9IquPbbd5419dv8ya/76PA7ysWYaYCuxOTGvmtb/U pLOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=C80KeoBT; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l3-v6si13983255pld.519.2018.03.07.17.02.53; Wed, 07 Mar 2018 17:02:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=C80KeoBT; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754980AbeCHBCw (ORCPT + 6 others); Wed, 7 Mar 2018 20:02:52 -0500 Received: from mail-pl0-f67.google.com ([209.85.160.67]:34964 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754965AbeCHBCv (ORCPT ); Wed, 7 Mar 2018 20:02:51 -0500 Received: by mail-pl0-f67.google.com with SMTP id w22-v6so2398944pll.2 for ; Wed, 07 Mar 2018 17:02:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KNvLwcx3NwG6ynCdCjtOqGSe8uoHEQqyrMKCfHlKIqg=; b=C80KeoBTZzhA4AkTcBYL5eFUc9bCATKSqVW23oCr4rRKqfRz/zYedUWIQdfnbfflPv 8lGxeY2T2UagnNkKuOiyA0GUFRBF7ejLxoREZ4ynPRxc6NM7XvQxlqpJ5CTX8wX02bSP usKfu4vchYF8MipaOFvepMGKrkHspdh88mBQY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KNvLwcx3NwG6ynCdCjtOqGSe8uoHEQqyrMKCfHlKIqg=; b=fyB4sA0/x7fU82TyaZLDtAyVM8gHhBalpAK0MRJv54Vr/4DQ/yMZ2ygtk2m7CPlK1Q Ch4qwaqZ7i6oxsSmQPM6vQQRzy0tzL4LORJ4g14JfJRGpwwRLxY2SiyA5TIzbtlrMejP MXrslX36DBSU2Td5X++u8rduHR4Ne/JtodfO50eYFutQHEOkgsbpBKa0APC8YFDX24Fv 9O/KhljidYFPIPox2yaNNj8w82I+7XJbKuG96h99jxmpBTXv+N0wvOZN/r3UPj/jpF5c RwtNrWzdMvCYRn+7A/12ktZ1Anle7mHFit3Vci8NBmPGRdpwpP95s950HcR0g2UZmgUn eeZQ== X-Gm-Message-State: APf1xPB37V14oza0cvM86nl+tiTJQKZYjV7p/oDkYEaULMBukBM/dpC0 YD7SRz8SR1OdDUIQKWSEAnsTDA== X-Received: by 2002:a17:902:9883:: with SMTP id s3-v6mr21750023plp.96.1520470970748; Wed, 07 Mar 2018 17:02:50 -0800 (PST) Received: from localhost.localdomain ([104.237.91.63]) by smtp.gmail.com with ESMTPSA id l12sm39459131pfb.35.2018.03.07.17.02.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 07 Mar 2018 17:02:49 -0800 (PST) From: Shawn Guo To: Ulf Hansson Cc: Jaehoon Chung , Shawn Lin , Rob Herring , tianshuliang , Jiancheng Xue , devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, Shawn Guo Subject: [PATCH v3 2/2] mmc: dw_mmc: add support for hi3798cv200 specific extensions of dw-mshc Date: Thu, 8 Mar 2018 09:01:34 +0800 Message-Id: <1520470894-9114-3-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1520470894-9114-1-git-send-email-shawn.guo@linaro.org> References: <1520470894-9114-1-git-send-email-shawn.guo@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: tianshuliang Hi3798CV200 SoC extends the dw-mshc controller for additional clock and bus control. Add support for these extensions. Signed-off-by: tianshuliang Signed-off-by: Jiancheng Xue Signed-off-by: Shawn Guo --- drivers/mmc/host/Kconfig | 9 ++ drivers/mmc/host/Makefile | 1 + drivers/mmc/host/dw_mmc-hi3798cv200.c | 202 ++++++++++++++++++++++++++++++++++ drivers/mmc/host/dw_mmc.h | 6 + 4 files changed, 218 insertions(+) create mode 100644 drivers/mmc/host/dw_mmc-hi3798cv200.c -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Reviewed-by: Shawn Lin diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 620c2d90a646..de36fffe8225 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -718,6 +718,15 @@ config MMC_DW_EXYNOS Synopsys DesignWare Memory Card Interface driver. Select this option for platforms based on Exynos4 and Exynos5 SoC's. +config MMC_DW_HI3798CV200 + tristate "Hi3798CV200 specific extensions for Synopsys DW Memory Card Interface" + depends on MMC_DW + select MMC_DW_PLTFM + help + This selects support for HiSilicon Hi3798CV200 SoC specific extensions to the + Synopsys DesignWare Memory Card Interface driver. Select this option + for platforms based on HiSilicon Hi3798CV200 SoC. + config MMC_DW_K3 tristate "K3 specific extensions for Synopsys DW Memory Card Interface" depends on MMC_DW diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 84cd1388abc3..00ec9a2f59be 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -51,6 +51,7 @@ obj-$(CONFIG_MMC_CAVIUM_THUNDERX) += thunderx-mmc.o obj-$(CONFIG_MMC_DW) += dw_mmc.o obj-$(CONFIG_MMC_DW_PLTFM) += dw_mmc-pltfm.o obj-$(CONFIG_MMC_DW_EXYNOS) += dw_mmc-exynos.o +obj-$(CONFIG_MMC_DW_HI3798CV200) += dw_mmc-hi3798cv200.o obj-$(CONFIG_MMC_DW_K3) += dw_mmc-k3.o obj-$(CONFIG_MMC_DW_PCI) += dw_mmc-pci.o obj-$(CONFIG_MMC_DW_ROCKCHIP) += dw_mmc-rockchip.o diff --git a/drivers/mmc/host/dw_mmc-hi3798cv200.c b/drivers/mmc/host/dw_mmc-hi3798cv200.c new file mode 100644 index 000000000000..f9b333ff259e --- /dev/null +++ b/drivers/mmc/host/dw_mmc-hi3798cv200.c @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 HiSilicon Technologies Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dw_mmc.h" +#include "dw_mmc-pltfm.h" + +#define ALL_INT_CLR 0x1ffff + +struct hi3798cv200_priv { + struct clk *sample_clk; + struct clk *drive_clk; +}; + +static void dw_mci_hi3798cv200_set_ios(struct dw_mci *host, struct mmc_ios *ios) +{ + struct hi3798cv200_priv *priv = host->priv; + u32 val; + + val = mci_readl(host, UHS_REG); + if (ios->timing == MMC_TIMING_MMC_DDR52 || + ios->timing == MMC_TIMING_UHS_DDR50) + val |= SDMMC_UHS_DDR; + else + val &= ~SDMMC_UHS_DDR; + mci_writel(host, UHS_REG, val); + + val = mci_readl(host, ENABLE_SHIFT); + if (ios->timing == MMC_TIMING_MMC_DDR52) + val |= SDMMC_ENABLE_PHASE; + else + val &= ~SDMMC_ENABLE_PHASE; + mci_writel(host, ENABLE_SHIFT, val); + + val = mci_readl(host, DDR_REG); + if (ios->timing == MMC_TIMING_MMC_HS400) + val |= SDMMC_DDR_HS400; + else + val &= ~SDMMC_DDR_HS400; + mci_writel(host, DDR_REG, val); + + if (ios->timing == MMC_TIMING_MMC_HS || + ios->timing == MMC_TIMING_LEGACY) + clk_set_phase(priv->drive_clk, 180); + else if (ios->timing == MMC_TIMING_MMC_HS200) + clk_set_phase(priv->drive_clk, 135); +} + +static int dw_mci_hi3798cv200_execute_tuning(struct dw_mci_slot *slot, + u32 opcode) +{ + int degrees[] = { 0, 45, 90, 135, 180, 225, 270, 315 }; + struct dw_mci *host = slot->host; + struct hi3798cv200_priv *priv = host->priv; + int raise_point = -1, fall_point = -1; + int err, prev_err = -1; + int found = 0; + int i; + + for (i = 0; i < ARRAY_SIZE(degrees); i++) { + clk_set_phase(priv->sample_clk, degrees[i]); + mci_writel(host, RINTSTS, ALL_INT_CLR); + + err = mmc_send_tuning(slot->mmc, opcode, NULL); + if (!err) + found = 1; + + if (i > 0) { + if (err && !prev_err) + fall_point = i - 1; + if (!err && prev_err) + raise_point = i; + } + + if (raise_point != -1 && fall_point != -1) + goto tuning_out; + + prev_err = err; + err = 0; + } + +tuning_out: + if (found) { + if (raise_point == -1) + raise_point = 0; + if (fall_point == -1) + fall_point = ARRAY_SIZE(degrees) - 1; + if (fall_point < raise_point) { + if ((raise_point + fall_point) > + (ARRAY_SIZE(degrees) - 1)) + i = fall_point / 2; + else + i = (raise_point + ARRAY_SIZE(degrees) - 1) / 2; + } else { + i = (raise_point + fall_point) / 2; + } + + clk_set_phase(priv->sample_clk, degrees[i]); + dev_dbg(host->dev, "Tuning clk_sample[%d, %d], set[%d]\n", + raise_point, fall_point, degrees[i]); + } else { + dev_err(host->dev, "No valid clk_sample shift! use default\n"); + err = -EINVAL; + } + + mci_writel(host, RINTSTS, ALL_INT_CLR); + return err; +} + +static int dw_mci_hi3798cv200_init(struct dw_mci *host) +{ + struct hi3798cv200_priv *priv; + int ret; + + priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->sample_clk = devm_clk_get(host->dev, "ciu-sample"); + if (IS_ERR(priv->sample_clk)) { + dev_err(host->dev, "failed to get ciu-sample clock\n"); + return PTR_ERR(priv->sample_clk); + } + + priv->drive_clk = devm_clk_get(host->dev, "ciu-drive"); + if (IS_ERR(priv->drive_clk)) { + dev_err(host->dev, "failed to get ciu-drive clock\n"); + return PTR_ERR(priv->drive_clk); + } + + ret = clk_prepare_enable(priv->sample_clk); + if (ret) { + dev_err(host->dev, "failed to enable ciu-sample clock\n"); + return ret; + } + + ret = clk_prepare_enable(priv->drive_clk); + if (ret) { + dev_err(host->dev, "failed to enable ciu-drive clock\n"); + goto disable_sample_clk; + } + + host->priv = priv; + return 0; + +disable_sample_clk: + clk_disable_unprepare(priv->sample_clk); + return ret; +} + +static const struct dw_mci_drv_data hi3798cv200_data = { + .init = dw_mci_hi3798cv200_init, + .set_ios = dw_mci_hi3798cv200_set_ios, + .execute_tuning = dw_mci_hi3798cv200_execute_tuning, +}; + +static int dw_mci_hi3798cv200_probe(struct platform_device *pdev) +{ + return dw_mci_pltfm_register(pdev, &hi3798cv200_data); +} + +static int dw_mci_hi3798cv200_remove(struct platform_device *pdev) +{ + struct dw_mci *host = platform_get_drvdata(pdev); + struct hi3798cv200_priv *priv = host->priv; + + clk_disable_unprepare(priv->drive_clk); + clk_disable_unprepare(priv->sample_clk); + + return dw_mci_pltfm_remove(pdev); +} + +static const struct of_device_id dw_mci_hi3798cv200_match[] = { + { .compatible = "hisilicon,hi3798cv200-dw-mshc", }, + {}, +}; + +MODULE_DEVICE_TABLE(of, dw_mci_hi3798cv200_match); +static struct platform_driver dw_mci_hi3798cv200_driver = { + .probe = dw_mci_hi3798cv200_probe, + .remove = dw_mci_hi3798cv200_remove, + .driver = { + .name = "dwmmc_hi3798cv200", + .of_match_table = dw_mci_hi3798cv200_match, + }, +}; +module_platform_driver(dw_mci_hi3798cv200_driver); + +MODULE_DESCRIPTION("HiSilicon Hi3798CV200 Specific DW-MSHC Driver Extension"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:dwmmc_hi3798cv200"); diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h index e3124f06a47e..d0c573dfe115 100644 --- a/drivers/mmc/host/dw_mmc.h +++ b/drivers/mmc/host/dw_mmc.h @@ -318,6 +318,7 @@ struct dw_mci_board { #define SDMMC_BUFADDR 0x098 #define SDMMC_CDTHRCTL 0x100 #define SDMMC_UHS_REG_EXT 0x108 +#define SDMMC_DDR_REG 0x10c #define SDMMC_ENABLE_SHIFT 0x110 #define SDMMC_DATA(x) (x) /* @@ -443,7 +444,12 @@ struct dw_mci_board { #define SDMMC_CARD_WR_THR_EN BIT(2) #define SDMMC_CARD_RD_THR_EN BIT(0) /* UHS-1 register defines */ +#define SDMMC_UHS_DDR BIT(16) #define SDMMC_UHS_18V BIT(0) +/* DDR register defines */ +#define SDMMC_DDR_HS400 BIT(31) +/* Enable shift register defines */ +#define SDMMC_ENABLE_PHASE BIT(0) /* All ctrl reset bits */ #define SDMMC_CTRL_ALL_RESET_FLAGS \ (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET)