From patchwork Thu Mar 8 13:06:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 130998 Delivered-To: patches@linaro.org Received: by 10.46.66.2 with SMTP id p2csp6455701lja; Thu, 8 Mar 2018 05:06:30 -0800 (PST) X-Google-Smtp-Source: AG47ELs8KguZ9sn2sr1y1V+7Q+AyamHMPNN3WtoAF8eoqDGE+fRew/jGNW2t/S/BZClPZlWt6iFS X-Received: by 10.223.138.153 with SMTP id y25mr22125540wry.257.1520514390435; Thu, 08 Mar 2018 05:06:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520514390; cv=none; d=google.com; s=arc-20160816; b=aqvrhmVnATxIMJpRjussibVLdhS8U276h1Tp6Ua5lKfyfevnpcS4/LjOUnf/AkMCo7 INjhaCGe0mMK0NHZQoh0EJeWEFBab+4LzLCP3Ljw6BbJBR6La2jZ2cUUQaSlcwcGpSMn WLbhmol+y+Poa6VoaZHvnIfyPXVhA3jDmgzCbNRvWGddwtl5U6pn5E7DR2MVUMqERtmw QETbOs1eAAp6v2KNNRYmqciie+CHzeF8W2DW5LYnAmSgUuEbwm9R6YPowzSXhcztty3s HAURkvB0VwUJ/tJM8CpAq7CR3qYVjaDlBWfQVjyZVs3emiayeHimbTBasdVvSOp853GA bT/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=8DYTh3ifXlfM9ksJAhKjNRRsCx5UKF086u9co5t48gU=; b=L7E3sWVO6boNW08UKIlynGjR1kc2xJEoK9EyVOkUe00Xphla1jcW0JNx3u4PShTeq4 ywGIWfw07NZBRnDAdlJZJoM+iFrRYQfyxp3o3oF5oFEaCKlvZdxE10+JoPm47cphebZc FpsK3FM2Fzey6hzRcyoOdaamNzYJeMwP5tzneAI5gCSyeMfARXx3oaEdUXAXUGFq6lY3 I4Rpqlnh4Lsww0xUjKxz39w9SLTKBR7pCKdkFbDWsdWnMrQV3C+EOWdvVTprUqHxMvLo pDgsEgmi2/doI4SU9L+VW/kA8aAFiu/CxfJKCc5eJdOnfh34TutGsMnkPYAUv80Q3O0y rrrA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id l17si602911wrb.418.2018.03.08.05.06.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Mar 2018 05:06:30 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1etvFc-0005yI-Oo; Thu, 08 Mar 2018 13:06:28 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Igor Mammedov , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= , =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH v3 1/6] target/arm: Query host CPU features on-demand at instance init Date: Thu, 8 Mar 2018 13:06:21 +0000 Message-Id: <20180308130626.12393-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180308130626.12393-1-peter.maydell@linaro.org> References: <20180308130626.12393-1-peter.maydell@linaro.org> MIME-Version: 1.0 Currently we query the host CPU features in the class init function for the TYPE_ARM_HOST_CPU class, so that we can later copy them from the class object into the instance object in the object instance init function. This is awkward for implementing "-cpu max", which should work like "-cpu host" for KVM but like "cpu with all implemented features" for TCG. Move the place where we store the information about the host CPU from a class object to static variables in kvm.c, and then in the instance init function call a new kvm_arm_set_cpu_features_from_host() function which will query the host kernel if necessary and then fill in the CPU instance fields. This allows us to drop the special class struct and class init function for TYPE_ARM_HOST_CPU entirely. We can't delay the probe until realize, because the ARM instance_post_init hook needs to look at the feature bits we set, so we need to do it in the initfn. This is safe because the probing doesn't affect the actual VM state (it creates a separate scratch VM to do its testing), but the probe might fail. Because we can't report errors in retrieving the host features in the initfn, we check this belatedly in the realize function (the intervening code will be able to cope with the relevant fields in the CPU structure being zero). Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- target/arm/cpu.h | 5 +++++ target/arm/kvm_arm.h | 35 ++++++++++++++++++++++++----------- target/arm/cpu.c | 13 +++++++++++++ target/arm/kvm.c | 36 +++++++++++++++++++----------------- target/arm/kvm32.c | 8 ++++---- target/arm/kvm64.c | 8 ++++---- 6 files changed, 69 insertions(+), 36 deletions(-) -- 2.16.2 Reviewed-by: Alex Bennée diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8dd6b788df..1df46ad7a0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -745,6 +745,11 @@ struct ARMCPU { /* Uniprocessor system with MP extensions */ bool mp_is_up; + /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init + * and the probe failed (so we need to report the error in realize) + */ + bool host_cpu_probe_failed; + /* The instance init functions for implementation-specific subclasses * set these fields to specify the implementation-dependent values of * various constant registers and reset values of non-constant diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index cfb7e5af72..1e2364007d 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -152,20 +152,16 @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try, void kvm_arm_destroy_scratch_host_vcpu(int *fdarray); #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU -#define ARM_HOST_CPU_CLASS(klass) \ - OBJECT_CLASS_CHECK(ARMHostCPUClass, (klass), TYPE_ARM_HOST_CPU) -#define ARM_HOST_CPU_GET_CLASS(obj) \ - OBJECT_GET_CLASS(ARMHostCPUClass, (obj), TYPE_ARM_HOST_CPU) - -typedef struct ARMHostCPUClass { - /*< private >*/ - ARMCPUClass parent_class; - /*< public >*/ +/** + * ARMHostCPUFeatures: information about the host CPU (identified + * by asking the host kernel) + */ +typedef struct ARMHostCPUFeatures { uint64_t features; uint32_t target; const char *dtb_compatible; -} ARMHostCPUClass; +} ARMHostCPUFeatures; /** * kvm_arm_get_host_cpu_features: @@ -174,8 +170,16 @@ typedef struct ARMHostCPUClass { * Probe the capabilities of the host kernel's preferred CPU and fill * in the ARMHostCPUClass struct accordingly. */ -bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc); +bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf); +/** + * kvm_arm_set_cpu_features_from_host: + * @cpu: ARMCPU to set the features for + * + * Set up the ARMCPU struct fields up to match the information probed + * from the host CPU. + */ +void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu); /** * kvm_arm_sync_mpstate_to_kvm @@ -200,6 +204,15 @@ void kvm_arm_pmu_init(CPUState *cs); #else +static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) +{ + /* This should never actually be called in the "not KVM" case, + * but set up the fields to indicate an error anyway. + */ + cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; + cpu->host_cpu_probe_failed = true; +} + static inline int kvm_arm_vgic_probe(void) { return 0; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6b77aaa445..abf9fb2160 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -725,6 +725,19 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) int pagebits; Error *local_err = NULL; + /* If we needed to query the host kernel for the CPU features + * then it's possible that might have failed in the initfn, but + * this is the first point where we can report it. + */ + if (cpu->host_cpu_probe_failed) { + if (!kvm_enabled()) { + error_setg(errp, "The 'host' CPU type can only be used with KVM"); + } else { + error_setg(errp, "Failed to retrieve host CPU features"); + } + return; + } + cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 1219d0062b..1c0e57690a 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -33,6 +33,8 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = { static bool cap_has_mp_state; +static ARMHostCPUFeatures arm_host_cpu_features; + int kvm_arm_vcpu_init(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); @@ -129,30 +131,32 @@ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray) } } -static void kvm_arm_host_cpu_class_init(ObjectClass *oc, void *data) +void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) { - ARMHostCPUClass *ahcc = ARM_HOST_CPU_CLASS(oc); + CPUARMState *env = &cpu->env; - /* All we really need to set up for the 'host' CPU - * is the feature bits -- we rely on the fact that the - * various ID register values in ARMCPU are only used for - * TCG CPUs. - */ - if (!kvm_arm_get_host_cpu_features(ahcc)) { - fprintf(stderr, "Failed to retrieve host CPU features!\n"); - abort(); + if (!arm_host_cpu_features.dtb_compatible) { + if (!kvm_enabled() || + !kvm_arm_get_host_cpu_features(&arm_host_cpu_features)) { + /* We can't report this error yet, so flag that we need to + * in arm_cpu_realizefn(). + */ + cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; + cpu->host_cpu_probe_failed = true; + return; + } } + + cpu->kvm_target = arm_host_cpu_features.target; + cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible; + env->features = arm_host_cpu_features.features; } static void kvm_arm_host_cpu_initfn(Object *obj) { - ARMHostCPUClass *ahcc = ARM_HOST_CPU_GET_CLASS(obj); ARMCPU *cpu = ARM_CPU(obj); - CPUARMState *env = &cpu->env; - cpu->kvm_target = ahcc->target; - cpu->dtb_compatible = ahcc->dtb_compatible; - env->features = ahcc->features; + kvm_arm_set_cpu_features_from_host(cpu); } static const TypeInfo host_arm_cpu_type_info = { @@ -163,8 +167,6 @@ static const TypeInfo host_arm_cpu_type_info = { .parent = TYPE_ARM_CPU, #endif .instance_init = kvm_arm_host_cpu_initfn, - .class_init = kvm_arm_host_cpu_class_init, - .class_size = sizeof(ARMHostCPUClass), }; int kvm_arch_init(MachineState *ms, KVMState *s) diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index f77c9c494b..1740cda47d 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -28,7 +28,7 @@ static inline void set_feature(uint64_t *features, int feature) *features |= 1ULL << feature; } -bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc) +bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and * fill out the ARMHostCPUClass fields accordingly. To do this @@ -74,13 +74,13 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc) return false; } - ahcc->target = init.target; + ahcf->target = init.target; /* This is not strictly blessed by the device tree binding docs yet, * but in practice the kernel does not care about this string so * there is no point maintaining an KVM_ARM_TARGET_* -> string table. */ - ahcc->dtb_compatible = "arm,arm-v7"; + ahcf->dtb_compatible = "arm,arm-v7"; for (i = 0; i < ARRAY_SIZE(idregs); i++) { ret = ioctl(fdarray[2], KVM_GET_ONE_REG, &idregs[i]); @@ -132,7 +132,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc) set_feature(&features, ARM_FEATURE_VFP4); } - ahcc->features = features; + ahcf->features = features; return true; } diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index ac728494a4..e0b8246283 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -443,7 +443,7 @@ static inline void unset_feature(uint64_t *features, int feature) *features &= ~(1ULL << feature); } -bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc) +bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and * fill out the ARMHostCPUClass fields accordingly. To do this @@ -471,8 +471,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc) return false; } - ahcc->target = init.target; - ahcc->dtb_compatible = "arm,arm-v8"; + ahcf->target = init.target; + ahcf->dtb_compatible = "arm,arm-v8"; kvm_arm_destroy_scratch_host_vcpu(fdarray); @@ -486,7 +486,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc) set_feature(&features, ARM_FEATURE_AARCH64); set_feature(&features, ARM_FEATURE_PMU); - ahcc->features = features; + ahcf->features = features; return true; } From patchwork Thu Mar 8 13:06:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 131004 Delivered-To: patches@linaro.org Received: by 10.46.66.2 with SMTP id p2csp6455825lja; Thu, 8 Mar 2018 05:06:34 -0800 (PST) X-Google-Smtp-Source: AG47ELu1YbPWFV1MK9PtnX8q2YJw/i2BHWu6w+WUsPq/+D2DEF23J27bjT0+RnJ99vGljhPBawKV X-Received: by 10.99.110.133 with SMTP id j127mr21299638pgc.79.1520514394798; Thu, 08 Mar 2018 05:06:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520514394; cv=none; d=google.com; s=arc-20160816; b=kpGUqd+5lg4PcpkniZgKT1htxLjHgm83nit9NqXtrIP0oCY3z/bbh+Q29ZCfjRK+BW pgC4RIIe5JF53mLnGcD4BpCFi0Ia+Sojp/C/A8/uNMWxcEf5gFeksd3WaQGJtA/sH0I7 s3IhAqBBzSh3cOHE5YkKlhemdXfAZLHew5lCD9hfDS01pwM6yfZyKrafFJF0GtUbHXoG BjU4mA8JA4VfKZDkwegDFYwPPDa7EpJr8D06eNtSgB6p4VTjlRyJegL9/9ifYLgQTclN JsarhZfqYxlZSVDhxMZdLA9H6CtqmbtwgT+IFn7anne3ohkBrvdG8kQVn2XM9ygFKjW9 Po9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=FzJU/kEruoIH3cfzo9Hc25ssSkXhrEypFBeW/d96WUw=; b=Nl4Aqn2E0yvsPDUlKIcZmNlXhk2YO0NsAOXlnVIosUYgpjRG/l/LQv1K7chGXlxQQ+ zafB8DtYzSTTc827lFNetOSG93bB8RzpRIfMSIyJFaGFK/sccM8JjwSdqEoOFJjFT5W5 qWFSV3C1Y0Qsw8KY2cSjjVXe/mTUvVnOpBkVXSmm75TEySi7nizoUIY0r8yOsVRgAgbT 2Ci1z79osKNgry9PT1pZpg4YHnZao38k8MooQQQppof7mOKwspe4HVq1jGa4ZMo7oaIG p1CqpphNPF5J4Y3/AR/DKYtoEt+24+rmZViLgZ2G08jVdVFXBcPbcvGZoA2LnE18rFVY YMxw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id p2si13022935pga.143.2018.03.08.05.06.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Mar 2018 05:06:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1etvFd-0005yV-Dv; Thu, 08 Mar 2018 13:06:29 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Igor Mammedov , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= , =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH v3 2/6] target/arm: Move definition of 'host' cpu type into cpu.c Date: Thu, 8 Mar 2018 13:06:22 +0000 Message-Id: <20180308130626.12393-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180308130626.12393-1-peter.maydell@linaro.org> References: <20180308130626.12393-1-peter.maydell@linaro.org> MIME-Version: 1.0 Move the definition of the 'host' cpu type into cpu.c, where all the other CPU types are defined. We can do this now we've decoupled it from the KVM-specific host feature probing. This means we now create the type unconditionally (assuming we were built with KVM support at all), but if you try to use it without -enable-kvm this will end up in the "host cpu probe failed and KVM not enabled" path in arm_cpu_realizefn(), for an appropriate error message. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- target/arm/cpu.c | 24 ++++++++++++++++++++++++ target/arm/kvm.c | 19 ------------------- 2 files changed, 24 insertions(+), 19 deletions(-) -- 2.16.2 Reviewed-by: Alex Bennée diff --git a/target/arm/cpu.c b/target/arm/cpu.c index abf9fb2160..1a58a2c094 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1858,6 +1858,26 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) #endif } +#ifdef CONFIG_KVM +static void arm_host_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + kvm_arm_set_cpu_features_from_host(cpu); +} + +static const TypeInfo host_arm_cpu_type_info = { + .name = TYPE_ARM_HOST_CPU, +#ifdef TARGET_AARCH64 + .parent = TYPE_AARCH64_CPU, +#else + .parent = TYPE_ARM_CPU, +#endif + .instance_init = arm_host_initfn, +}; + +#endif + static void cpu_register(const ARMCPUInfo *info) { TypeInfo type_info = { @@ -1902,6 +1922,10 @@ static void arm_cpu_register_types(void) cpu_register(info); info++; } + +#ifdef CONFIG_KVM + type_register_static(&host_arm_cpu_type_info); +#endif } type_init(arm_cpu_register_types) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 1c0e57690a..ecc39ac295 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -152,23 +152,6 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) env->features = arm_host_cpu_features.features; } -static void kvm_arm_host_cpu_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - kvm_arm_set_cpu_features_from_host(cpu); -} - -static const TypeInfo host_arm_cpu_type_info = { - .name = TYPE_ARM_HOST_CPU, -#ifdef TARGET_AARCH64 - .parent = TYPE_AARCH64_CPU, -#else - .parent = TYPE_ARM_CPU, -#endif - .instance_init = kvm_arm_host_cpu_initfn, -}; - int kvm_arch_init(MachineState *ms, KVMState *s) { /* For ARM interrupt delivery is always asynchronous, @@ -184,8 +167,6 @@ int kvm_arch_init(MachineState *ms, KVMState *s) cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); - type_register_static(&host_arm_cpu_type_info); - return 0; } From patchwork Thu Mar 8 13:06:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 130999 Delivered-To: patches@linaro.org Received: by 10.46.66.2 with SMTP id p2csp6455722lja; Thu, 8 Mar 2018 05:06:31 -0800 (PST) X-Google-Smtp-Source: AG47ELuDkccuIRm7TrwrO3e3tmIXmD5VhypaLmLckjlQ2AHQyR+qRmyT2jxEi9PdiKnGXm+3Q+Ak X-Received: by 10.46.113.17 with SMTP id m17mr17987492ljc.114.1520514391356; Thu, 08 Mar 2018 05:06:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520514391; cv=none; d=google.com; s=arc-20160816; b=S0cj/e3b3FpQtu0PhluYemnZ1VIaoJT9TpLoGB7U/qFz//o27PkjwxpgMI4wL0WRbW mvlUMhh3i+wSgSkJts1E1YPaL0RhnnCS1OQTiPbk0uWIt5xTIVzt+RF1lEmCBd9XN8Ec alKvmoBJUhDLPvkfwIGik+rbEyKHYMPPKdTH2/Ql/6QMdPS+yX2UaDlAhh7fJmpTLbx3 J5AXOwxQ4QoAjxJNNA0vwP78BLmxkIv1vcHdvxF30gTyi6jcLkJxh/L0VzSFs0Hw+Nhz 0gK9WPb+h2NkzTv7I1UTBbuwqLtIs6w2Ra2ALvyELTF15o/WvqPGpNoWkDA7XiVfC8Kw kgGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=cmm5ofVdvZsjmXVzFiVw1Rx7JV/kj/fnyczzDnJ6p7U=; b=LMK0GoNP/2mPiXfejsYL2XH+AEh0IH+eKJARTSt0NnmBUoFw9kFi2m3uIdV1Jg658b Wy57ngpXHvWT1M0shUkfHi8toOU+3wfGQFgDqyEaS0DINjE0nA3PDBabgG/Ke5nYoOmA ntdggoavsom/iS1Rw0nVssXM8c5/K4+ARk+b5s0h0hGpNERaLMpftlk22NRMzvpyfEbi FC1CTMEaGwi4f2JaswHN7kzIb5fvz0x+Pc9zRW4q9vWWrBVObM7yvsu2tYFQ3SfnvyjQ Rr/6CpTtjpq5SBjnhME2eZd0bhkZdczwlrijgGHaFnrLwgv1zlel3boHh5rNjhPr0xyt k02g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id w187si7512393lff.443.2018.03.08.05.06.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Mar 2018 05:06:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1etvFe-0005yt-45; Thu, 08 Mar 2018 13:06:30 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Igor Mammedov , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= , =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH v3 3/6] target/arm: Add "-cpu max" support Date: Thu, 8 Mar 2018 13:06:23 +0000 Message-Id: <20180308130626.12393-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180308130626.12393-1-peter.maydell@linaro.org> References: <20180308130626.12393-1-peter.maydell@linaro.org> Add support for "-cpu max" for ARM guests. This CPU type behaves like "-cpu host" when KVM is enabled, and like a system CPU with the maximum possible feature set otherwise. (Note that this means it won't be migratable across versions, as we will likely add features to it in future.) Signed-off-by: Peter Maydell --- target/arm/cpu-qom.h | 2 ++ target/arm/cpu.c | 24 ++++++++++++++++++++++++ target/arm/cpu64.c | 21 +++++++++++++++++++++ 3 files changed, 47 insertions(+) -- 2.16.2 Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index a42495bac9..d135ff8e06 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -33,6 +33,8 @@ struct arm_boot_info; #define ARM_CPU_GET_CLASS(obj) \ OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU) +#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU + /** * ARMCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1a58a2c094..e46ddcc613 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1697,6 +1697,27 @@ static void pxa270c5_initfn(Object *obj) cpu->reset_sctlr = 0x00000078; } +#ifndef TARGET_AARCH64 +/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); + * otherwise, a CPU with as many features enabled as our emulation supports. + * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; + * this only needs to handle 32 bits. + */ +static void arm_max_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + if (kvm_enabled()) { + kvm_arm_set_cpu_features_from_host(cpu); + } else { + cortex_a15_initfn(obj); + /* In future we might add feature bits here even if the + * real-world A15 doesn't implement them. + */ + } +} +#endif + #ifdef CONFIG_USER_ONLY static void arm_any_initfn(Object *obj) { @@ -1764,6 +1785,9 @@ static const ARMCPUInfo arm_cpus[] = { { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, +#ifndef TARGET_AARCH64 + { .name = "max", .initfn = arm_max_initfn }, +#endif #ifdef CONFIG_USER_ONLY { .name = "any", .initfn = arm_any_initfn }, #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 4228713b19..9042d3dfd1 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -28,6 +28,7 @@ #include "hw/arm/arm.h" #include "sysemu/sysemu.h" #include "sysemu/kvm.h" +#include "kvm_arm.h" static inline void set_feature(CPUARMState *env, int feature) { @@ -212,6 +213,25 @@ static void aarch64_a53_initfn(Object *obj) define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); } +/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); + * otherwise, a CPU with as many features enabled as our emulation supports. + * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; + * this only needs to handle 64 bits. + */ +static void aarch64_max_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + if (kvm_enabled()) { + kvm_arm_set_cpu_features_from_host(cpu); + } else { + aarch64_a57_initfn(obj); + /* In future we might add feature bits here even if the + * real-world A57 doesn't implement them. + */ + } +} + #ifdef CONFIG_USER_ONLY static void aarch64_any_initfn(Object *obj) { @@ -247,6 +267,7 @@ typedef struct ARMCPUInfo { static const ARMCPUInfo aarch64_cpus[] = { { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, + { .name = "max", .initfn = aarch64_max_initfn }, #ifdef CONFIG_USER_ONLY { .name = "any", .initfn = aarch64_any_initfn }, #endif From patchwork Thu Mar 8 13:06:24 2018 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by mx.google.com with ESMTPS id r31si14831025wrb.482.2018.03.08.05.06.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Mar 2018 05:06:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1etvFe-0005zA-SR; Thu, 08 Mar 2018 13:06:30 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Igor Mammedov , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= , =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH v3 4/6] target/arm: Make 'any' CPU just an alias for 'max' Date: Thu, 8 Mar 2018 13:06:24 +0000 Message-Id: <20180308130626.12393-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180308130626.12393-1-peter.maydell@linaro.org> References: <20180308130626.12393-1-peter.maydell@linaro.org> Now we have a working '-cpu max', the linux-user-only 'any' CPU is pretty much the same thing, so implement it that way. For the moment we don't add any of the extra feature bits to the system-emulation "max", because we don't set the ID register bits we would need to to advertise those features as present. Signed-off-by: Peter Maydell --- target/arm/cpu.c | 52 +++++++++++++++++++++++++---------------------- target/arm/cpu64.c | 59 ++++++++++++++++++++++++++---------------------------- 2 files changed, 56 insertions(+), 55 deletions(-) -- 2.16.2 Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e46ddcc613..6068efb8ff 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -965,9 +965,19 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) ObjectClass *oc; char *typename; char **cpuname; + const char *cpunamestr; cpuname = g_strsplit(cpu_model, ",", 1); - typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpuname[0]); + cpunamestr = cpuname[0]; +#ifdef CONFIG_USER_ONLY + /* For backwards compatibility usermode emulation allows "-cpu any", + * which has the same semantics as "-cpu max". + */ + if (!strcmp(cpunamestr, "any")) { + cpunamestr = "max"; + } +#endif + typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); oc = object_class_by_name(typename); g_strfreev(cpuname); g_free(typename); @@ -1711,29 +1721,23 @@ static void arm_max_initfn(Object *obj) kvm_arm_set_cpu_features_from_host(cpu); } else { cortex_a15_initfn(obj); - /* In future we might add feature bits here even if the - * real-world A15 doesn't implement them. - */ - } -} -#endif - #ifdef CONFIG_USER_ONLY -static void arm_any_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_VFP4); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); - set_feature(&cpu->env, ARM_FEATURE_V8_AES); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); - set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); - set_feature(&cpu->env, ARM_FEATURE_CRC); - set_feature(&cpu->env, ARM_FEATURE_V8_RDM); - set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); - cpu->midr = 0xffffffff; + /* We don't set these in system emulation mode for the moment, + * since we don't correctly set the ID registers to advertise them, + */ + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_V8_AES); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); + set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); + set_feature(&cpu->env, ARM_FEATURE_CRC); + set_feature(&cpu->env, ARM_FEATURE_V8_RDM); + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); +#endif + } } #endif @@ -1789,7 +1793,7 @@ static const ARMCPUInfo arm_cpus[] = { { .name = "max", .initfn = arm_max_initfn }, #endif #ifdef CONFIG_USER_ONLY - { .name = "any", .initfn = arm_any_initfn }, + { .name = "any", .initfn = arm_max_initfn }, #endif #endif { .name = NULL } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 9042d3dfd1..3429875787 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -226,38 +226,38 @@ static void aarch64_max_initfn(Object *obj) kvm_arm_set_cpu_features_from_host(cpu); } else { aarch64_a57_initfn(obj); - /* In future we might add feature bits here even if the - * real-world A57 doesn't implement them. +#ifdef CONFIG_USER_ONLY + /* We don't set these in system emulation mode for the moment, + * since we don't correctly set the ID registers to advertise them, + * and in some cases they're only available in AArch64 and not AArch32, + * whereas the architecture requires them to be present in both if + * present in either. */ + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_V8_AES); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); + set_feature(&cpu->env, ARM_FEATURE_V8_SM3); + set_feature(&cpu->env, ARM_FEATURE_V8_SM4); + set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); + set_feature(&cpu->env, ARM_FEATURE_CRC); + set_feature(&cpu->env, ARM_FEATURE_V8_RDM); + set_feature(&cpu->env, ARM_FEATURE_V8_FP16); + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); + /* For usermode -cpu max we can use a larger and more efficient DCZ + * blocksize since we don't have to follow what the hardware does. + */ + cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ + cpu->dcz_blocksize = 7; /* 512 bytes */ +#endif } } -#ifdef CONFIG_USER_ONLY -static void aarch64_any_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_VFP4); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - set_feature(&cpu->env, ARM_FEATURE_V8_AES); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); - set_feature(&cpu->env, ARM_FEATURE_V8_SM3); - set_feature(&cpu->env, ARM_FEATURE_V8_SM4); - set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); - set_feature(&cpu->env, ARM_FEATURE_CRC); - set_feature(&cpu->env, ARM_FEATURE_V8_RDM); - set_feature(&cpu->env, ARM_FEATURE_V8_FP16); - set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); - cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ - cpu->dcz_blocksize = 7; /* 512 bytes */ -} -#endif - typedef struct ARMCPUInfo { const char *name; void (*initfn)(Object *obj); @@ -268,9 +268,6 @@ static const ARMCPUInfo aarch64_cpus[] = { { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, { .name = "max", .initfn = aarch64_max_initfn }, -#ifdef CONFIG_USER_ONLY - { .name = "any", .initfn = aarch64_any_initfn }, -#endif { .name = NULL } }; From patchwork Thu Mar 8 13:06:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 131001 Delivered-To: patches@linaro.org Received: by 10.46.66.2 with SMTP id p2csp6455748lja; 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[2001:8b0:1d0::2]) by mx.google.com with ESMTPS id p3si15141038wrc.201.2018.03.08.05.06.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Mar 2018 05:06:32 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1etvFf-0005zS-KW; Thu, 08 Mar 2018 13:06:31 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Igor Mammedov , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= , =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH v3 5/6] hw/arm/virt: Add "max" to the list of CPU types "virt" supports Date: Thu, 8 Mar 2018 13:06:25 +0000 Message-Id: <20180308130626.12393-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180308130626.12393-1-peter.maydell@linaro.org> References: <20180308130626.12393-1-peter.maydell@linaro.org> Allow the virt board to support '-cpu max' in the same way it already handles '-cpu host'. Signed-off-by: Peter Maydell --- hw/arm/virt.c | 1 + 1 file changed, 1 insertion(+) -- 2.16.2 Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/virt.c b/hw/arm/virt.c index dbb3c8036a..cda4b83586 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -169,6 +169,7 @@ static const char *valid_cpus[] = { ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("host"), + ARM_CPU_TYPE_NAME("max"), }; static bool cpu_type_valid(const char *cpu) From patchwork Thu Mar 8 13:06:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 131002 Delivered-To: patches@linaro.org Received: by 10.46.66.2 with SMTP id p2csp6455782lja; Thu, 8 Mar 2018 05:06:33 -0800 (PST) X-Google-Smtp-Source: AG47ELvocb7hJ935bbR5NbJXOWLamlTYJrL/4HgH3e1jnIh28lBZ3SFRZIJ8sKLqurnkbKyHhX1W X-Received: by 10.25.228.18 with SMTP id b18mr15088802lfh.61.1520514393062; Thu, 08 Mar 2018 05:06:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520514393; cv=none; d=google.com; s=arc-20160816; b=I7n0+OjjGaLpxrqm3M7PG+FWaGaLiQd/2T4jfnyG3+4j0NVI8legStFiXZ+MgITCRr aeKpDhFiYRekAKM9uDVJjpy4YG0ops2RC4BapJ/lbs6nFYpqb5kwx7dHf96QlgDOEi7a h19fuRYxP2zOUqO76m8h1RrFAhRhpMlpua5PJnUAASMyL2w1655qBKueBOxfsKk52MhC 4NYqC6Yo7zcivIRW7qj+Jv2zmzhnah7bUtbzPGomHl/WJR9hKVnwZ36mxfN2H0KvLL7B J001HTxskWUua0kII2TjtLqnYWlyY2Hmp1a6x4jab/ItbK522i9XnuIdcgvbK8ldd3Pk i/EQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=swZCpyIxmNtZupe/BWVZaMk/478ba7WYRGLlZWC5elM=; b=Q0xlmzruuvqVS7tJ32+/t5VmneuEuwhjgabsbsWjzN4/HFoaGWIQhJUoyNAeCIjfVh hDSrypTGi+UAkW8ixxQQAmyIhrL4g14jsO7m0yATbs+7lk/gk25xb0hSKSRrIDAmsUE4 VictFp8Xw0jhl+ScVBrWZO4pRu9jb+9gV6Xm7wpUhlxg8kcbLoN/4C6KwPHKOe8XIrEE 5ncLUnSBax1LZbgbCSK0fC8fAdNB7glZ6ZSJTAccw5UJBiJ/vsh7N1CYrYKIduTYuOWc HAaBiP/wlt5HzxqG3EonMmurBqi6alfRcCB6KPhEsk1IvSxhHhUimj66qtUClUwRz+0d Kk/w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id o11si8121864lfi.411.2018.03.08.05.06.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Mar 2018 05:06:33 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1etvFg-0005zj-9z; Thu, 08 Mar 2018 13:06:32 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Igor Mammedov , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= , =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH v3 6/6] hw/arm/virt: Support -machine gic-version=max Date: Thu, 8 Mar 2018 13:06:26 +0000 Message-Id: <20180308130626.12393-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180308130626.12393-1-peter.maydell@linaro.org> References: <20180308130626.12393-1-peter.maydell@linaro.org> Add support for passing 'max' to -machine gic-version. By analogy with the -cpu max option, this picks the "best available" GIC version whether you're using KVM or TCG, so it behaves like 'host' when using KVM, and gives you GICv3 when using TCG. Also like '-cpu host', using -machine gic-version=max' means there is no guarantee of migration compatibility between QEMU versions; in future 'max' might mean '4'. Signed-off-by: Peter Maydell --- hw/arm/virt.c | 29 +++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) -- 2.16.2 Reviewed-by: Alex Bennée diff --git a/hw/arm/virt.c b/hw/arm/virt.c index cda4b83586..2c07245047 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1207,16 +1207,23 @@ static void machvirt_init(MachineState *machine) /* We can probe only here because during property set * KVM is not available yet */ - if (!vms->gic_version) { + if (vms->gic_version <= 0) { + /* "host" or "max" */ if (!kvm_enabled()) { - error_report("gic-version=host requires KVM"); - exit(1); - } - - vms->gic_version = kvm_arm_vgic_probe(); - if (!vms->gic_version) { - error_report("Unable to determine GIC version supported by host"); - exit(1); + if (vms->gic_version == 0) { + error_report("gic-version=host requires KVM"); + exit(1); + } else { + /* "max": currently means 3 for TCG */ + vms->gic_version = 3; + } + } else { + vms->gic_version = kvm_arm_vgic_probe(); + if (!vms->gic_version) { + error_report( + "Unable to determine GIC version supported by host"); + exit(1); + } } } @@ -1480,9 +1487,11 @@ static void virt_set_gic_version(Object *obj, const char *value, Error **errp) vms->gic_version = 2; } else if (!strcmp(value, "host")) { vms->gic_version = 0; /* Will probe later */ + } else if (!strcmp(value, "max")) { + vms->gic_version = -1; /* Will probe later */ } else { error_setg(errp, "Invalid gic-version value"); - error_append_hint(errp, "Valid values are 3, 2, host.\n"); + error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); } }