From patchwork Tue Feb 2 07:16:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 374600 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp1978991jah; Mon, 1 Feb 2021 23:22:45 -0800 (PST) X-Google-Smtp-Source: ABdhPJyTdBFvBO+A5nmWXH58aK/UAb3U+DTZAjq68rVzSbvfbfb5coW2ZBi7/Xrt+4LOS/+jvNG6 X-Received: by 2002:a17:906:1fda:: with SMTP id e26mr12934052ejt.195.1612250565125; Mon, 01 Feb 2021 23:22:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612250565; cv=none; d=google.com; s=arc-20160816; b=QsC5+OwBUSYW0Y3YmbuOE8cw4OeDWT9wUJwcY8zTwebBuWm2mCxqbPNOcHXu6fxzcl fSmEHZWXygn/AgMxHjMHd8VlBs4Tu9KYLWqLyrmSO/MRurQ65sOFoWyjxZhDLC1audnu 6IWW4GCLev2uODoPDYxdEGSO4XmId+SiN4rMZ1oVs17hrnxJBVaHNGTvIXqjmvCfimCB fwHl73bWWFoSSdbOCDOU8Euh7tpRrkuIZbfTv++HFqBHfc7nMke5cuTs8FV1GR2jW7Ce zv7g8ngKwflZGpLopr1xy9zYLZTU5rv66aXGkpoUyRTIrWQvOOAt6NykXnSaftLvwrRo n9EQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=OKgvmkVfnDYraB4FpoZzyau2cU7eV2objgOUnU0blYk=; b=pWC7uWliyRHKFTv5+zQyxJfej6VeE3Lq+CT47FpVg9JdNaO8JVrt6wFKz+Y6Tkuyr+ cXaMbNRLXk4vnNvghzdfpFAcGycGw/G95rhGEkaIP4neOqRLZ9ByzAo4mzTvkZCk7I0p vzKpzPEp3sgLbii+wV9K3oZIUiLLiWzdWYVY76IJF3jfkgPm0OjGsEbFCz1xF5luYVsi +561kP2kkr8AzhYq4/h5OVfd8E2oc8dVKiisYh4WIYIRpfuccUdfa+QYgZ/NfwJBMHp2 qOW2p7DCNC4of6k1XprB13CUIFYCm5NR8sDg5aW1qDsznEcmMrIDY0hQm+kphVIL9UES +A6Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id w3si11914746edt.463.2021.02.01.23.22.44; Mon, 01 Feb 2021 23:22:45 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231522AbhBBHWJ (ORCPT + 6 others); Tue, 2 Feb 2021 02:22:09 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:12004 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231670AbhBBHWI (ORCPT ); Tue, 2 Feb 2021 02:22:08 -0500 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4DVGRW10dxzjHPn; Tue, 2 Feb 2021 15:20:07 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.176.220) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.498.0; Tue, 2 Feb 2021 15:21:18 +0800 From: Zhen Lei To: Russell King , Greg Kroah-Hartman , Will Deacon , "Haojian Zhuang" , Arnd Bergmann , "Rob Herring" , Wei Xu , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH v7 1/4] ARM: LPAE: Use phys_addr_t instead of unsigned long in outercache hooks Date: Tue, 2 Feb 2021 15:16:45 +0800 Message-ID: <20210202071648.1776-2-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20210202071648.1776-1-thunder.leizhen@huawei.com> References: <20210202071648.1776-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.176.220] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The outercache of some Hisilicon SOCs support physical addresses wider than 32-bits. The unsigned long datatype is not sufficient for mapping physical addresses >= 4GB. The commit ad6b9c9d78b9 ("ARM: 6671/1: LPAE: use phys_addr_t instead of unsigned long in outercache functions") has already modified the outercache functions. But the parameters of the outercache hooks are not changed. This patch use phys_addr_t instead of unsigned long in outercache hooks: inv_range, clean_range, flush_range. To ensure the outercache that does not support LPAE works properly, do cast phys_addr_t to unsigned long by adding a group of temporary variables. For example: -static void l2c220_inv_range(unsigned long start, unsigned long end) +static void l2c220_inv_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; Note that the outercache functions have been doing this cast before this patch. So now, the cast is just moved into the outercache hook functions. No functional change. Signed-off-by: Zhen Lei Reviewed-by: Arnd Bergmann --- arch/arm/include/asm/outercache.h | 6 ++-- arch/arm/mm/cache-feroceon-l2.c | 15 ++++++++-- arch/arm/mm/cache-l2x0.c | 50 ++++++++++++++++++++++--------- arch/arm/mm/cache-tauros2.c | 15 ++++++++-- arch/arm/mm/cache-uniphier.c | 6 ++-- arch/arm/mm/cache-xsc3l2.c | 12 ++++++-- 6 files changed, 75 insertions(+), 29 deletions(-) -- 2.26.0.106.g9fadedd diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h index 3364637755e86aa..4cee1ea0c15449a 100644 --- a/arch/arm/include/asm/outercache.h +++ b/arch/arm/include/asm/outercache.h @@ -14,9 +14,9 @@ struct l2x0_regs; struct outer_cache_fns { - void (*inv_range)(unsigned long, unsigned long); - void (*clean_range)(unsigned long, unsigned long); - void (*flush_range)(unsigned long, unsigned long); + void (*inv_range)(phys_addr_t, phys_addr_t); + void (*clean_range)(phys_addr_t, phys_addr_t); + void (*flush_range)(phys_addr_t, phys_addr_t); void (*flush_all)(void); void (*disable)(void); #ifdef CONFIG_OUTER_CACHE_SYNC diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c index 5c1b7a7b9af6300..10f909744d5e963 100644 --- a/arch/arm/mm/cache-feroceon-l2.c +++ b/arch/arm/mm/cache-feroceon-l2.c @@ -168,8 +168,11 @@ static unsigned long calc_range_end(unsigned long start, unsigned long end) return range_end; } -static void feroceon_l2_inv_range(unsigned long start, unsigned long end) +static void feroceon_l2_inv_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; + /* * Clean and invalidate partial first cache line. */ @@ -198,8 +201,11 @@ static void feroceon_l2_inv_range(unsigned long start, unsigned long end) dsb(); } -static void feroceon_l2_clean_range(unsigned long start, unsigned long end) +static void feroceon_l2_clean_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; + /* * If L2 is forced to WT, the L2 will always be clean and we * don't need to do anything here. @@ -217,8 +223,11 @@ static void feroceon_l2_clean_range(unsigned long start, unsigned long end) dsb(); } -static void feroceon_l2_flush_range(unsigned long start, unsigned long end) +static void feroceon_l2_flush_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; + start &= ~(CACHE_LINE_SIZE - 1); end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1); while (start != end) { diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 43d91bfd2360086..cdaddd772b09ede 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -184,8 +184,10 @@ static void __l2c210_op_pa_range(void __iomem *reg, unsigned long start, } } -static void l2c210_inv_range(unsigned long start, unsigned long end) +static void l2c210_inv_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; void __iomem *base = l2x0_base; if (start & (CACHE_LINE_SIZE - 1)) { @@ -203,8 +205,10 @@ static void l2c210_inv_range(unsigned long start, unsigned long end) __l2c210_cache_sync(base); } -static void l2c210_clean_range(unsigned long start, unsigned long end) +static void l2c210_clean_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; void __iomem *base = l2x0_base; start &= ~(CACHE_LINE_SIZE - 1); @@ -212,8 +216,10 @@ static void l2c210_clean_range(unsigned long start, unsigned long end) __l2c210_cache_sync(base); } -static void l2c210_flush_range(unsigned long start, unsigned long end) +static void l2c210_flush_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; void __iomem *base = l2x0_base; start &= ~(CACHE_LINE_SIZE - 1); @@ -304,8 +310,10 @@ static unsigned long l2c220_op_pa_range(void __iomem *reg, unsigned long start, return flags; } -static void l2c220_inv_range(unsigned long start, unsigned long end) +static void l2c220_inv_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; void __iomem *base = l2x0_base; unsigned long flags; @@ -331,8 +339,10 @@ static void l2c220_inv_range(unsigned long start, unsigned long end) raw_spin_unlock_irqrestore(&l2x0_lock, flags); } -static void l2c220_clean_range(unsigned long start, unsigned long end) +static void l2c220_clean_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; void __iomem *base = l2x0_base; unsigned long flags; @@ -350,8 +360,10 @@ static void l2c220_clean_range(unsigned long start, unsigned long end) raw_spin_unlock_irqrestore(&l2x0_lock, flags); } -static void l2c220_flush_range(unsigned long start, unsigned long end) +static void l2c220_flush_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; void __iomem *base = l2x0_base; unsigned long flags; @@ -464,8 +476,10 @@ static const struct l2c_init_data l2c220_data = { * Affects: store buffer * store buffer is not automatically drained. */ -static void l2c310_inv_range_erratum(unsigned long start, unsigned long end) +static void l2c310_inv_range_erratum(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; void __iomem *base = l2x0_base; if ((start | end) & (CACHE_LINE_SIZE - 1)) { @@ -496,8 +510,10 @@ static void l2c310_inv_range_erratum(unsigned long start, unsigned long end) __l2c210_cache_sync(base); } -static void l2c310_flush_range_erratum(unsigned long start, unsigned long end) +static void l2c310_flush_range_erratum(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; raw_spinlock_t *lock = &l2x0_lock; unsigned long flags; void __iomem *base = l2x0_base; @@ -1400,12 +1416,12 @@ static void aurora_pa_range(unsigned long start, unsigned long end, start = range_end; } } -static void aurora_inv_range(unsigned long start, unsigned long end) +static void aurora_inv_range(phys_addr_t start, phys_addr_t end) { aurora_pa_range(start, end, AURORA_INVAL_RANGE_REG); } -static void aurora_clean_range(unsigned long start, unsigned long end) +static void aurora_clean_range(phys_addr_t start, phys_addr_t end) { /* * If L2 is forced to WT, the L2 will always be clean and we @@ -1415,7 +1431,7 @@ static void aurora_clean_range(unsigned long start, unsigned long end) aurora_pa_range(start, end, AURORA_CLEAN_RANGE_REG); } -static void aurora_flush_range(unsigned long start, unsigned long end) +static void aurora_flush_range(phys_addr_t start, phys_addr_t end) { if (l2_wt_override) aurora_pa_range(start, end, AURORA_INVAL_RANGE_REG); @@ -1604,8 +1620,10 @@ static inline unsigned long bcm_l2_phys_addr(unsigned long addr) return addr + BCM_VC_EMI_OFFSET; } -static void bcm_inv_range(unsigned long start, unsigned long end) +static void bcm_inv_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; unsigned long new_start, new_end; BUG_ON(start < BCM_SYS_EMI_START_ADDR); @@ -1631,8 +1649,10 @@ static void bcm_inv_range(unsigned long start, unsigned long end) new_end); } -static void bcm_clean_range(unsigned long start, unsigned long end) +static void bcm_clean_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; unsigned long new_start, new_end; BUG_ON(start < BCM_SYS_EMI_START_ADDR); @@ -1658,8 +1678,10 @@ static void bcm_clean_range(unsigned long start, unsigned long end) new_end); } -static void bcm_flush_range(unsigned long start, unsigned long end) +static void bcm_flush_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; unsigned long new_start, new_end; BUG_ON(start < BCM_SYS_EMI_START_ADDR); diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c index 88255bea65e41e6..d768bbb5e05c690 100644 --- a/arch/arm/mm/cache-tauros2.c +++ b/arch/arm/mm/cache-tauros2.c @@ -66,8 +66,11 @@ static inline void tauros2_inv_pa(unsigned long addr) */ #define CACHE_LINE_SIZE 32 -static void tauros2_inv_range(unsigned long start, unsigned long end) +static void tauros2_inv_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; + /* * Clean and invalidate partial first cache line. */ @@ -95,8 +98,11 @@ static void tauros2_inv_range(unsigned long start, unsigned long end) dsb(); } -static void tauros2_clean_range(unsigned long start, unsigned long end) +static void tauros2_clean_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; + start &= ~(CACHE_LINE_SIZE - 1); while (start < end) { tauros2_clean_pa(start); @@ -106,8 +112,11 @@ static void tauros2_clean_range(unsigned long start, unsigned long end) dsb(); } -static void tauros2_flush_range(unsigned long start, unsigned long end) +static void tauros2_flush_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; + start &= ~(CACHE_LINE_SIZE - 1); while (start < end) { tauros2_clean_inv_pa(start); diff --git a/arch/arm/mm/cache-uniphier.c b/arch/arm/mm/cache-uniphier.c index ff2881458504329..e2508358e9f4082 100644 --- a/arch/arm/mm/cache-uniphier.c +++ b/arch/arm/mm/cache-uniphier.c @@ -250,17 +250,17 @@ static void uniphier_cache_maint_all(u32 operation) __uniphier_cache_maint_all(data, operation); } -static void uniphier_cache_inv_range(unsigned long start, unsigned long end) +static void uniphier_cache_inv_range(phys_addr_t start, phys_addr_t end) { uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_INV); } -static void uniphier_cache_clean_range(unsigned long start, unsigned long end) +static void uniphier_cache_clean_range(phys_addr_t start, phys_addr_t end) { uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_CLEAN); } -static void uniphier_cache_flush_range(unsigned long start, unsigned long end) +static void uniphier_cache_flush_range(phys_addr_t start, phys_addr_t end) { uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_FLUSH); } diff --git a/arch/arm/mm/cache-xsc3l2.c b/arch/arm/mm/cache-xsc3l2.c index d20d7af02d10fc0..5814731653d9091 100644 --- a/arch/arm/mm/cache-xsc3l2.c +++ b/arch/arm/mm/cache-xsc3l2.c @@ -83,8 +83,10 @@ static inline unsigned long l2_map_va(unsigned long pa, unsigned long prev_va) #endif } -static void xsc3_l2_inv_range(unsigned long start, unsigned long end) +static void xsc3_l2_inv_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; unsigned long vaddr; if (start == 0 && end == -1ul) { @@ -127,8 +129,10 @@ static void xsc3_l2_inv_range(unsigned long start, unsigned long end) dsb(); } -static void xsc3_l2_clean_range(unsigned long start, unsigned long end) +static void xsc3_l2_clean_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; unsigned long vaddr; vaddr = -1; /* to force the first mapping */ @@ -165,8 +169,10 @@ static inline void xsc3_l2_flush_all(void) dsb(); } -static void xsc3_l2_flush_range(unsigned long start, unsigned long end) +static void xsc3_l2_flush_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; unsigned long vaddr; if (start == 0 && end == -1ul) { From patchwork Tue Feb 2 07:16:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 374601 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp1978998jah; Mon, 1 Feb 2021 23:22:45 -0800 (PST) X-Google-Smtp-Source: ABdhPJz0Z5NbgS6WuHUq1D4oNFJIl4Ayy/iOn3qP4z7RkZpVy7mP+qAqq1qm/iGTIBsKTjo42ef6 X-Received: by 2002:a17:906:7cd8:: with SMTP id h24mr20817048ejp.511.1612250565665; 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[23.128.96.18]) by mx.google.com with ESMTP id w3si11914746edt.463.2021.02.01.23.22.45; Mon, 01 Feb 2021 23:22:45 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231670AbhBBHWP (ORCPT + 6 others); Tue, 2 Feb 2021 02:22:15 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:12096 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232087AbhBBHWM (ORCPT ); Tue, 2 Feb 2021 02:22:12 -0500 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4DVGRb62nLz162wf; Tue, 2 Feb 2021 15:20:11 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.176.220) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.498.0; Tue, 2 Feb 2021 15:21:19 +0800 From: Zhen Lei To: Russell King , Greg Kroah-Hartman , Will Deacon , "Haojian Zhuang" , Arnd Bergmann , Rob Herring , Wei Xu , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH v7 2/4] ARM: hisi: add support for Kunpeng50x SoC Date: Tue, 2 Feb 2021 15:16:46 +0800 Message-ID: <20210202071648.1776-3-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20210202071648.1776-1-thunder.leizhen@huawei.com> References: <20210202071648.1776-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.176.220] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable support for the Hisilicon Kunpeng506 and Kunpeng509 SoC. Signed-off-by: Zhen Lei Reviewed-by: Arnd Bergmann --- arch/arm/mach-hisi/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.26.0.106.g9fadedd diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig index 2e980f834a6aa1b..a004eac24b243af 100644 --- a/arch/arm/mach-hisi/Kconfig +++ b/arch/arm/mach-hisi/Kconfig @@ -55,6 +55,12 @@ config ARCH_HIX5HD2 help Support for Hisilicon HIX5HD2 SoC family +config ARCH_KUNPENG50X + bool "Hisilicon Kunpeng50x family" + depends on ARCH_MULTI_V7 + help + Support for Hisilicon Kunpeng506 and Kunpeng509 SoC family + config ARCH_SD5203 bool "Hisilicon SD5203 family" depends on ARCH_MULTI_V5 From patchwork Tue Feb 2 07:16:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 374602 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp1979009jah; Mon, 1 Feb 2021 23:22:47 -0800 (PST) X-Google-Smtp-Source: ABdhPJxZdLENU5d35DfpVgw1WkAippZ0AciInFfhavF03xDTa4VA/AdRUWOvsoyyDyySI/SzzNjn X-Received: by 2002:a17:906:84d7:: with SMTP id f23mr5790749ejy.87.1612250567361; Mon, 01 Feb 2021 23:22:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612250567; cv=none; d=google.com; s=arc-20160816; b=W1h6gO66RJku7pIhgY5E9hGxyoRLAQFJr+JWKvKVg0kBG9/4+NVgYnmV3zQkXtI427 moe13D3xadvLmCYkxONgChXvf4sHXGry+YxxI0InZhYjhRUWY/Xr/5Rg6jbGg+ozPpQs UL18l1I9Etgiu8heC01K4BvwG7afDBZJJOhmxgpCD9ny+DVgExThI/MnTYuGDN34aapr A0awEGgkVShB7k3wAaacUjDAj8ILAYACqINdPckIR6/36PdJjlVTkOFgV0juIYpw/wXL 7TVH6PW362vr9/RQTsNi9dZrZCAdjzgh3LhaG7rs+CNaDeq8fouX9pPTKbGgoABf84+7 ud/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=+xcN+kIaowoRUGj3w0U6AbldgEm61PML9VrtqOpaWCk=; b=oIjn506m+XqPneN6XffrrTDzGGb8hRR+b1wEKm/ksExUaxpOd8YTFa4TXalZq6ZqXu Qb3vx4HELT6Mxn1wyphbD75GQnBYu1SstwIclIYdcZgBVImQ7CHzQ4z0R3gHhkG3Rh8i WFgrts2phBV9tQgDuj9/E5GT/n5enQVoU51jJeE+FjVsSVQzUGz83leYO6QzlFmYUe5T nA+YV94SYpaRePRM9qMMPmkZtNxJYiy+q1RlOixFqCk9/xLR9zdi3yWokf48tClUK/ML 1vbOkaPyGwka6f5IbsaGCHQ2nohWFesOVLHbd1dHGDAX+JMXOpx0JhHxxEHK2CtkjK8z chmQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id w3si11914746edt.463.2021.02.01.23.22.47; Mon, 01 Feb 2021 23:22:47 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232165AbhBBHWP (ORCPT + 6 others); Tue, 2 Feb 2021 02:22:15 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:12097 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232108AbhBBHWN (ORCPT ); Tue, 2 Feb 2021 02:22:13 -0500 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4DVGRb5kbWz162Kl; Tue, 2 Feb 2021 15:20:11 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.176.220) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.498.0; Tue, 2 Feb 2021 15:21:19 +0800 From: Zhen Lei To: Russell King , Greg Kroah-Hartman , Will Deacon , "Haojian Zhuang" , Arnd Bergmann , Rob Herring , Wei Xu , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH v7 3/4] dt-bindings: arm: hisilicon: Add binding for Kunpeng L3 cache controller Date: Tue, 2 Feb 2021 15:16:47 +0800 Message-ID: <20210202071648.1776-4-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20210202071648.1776-1-thunder.leizhen@huawei.com> References: <20210202071648.1776-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.176.220] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add devicetree binding for Hisilicon Kunpeng L3 cache controller. Signed-off-by: Zhen Lei Reviewed-by: Arnd Bergmann --- .../arm/hisilicon/kunpeng-l3cache.yaml | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml -- 2.26.0.106.g9fadedd Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml b/Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml new file mode 100644 index 000000000000000..5bf33c0e4d14b7f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/kunpeng-l3cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Kunpeng L3 cache controller + +maintainers: + - Wei Xu + +description: | + The Hisilicon Kunpeng L3 outer cache controller supports a maximum of 36-bit + physical addresses. The data cached in the L3 outer cache can be operated + based on the physical address range or the entire cache. + +properties: + compatible: + items: + - enum: + - hisilicon,kunpeng506-l3cache + - hisilicon,kunpeng509-l3cache + - const: hisilicon,kunpeng-l3cache + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + l3cache@f302b000 { + compatible = "hisilicon,kunpeng509-l3cache", "hisilicon,kunpeng-l3cache"; + reg = <0xf302b000 0x1000>; + }; +... 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[23.128.96.18]) by mx.google.com with ESMTP id w3si11914746edt.463.2021.02.01.23.22.49; Mon, 01 Feb 2021 23:22:50 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232180AbhBBHWU (ORCPT + 6 others); Tue, 2 Feb 2021 02:22:20 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:12095 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232137AbhBBHWP (ORCPT ); Tue, 2 Feb 2021 02:22:15 -0500 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4DVGRb6KX6z1631T; Tue, 2 Feb 2021 15:20:11 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.176.220) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.498.0; Tue, 2 Feb 2021 15:21:20 +0800 From: Zhen Lei To: Russell King , Greg Kroah-Hartman , Will Deacon , "Haojian Zhuang" , Arnd Bergmann , Rob Herring , Wei Xu , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH v7 4/4] ARM: Add support for Hisilicon Kunpeng L3 cache controller Date: Tue, 2 Feb 2021 15:16:48 +0800 Message-ID: <20210202071648.1776-5-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20210202071648.1776-1-thunder.leizhen@huawei.com> References: <20210202071648.1776-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.176.220] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for the Hisilicon Kunpeng L3 cache controller as used with Kunpeng506 and Kunpeng509 SoCs. These Hisilicon SoCs support LPAE, so the physical addresses is wider than 32-bits, but the actual bit width does not exceed 36 bits. When the cache operation is performed based on the address range, the upper 30 bits of the physical address are recorded in registers L3_MAINT_START and L3_MAINT_END, and ignore the lower 6 bits cacheline offset. Signed-off-by: Zhen Lei Reviewed-by: Arnd Bergmann --- arch/arm/mm/Kconfig | 10 ++ arch/arm/mm/Makefile | 1 + arch/arm/mm/cache-kunpeng-l3.c | 178 +++++++++++++++++++++++++++++++++ 3 files changed, 189 insertions(+) create mode 100644 arch/arm/mm/cache-kunpeng-l3.c -- 2.26.0.106.g9fadedd diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 02692fbe2db5c59..d2082503de053d2 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -1070,6 +1070,16 @@ config CACHE_XSC3L2 help This option enables the L2 cache on XScale3. +config CACHE_KUNPENG_L3 + bool "Enable the Hisilicon Kunpeng L3 cache controller" + depends on ARCH_KUNPENG50X && OF + default y + select OUTER_CACHE + help + This option enables the Kunpeng L3 cache controller on Hisilicon + Kunpeng506 and Kunpeng509 SoCs. It supports a maximum of 36-bit + physical addresses. + config ARM_L1_CACHE_SHIFT_6 bool default y if CPU_V7 diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index 3510503bc5e688b..ececc5489e353eb 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -112,6 +112,7 @@ obj-$(CONFIG_CACHE_L2X0_PMU) += cache-l2x0-pmu.o obj-$(CONFIG_CACHE_XSC3L2) += cache-xsc3l2.o obj-$(CONFIG_CACHE_TAUROS2) += cache-tauros2.o obj-$(CONFIG_CACHE_UNIPHIER) += cache-uniphier.o +obj-$(CONFIG_CACHE_KUNPENG_L3) += cache-kunpeng-l3.o KASAN_SANITIZE_kasan_init.o := n obj-$(CONFIG_KASAN) += kasan_init.o diff --git a/arch/arm/mm/cache-kunpeng-l3.c b/arch/arm/mm/cache-kunpeng-l3.c new file mode 100644 index 000000000000000..64f892de9d68058 --- /dev/null +++ b/arch/arm/mm/cache-kunpeng-l3.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021 Hisilicon Limited. + */ + +#include +#include +#include +#include + +#include + +#define L3_CACHE_LINE_SHITF 6 + +#define L3_CTRL 0x0 +#define L3_CTRL_ENABLE (1U << 0) +#define L3_CTRL_DISABLE (0U << 0) + +#define L3_AUCTRL 0x4 +#define L3_AUCTRL_EVENT_EN BIT(23) +#define L3_AUCTRL_ECC_EN BIT(8) + +#define L3_MAINT_CTRL 0x20 +#define L3_MAINT_RANGE_MASK GENMASK(3, 3) +#define L3_MAINT_RANGE_ALL (0U << 3) +#define L3_MAINT_RANGE_ADDR (1U << 3) +#define L3_MAINT_TYPE_MASK GENMASK(2, 1) +#define L3_MAINT_TYPE_CLEAN (1U << 1) +#define L3_MAINT_TYPE_INV (2U << 1) +#define L3_MAINT_TYPE_FLUSH (3U << 1) +#define L3_MAINT_STATUS_MASK GENMASK(0, 0) +#define L3_MAINT_STATUS_START (1U << 0) +#define L3_MAINT_STATUS_END (0U << 0) + +#define L3_MAINT_START 0x24 +#define L3_MAINT_END 0x28 + +static DEFINE_RAW_SPINLOCK(l3cache_lock); +static void __iomem *l3_ctrl_base; + +/* + * All read and write operations on L3 cache registers are protected by the + * spinlock, except for l3cache_init(). Each time the L3 cache operation is + * performed, all related information is filled into its registers. Therefore, + * there is no memory order problem when only _relaxed() functions are used. + * This can help us achieve some performance improvement: + * 1) The readl_relaxed() is about 20ns faster than readl(). + * 2) The writel_relaxed() is about 123ns faster than writel(). + */ +static void l3cache_maint_common(u32 range, u32 op_type) +{ + u32 reg; + + reg = readl_relaxed(l3_ctrl_base + L3_MAINT_CTRL); + reg &= ~(L3_MAINT_RANGE_MASK | L3_MAINT_TYPE_MASK); + reg |= range | op_type; + reg |= L3_MAINT_STATUS_START; + writel_relaxed(reg, l3_ctrl_base + L3_MAINT_CTRL); + + /* Wait until the hardware maintenance operation is complete. */ + do { + cpu_relax(); + reg = readl_relaxed(l3_ctrl_base + L3_MAINT_CTRL); + } while ((reg & L3_MAINT_STATUS_MASK) != L3_MAINT_STATUS_END); +} + +static void l3cache_maint_range(phys_addr_t start, phys_addr_t end, u32 op_type) +{ + start = start >> L3_CACHE_LINE_SHITF; + end = ((end - 1) >> L3_CACHE_LINE_SHITF) + 1; + + writel_relaxed(start, l3_ctrl_base + L3_MAINT_START); + writel_relaxed(end, l3_ctrl_base + L3_MAINT_END); + + l3cache_maint_common(L3_MAINT_RANGE_ADDR, op_type); +} + +static inline void l3cache_flush_all_nolock(void) +{ + l3cache_maint_common(L3_MAINT_RANGE_ALL, L3_MAINT_TYPE_FLUSH); +} + +static void l3cache_flush_all(void) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&l3cache_lock, flags); + l3cache_flush_all_nolock(); + raw_spin_unlock_irqrestore(&l3cache_lock, flags); +} + +static void l3cache_inv_range(phys_addr_t start, phys_addr_t end) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&l3cache_lock, flags); + l3cache_maint_range(start, end, L3_MAINT_TYPE_INV); + raw_spin_unlock_irqrestore(&l3cache_lock, flags); +} + +static void l3cache_clean_range(phys_addr_t start, phys_addr_t end) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&l3cache_lock, flags); + l3cache_maint_range(start, end, L3_MAINT_TYPE_CLEAN); + raw_spin_unlock_irqrestore(&l3cache_lock, flags); +} + +static void l3cache_flush_range(phys_addr_t start, phys_addr_t end) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&l3cache_lock, flags); + l3cache_maint_range(start, end, L3_MAINT_TYPE_FLUSH); + raw_spin_unlock_irqrestore(&l3cache_lock, flags); +} + +static void l3cache_disable(void) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&l3cache_lock, flags); + l3cache_flush_all_nolock(); + writel_relaxed(L3_CTRL_DISABLE, l3_ctrl_base + L3_CTRL); + raw_spin_unlock_irqrestore(&l3cache_lock, flags); +} + +static const struct of_device_id l3cache_ids[] __initconst = { + {.compatible = "hisilicon,kunpeng-l3cache", .data = NULL}, + {} +}; + +static int __init l3cache_init(void) +{ + u32 reg; + struct device_node *node; + + node = of_find_matching_node(NULL, l3cache_ids); + if (!node) + return -ENODEV; + + l3_ctrl_base = of_iomap(node, 0); + if (!l3_ctrl_base) { + pr_err("failed to map Kunpeng L3 cache controller registers\n"); + return -ENOMEM; + } + + reg = readl_relaxed(l3_ctrl_base + L3_CTRL); + if (!(reg & L3_CTRL_ENABLE)) { + /* + * Ensure that no L3 cache hardware maintenance operations are + * being performed before enabling the L3 cache. Wait for it to + * finish. + */ + do { + cpu_relax(); + reg = readl_relaxed(l3_ctrl_base + L3_MAINT_CTRL); + } while ((reg & L3_MAINT_STATUS_MASK) != L3_MAINT_STATUS_END); + + reg = readl_relaxed(l3_ctrl_base + L3_AUCTRL); + reg |= L3_AUCTRL_EVENT_EN | L3_AUCTRL_ECC_EN; + writel_relaxed(reg, l3_ctrl_base + L3_AUCTRL); + + writel_relaxed(L3_CTRL_ENABLE, l3_ctrl_base + L3_CTRL); + } + + outer_cache.inv_range = l3cache_inv_range; + outer_cache.clean_range = l3cache_clean_range; + outer_cache.flush_range = l3cache_flush_range; + outer_cache.flush_all = l3cache_flush_all; + outer_cache.disable = l3cache_disable; + + pr_info("Hisilicon Kunpeng L3 cache controller enabled\n"); + + return 0; +} +arch_initcall(l3cache_init);