From patchwork Thu Feb 4 16:58:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 376302 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp1456183jah; Thu, 4 Feb 2021 09:00:44 -0800 (PST) X-Google-Smtp-Source: ABdhPJy299VkoyMiOo/kODPCZG3ibdzPWEuT4KAItlZaeKuzgSqYHfIa75nnRfIWjjUbm9tyo3h2 X-Received: by 2002:aa7:c9c9:: with SMTP id i9mr8728741edt.160.1612458044670; Thu, 04 Feb 2021 09:00:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612458044; cv=none; d=google.com; s=arc-20160816; b=01qLjhv5Ip2CS6XdS7pl6ZYMI4F1c6uBhVhoFTd9rMdOm1KuRjiyRDjM8+h9ItfdGi P32FSziOkQayCA8TGqFYTAjfaYmlmv0B6yzAx9X1R0Mz+LXpQ9ryeVOvjnyc+7gzBDLC 27K9ZmLSr8a1tDo9+trEboflWP66ZmjwFrrijMjrP77j0Tt0Rtm4rCxT5NRQqYWEpPmj 8fi4hLf770z2i6pJ0o53XRZDT/6wRfzHB2m6Jjz8oR/0Em12lPDWHubQZKGkGLlnlQsj PRDM9KqUB/LlEFkyBVDGtwCvyhDNBIpQdY6tg6oSTlLQxug7pSswfhA6gpB13JebeqPp EHtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:to:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:from :dkim-signature; bh=jDlHvsdUIONRKVtU19867Fygzm30l1LXU0YAlNqxBW0=; b=pom84a3sEie1sslAMtV3FoN2ljuqROzkbNHeVknKR5sdNiQ/bNGeUJP7HVfvBckmyb qOCyuAMIb6cBaVtAXif0LfPLzBC/vNlIJhgI68qNP8/g/r8lsUBXEdZ3oyMz/7ittRYP ZrtavIFiwijWHHXjR4TKns1aHCowIJuUbfxVb70soqnrMDCjo78SmdbanEhpLnjk7qzX 5grFgGKH0moM6mF+icl/4EkX+1UI4OzSNQtfBqc1coT6t2IPLVQVulkzS6de60jaTSVL /ISz44zuSifONA+35ppTnCSjqO+xoWhB9ho5cSQrowUN8i05eahHcbrK5gPsvDujzzih aowg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@kernel.org header.s=k20201202 header.b=lRM6DmXx; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id s3si3511906ejd.643.2021.02.04.09.00.44; Thu, 04 Feb 2021 09:00:44 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=fail header.i=@kernel.org header.s=k20201202 header.b=lRM6DmXx; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238239AbhBDQ7Z (ORCPT + 16 others); Thu, 4 Feb 2021 11:59:25 -0500 Received: from mail.kernel.org ([198.145.29.99]:54012 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238267AbhBDQ7G (ORCPT ); Thu, 4 Feb 2021 11:59:06 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id A7B9764F3C; Thu, 4 Feb 2021 16:58:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612457905; bh=z0XutANkFnDl2HKzc+3dvSKKP7OeyOyODq+qSSIl9nY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lRM6DmXxCArxfNSfeePmfUSveiVunt5ceaWIqQVEyk4khDRmJlg0UBU/gMhSV1dtf GV+YTJj607iRUjAPIff/6p4EMcEJRLSSeSojRFO5fW9+3lEQ0h5hBawCGvVv/z4WFY 47MnXywTa52DkYN4DI7jZO01NcUUBEVScq/dDC4LmBjbmpixXV1etctEsrwqR3YJNP sEQ2aFLQXd6etCssTk+3LyVockRKAE30k1Xj/fQU7ElTL+JqPD0FgITz5a75Rsjmyd vtjhbIbsLOW0UxrcGk/w0Dh1eBEGqSdB/6VqQMhAVNy72ZmglElEyJJHDIMB4l6SFK PUHJdDQ2SypzA== From: Vinod Koul Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , Andy Gross , Rob Herring , Asutosh Das , Jack Pham , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/3] dt-bindings: phy: qcom, qmp: Add SM8350 UFS PHY bindings Date: Thu, 4 Feb 2021 22:28:03 +0530 Message-Id: <20210204165805.62235-2-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210204165805.62235-1-vkoul@kernel.org> References: <20210204165805.62235-1-vkoul@kernel.org> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the compatible strings for the UFS PHY found on SM8350 SoC. Reviewed-by: Bjorn Andersson Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 1 + 1 file changed, 1 insertion(+) -- 2.26.2 diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index 62c4f2ba5b9f..bf804c12fa5f 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -38,6 +38,7 @@ properties: - qcom,sm8250-qmp-modem-pcie-phy - qcom,sm8250-qmp-usb3-phy - qcom,sm8250-qmp-usb3-uni-phy + - qcom,sm8350-qmp-ufs-phy - qcom,sm8350-qmp-usb3-phy - qcom,sm8350-qmp-usb3-uni-phy - qcom,sdx55-qmp-usb3-uni-phy From patchwork Thu Feb 4 16:58:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 376329 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp1564688jah; Thu, 4 Feb 2021 11:27:37 -0800 (PST) X-Google-Smtp-Source: ABdhPJwqqT6wnmTKQl6s8MOofmJEu/Y9g3jPCrNKm3+urz+k6D80aX2Y6erFcYZQOTpK6uEvEvop X-Received: by 2002:a17:906:c00a:: with SMTP id e10mr597857ejz.501.1612466857722; Thu, 04 Feb 2021 11:27:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612466857; cv=none; d=google.com; s=arc-20160816; b=PPolCD9bx9Lgt/XqSLfOVSYEVJ3WFQviWI+pSTxiIllLuvKb9bDHBeUCeDuin4LZqP Ss0r9fLiJNkPdEdKFk/kQBR+IzrpqW7Z4hYhsVCvrsNVgNMARmvpU+KOYcZdy0j3+FNc Zkz8+ciradokAT1vDBoht7n+gXF2YmtF+jDcWmtZjIo4QpymYxK1yC3xuom+GcTSOXnu gjF0VrPcQYsRIoy3FmGV2HYCKUgRVzzxBYtPPE1FLQ2nGOcCI0aU7F1EaVI7n+fGeXud AnyBcxWoOe0Ujl/NNaI+SPS9WP5McsTn+ZFRraWcfhyYlTKjCN2j21JirJy+Ma/44klc 6EFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:to:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:from :dkim-signature; bh=TsS33TOx1nRD0iisLJ1fOxmERJgNH70wTFk4pn82Yeg=; b=f5YLoXJM82Wp0gvv76EbbD8owuxBHkkYs8c0J3tZ8V7vRWjAJ6I18h6WWVp3vLMwwJ pUq0YDdFelK3MiwNTyeXy6B8z1URdBBywiotpoI8sIIkPAOngD1O9fGAspZa9SpIobs5 TvS2v6v28rgDaQSGVNOG8shxhigqpjoOHD5Y06ndVLN+kcXmqKXdVJM+PLcwxyssyzdc bax+QqbrntgLfj7TeiUbTX2P0Vdr84urNcdtfu0UBBg2EvQ95XbGQ0j2YR+IxfWn5Roz U8TseDL5qOOViMgDIUX9rjKfYCjOIfSuT3BNTBVUZ3EwFDr8QQnHSjcgTFn+QyMCLIz6 mmpA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@kernel.org header.s=k20201202 header.b="Sr/7UWgO"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id k5si3672732ejj.483.2021.02.04.11.27.37; Thu, 04 Feb 2021 11:27:37 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=fail header.i=@kernel.org header.s=k20201202 header.b="Sr/7UWgO"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238271AbhBDT0k (ORCPT + 16 others); Thu, 4 Feb 2021 14:26:40 -0500 Received: from mail.kernel.org ([198.145.29.99]:54028 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238268AbhBDQ7K (ORCPT ); Thu, 4 Feb 2021 11:59:10 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 83EBF64F72; Thu, 4 Feb 2021 16:58:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612457909; bh=J778l9M1K8153trMZBWLrcMcnqBtk9mX7SssLwTjnZg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Sr/7UWgOOzsbZ+6eyN8VQRljp/yFgix0YHfd8FdGDBIWWQ6/rRpChV+Vr8c3DEoag EUNNpauXVD0laBCGDzODaLxwcKbCQ3RPA4P1+7FRvnvhyyciHarKnlDB+X66HIqBY6 GWcAhn1KkW7qaYeXqEgBAf5xezhIojXJgZmoJOggTWQ5EjB26PYNayxvOs8HMGjKV8 EhnQOUlRLyIscKKm30hZ1VCXn3unlz5HyBBD1krE6ck+Xhd5H0RTCy0rZyg0hs/8Uh GdlZGgp+RGoV0WN+QVL/UwBMVYa0f3duHSgeghTvUCxPqN5eI+czl6q+54oNkqFuJM Qqlg8GgIwA/0A== From: Vinod Koul Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , Andy Gross , Rob Herring , Asutosh Das , Jack Pham , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/3] phy: qcom-qmp: Add UFS V5 registers found in SM8350 Date: Thu, 4 Feb 2021 22:28:04 +0530 Message-Id: <20210204165805.62235-3-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210204165805.62235-1-vkoul@kernel.org> References: <20210204165805.62235-1-vkoul@kernel.org> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the registers for UFS found in SM8350. The UFS phy used in SM8350 seems to have same offsets as V5 phy, although Documentation for that is lacking. Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp.h | 47 +++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) -- 2.26.2 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index dff7be5a1cc1..71ce3aa174ae 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -824,6 +824,32 @@ #define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc #define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 +/* Only for QMP V5 PHY - QSERDES COM registers */ +#define QSERDES_V5_COM_PLL_IVCO 0x058 +#define QSERDES_V5_COM_CP_CTRL_MODE0 0x074 +#define QSERDES_V5_COM_CP_CTRL_MODE1 0x078 +#define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c +#define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080 +#define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084 +#define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088 +#define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094 +#define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4 +#define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac +#define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0 +#define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4 +#define QSERDES_V5_COM_DEC_START_MODE0 0x0bc +#define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8 +#define QSERDES_V5_COM_DEC_START_MODE1 0x0c4 +#define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c +#define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124 +#define QSERDES_V5_COM_HSCLK_SEL 0x158 +#define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c +#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac +#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 +#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 +#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc +#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 + /* Only for QMP V5 PHY - TX registers */ #define QSERDES_V5_TX_RES_CODE_LANE_TX 0x34 #define QSERDES_V5_TX_RES_CODE_LANE_RX 0x38 @@ -837,6 +863,10 @@ #define QSERDES_V5_TX_RCV_DETECT_LVL_2 0xa4 #define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0xc0 #define QSERDES_V5_TX_PI_QEC_CTRL 0xe4 +#define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178 +#define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c +#define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180 +#define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184 /* Only for QMP V5 PHY - RX registers */ #define QSERDES_V5_RX_UCDR_FO_GAIN 0x008 @@ -893,6 +923,23 @@ #define QSERDES_V5_RX_DCC_CTRL1 0x1a8 #define QSERDES_V5_RX_VTH_CODE 0x1b0 +/* Only for QMP V5 PHY - UFS PCS registers */ +#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c +#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 +#define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c +#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 +#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 +#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 +#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 +#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 +#define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 +#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154 +#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158 +#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160 +#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168 +#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 +#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 + /* Only for QMP V5 PHY - USB3 have different offsets than V4 */ #define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x300 #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304 From patchwork Thu Feb 4 16:58:05 2021 Content-Type: text/plain; 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Thu, 4 Feb 2021 11:59:14 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 5781A64F6A; Thu, 4 Feb 2021 16:58:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612457913; bh=3cR4ub0anzzqMSTyHOhBLKh7dM9treWJAF/IvIyFH+A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VN9RTB1BG8Ig+e0Zj1DO2T3L0hpHHK1B7cvvBcuKKa8C/5aU05gxLBv752brgFuDg Ax1JDJ2G01c4YT9OTeUbsJsn3kvjrrZ/O91eMeRbplhZtCS++VVFrtofaX4fBOePH5 lHZp9+55Z02UsUO/rWdTjXG1N3JT2FSy7ceOLDKCDJ7HgZPGMNu6XI+dcMBAhVO04G IIwzcamxUTZ3mh90lrlKM0cH3/PWBUUuruUDjUV/tGOWOXTv0glOUptv6LPbwsFyLV z1KEtw/cnjvuEF7uYq+H5Ra2tzA71egcFx7HpMMb3Ecryc5dK3iyDn6GrDJriJ8oAU PFK/CZHQ3kVSA== From: Vinod Koul Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , Andy Gross , Rob Herring , Asutosh Das , Jack Pham , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/3] phy: qcom-qmp: Add support for SM8350 UFS phy Date: Thu, 4 Feb 2021 22:28:05 +0530 Message-Id: <20210204165805.62235-4-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210204165805.62235-1-vkoul@kernel.org> References: <20210204165805.62235-1-vkoul@kernel.org> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the tables for init sequences for UFS QMP phy found in SM8350 SoC. Reviewed-by: Bjorn Andersson Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp.c | 127 ++++++++++++++++++++++++++++ 1 file changed, 127 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index dbc12a19b702..4c6e0e86632b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -1983,6 +1983,106 @@ static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), }; +static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), + + /* Rate B */ + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), +}; + +static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c), +}; + +static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), +}; + +static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), +}; + static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), @@ -2971,6 +3071,30 @@ static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, }; +static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { + .type = PHY_TYPE_UFS, + .nlanes = 2, + + .serdes_tbl = sm8350_ufsphy_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), + .tx_tbl = sm8350_ufsphy_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl), + .rx_tbl = sm8350_ufsphy_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl), + .pcs_tbl = sm8350_ufsphy_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), + .clk_list = sdm845_ufs_phy_clk_l, + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sm8150_ufsphy_regs_layout, + + .start_ctrl = SERDES_START, + .pwrdn_ctrl = SW_PWRDN, + + .is_dual_lane_phy = true, +}; + static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { .type = PHY_TYPE_USB3, .nlanes = 1, @@ -4379,6 +4503,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { }, { .compatible = "qcom,sm8250-qmp-modem-pcie-phy", .data = &sm8250_qmp_gen3x2_pciephy_cfg, + }, { + .compatible = "qcom,sm8350-qmp-ufs-phy", + .data = &sm8350_ufsphy_cfg, }, { .compatible = "qcom,sm8350-qmp-usb3-phy", .data = &sm8350_usb3phy_cfg,