diff mbox

[ARM] Improve use of conditional execution in thumb mode.

Message ID 4F3AA18A.10701@codesourcery.com
State New
Headers show

Commit Message

Andrew Stubbs Feb. 14, 2012, 6:01 p.m. UTC 
And again with the attachment.

On Tue 14 Feb 2012 18:00:57 GMT, Andrew Stubbs wrote:
> On Tue 14 Feb 2012 17:35:36 GMT, Richard Earnshaw wrote:
>>> Bernds checked in a patch last year (or maybe even before that) to make
>>> the selection of flags clobbered insns run very late (certainly after
>>> condexec had run), so I'm not sure why you're not seeing this.
>>
>> Hm, you mentioned some peepholes. Try removing them....
>
> Hmmm, it seems you're right. The machine reorg pass now takes care of
> this. Well ... that was easy!
>
> Here's a patch to remove the obsolete peepholes. I've confirmed it
> works with the testcase.
>
> OK?
>
> Andrew

Comments

Richard Earnshaw Feb. 14, 2012, 6:30 p.m. UTC | #1 
On 14/02/12 18:01, Andrew Stubbs wrote:
> And again with the attachment.
> 
> On Tue 14 Feb 2012 18:00:57 GMT, Andrew Stubbs wrote:
>> On Tue 14 Feb 2012 17:35:36 GMT, Richard Earnshaw wrote:
>>>> Bernds checked in a patch last year (or maybe even before that) to make
>>>> the selection of flags clobbered insns run very late (certainly after
>>>> condexec had run), so I'm not sure why you're not seeing this.
>>>
>>> Hm, you mentioned some peepholes. Try removing them....
>>
>> Hmmm, it seems you're right. The machine reorg pass now takes care of
>> this. Well ... that was easy!
>>
>> Here's a patch to remove the obsolete peepholes. I've confirmed it
>> works with the testcase.
>>
>> OK?
>>
>> Andrew
>>
>> thumb-ifcvt2.patch
>>
>>
>> 2012-02-14  Andrew Stubbs  <ams@codesourcery.com>
>>
>> 	gcc/
>> 	* config/arm/thumb2.md: Delete obsolete peepholes.
>>
>> 	gcc/testsuite/
>> 	* gcc.target/arm/thumb-ifcvt.c: New test case.
>>

s/obsolete peepholes/obsolete flag-clobbering peepholes/

Otherwise ok for stage1

The 'Similarly' that you delete suggests there might still be more of
them...

R.
Andrew Stubbs Feb. 15, 2012, 11:10 a.m. UTC | #2 
On 14/02/12 18:30, Richard Earnshaw wrote:
> s/obsolete peepholes/obsolete flag-clobbering peepholes/
>
> Otherwise ok for stage1

Thanks.

> The 'Similarly' that you delete suggests there might still be more of
> them...

You'd think, but I can't figure out what that refers to.

There are some other peepholes that might be obsolete - I've not 
checked; I only deleted the ones I recognised.

Andrew
diff mbox

Patch

2012-02-14  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config/arm/thumb2.md: Delete obsolete peepholes.

	gcc/testsuite/
	* gcc.target/arm/thumb-ifcvt.c: New test case.

---
 gcc/config/arm/thumb2.md                   |  107 ----------------------------
 gcc/testsuite/gcc.target/arm/thumb-ifcvt.c |   19 +++++
 2 files changed, 19 insertions(+), 107 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/arm/thumb-ifcvt.c

diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md
index 05585da..799a3df 100644
--- a/gcc/config/arm/thumb2.md
+++ b/gcc/config/arm/thumb2.md
@@ -677,26 +677,6 @@ 
    (set_attr "length" "2")]
 )
 
-;; Similarly for 16-bit shift instructions
-;; There is no 16-bit rotate by immediate instruction.
-(define_peephole2
-  [(set (match_operand:SI   0 "low_register_operand" "")
-	(match_operator:SI  3 "shift_operator"
-	 [(match_operand:SI 1 "low_register_operand" "")
-	  (match_operand:SI 2 "low_reg_or_int_operand" "")]))]
-  "TARGET_THUMB2
-   && peep2_regno_dead_p(0, CC_REGNUM)
-   && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
-       || REG_P(operands[2]))"
-  [(parallel
-    [(set (match_dup 0)
-	  (match_op_dup 3
-	   [(match_dup 1)
-	    (match_dup 2)]))
-     (clobber (reg:CC CC_REGNUM))])]
-  ""
-)
-
 (define_insn "*thumb2_shiftsi3_short"
   [(set (match_operand:SI   0 "low_register_operand" "=l")
 	(match_operator:SI  3 "shift_operator"
@@ -715,20 +695,6 @@ 
 		      (const_string "alu_shift_reg")))]
 )
 
-;; 16-bit load immediate
-(define_peephole2
-  [(set (match_operand:QHSI 0 "low_register_operand" "")
-	(match_operand:QHSI 1 "const_int_operand" ""))]
-  "TARGET_THUMB2
-   && peep2_regno_dead_p(0, CC_REGNUM)
-   && (unsigned HOST_WIDE_INT) INTVAL(operands[1]) < 256"
-  [(parallel
-    [(set (match_dup 0)
-	  (match_dup 1))
-     (clobber (reg:CC CC_REGNUM))])]
-  ""
-)
-
 (define_insn "*thumb2_mov<mode>_shortim"
   [(set (match_operand:QHSI 0 "low_register_operand" "=l")
 	(match_operand:QHSI 1 "const_int_operand" "I"))
@@ -739,24 +705,6 @@ 
    (set_attr "length" "2")]
 )
 
-;; 16-bit add/sub immediate
-(define_peephole2
-  [(set (match_operand:SI 0 "low_register_operand" "")
-	(plus:SI (match_operand:SI 1 "low_register_operand" "")
-		 (match_operand:SI 2 "const_int_operand" "")))]
-  "TARGET_THUMB2
-   && peep2_regno_dead_p(0, CC_REGNUM)
-   && ((rtx_equal_p(operands[0], operands[1])
-	&& INTVAL(operands[2]) > -256 && INTVAL(operands[2]) < 256)
-       || (INTVAL(operands[2]) > -8 && INTVAL(operands[2]) < 8))"
-  [(parallel
-    [(set (match_dup 0)
-	  (plus:SI (match_dup 1)
-		   (match_dup 2)))
-     (clobber (reg:CC CC_REGNUM))])]
-  ""
-)
-
 (define_insn "*thumb2_addsi_short"
   [(set (match_operand:SI 0 "low_register_operand" "=l,l")
 	(plus:SI (match_operand:SI 1 "low_register_operand" "l,0")
@@ -868,35 +816,6 @@ 
    (set_attr "length" "2,4")]
 )
 
-;; 16-bit encodings of "muls" and "mul<c>".  We only use these when
-;; optimizing for size since "muls" is slow on all known
-;; implementations and since "mul<c>" will be generated by
-;; "*arm_mulsi3_v6" anyhow.  The assembler will use a 16-bit encoding
-;; for "mul<c>" whenever possible anyhow.
-(define_peephole2
-  [(set (match_operand:SI 0 "low_register_operand" "")
-        (mult:SI (match_operand:SI 1 "low_register_operand" "")
-                 (match_dup 0)))]
-  "TARGET_THUMB2 && optimize_size && peep2_regno_dead_p (0, CC_REGNUM)"
-  [(parallel
-    [(set (match_dup 0)
-           (mult:SI (match_dup 0) (match_dup 1)))
-     (clobber (reg:CC CC_REGNUM))])]
-  ""
-)
-
-(define_peephole2
-  [(set (match_operand:SI 0 "low_register_operand" "")
-        (mult:SI (match_dup 0)
-	         (match_operand:SI 1 "low_register_operand" "")))]
-  "TARGET_THUMB2 && optimize_size && peep2_regno_dead_p (0, CC_REGNUM)"
-  [(parallel
-    [(set (match_dup 0)
-           (mult:SI (match_dup 0) (match_dup 1)))
-     (clobber (reg:CC CC_REGNUM))])]
-  ""
-)
-
 (define_insn "*thumb2_mulsi_short"
   [(set (match_operand:SI 0 "low_register_operand" "=l")
         (mult:SI (match_operand:SI 1 "low_register_operand" "%0")
@@ -979,19 +898,6 @@ 
 	    (const_int 8)))]
 )
 
-;; 16-bit complement
-(define_peephole2
-  [(set (match_operand:SI 0 "low_register_operand" "")
-	(not:SI (match_operand:SI 1 "low_register_operand" "")))]
-  "TARGET_THUMB2
-   && peep2_regno_dead_p(0, CC_REGNUM)"
-  [(parallel
-    [(set (match_dup 0)
-	  (not:SI (match_dup 1)))
-     (clobber (reg:CC CC_REGNUM))])]
-  ""
-)
-
 (define_insn "*thumb2_one_cmplsi2_short"
   [(set (match_operand:SI 0 "low_register_operand" "=l")
 	(not:SI (match_operand:SI 1 "low_register_operand" "l")))
@@ -1002,19 +908,6 @@ 
    (set_attr "length" "2")]
 )
 
-;; 16-bit negate
-(define_peephole2
-  [(set (match_operand:SI 0 "low_register_operand" "")
-	(neg:SI (match_operand:SI 1 "low_register_operand" "")))]
-  "TARGET_THUMB2
-   && peep2_regno_dead_p(0, CC_REGNUM)"
-  [(parallel
-    [(set (match_dup 0)
-	  (neg:SI (match_dup 1)))
-     (clobber (reg:CC CC_REGNUM))])]
-  ""
-)
-
 (define_insn "*thumb2_negsi2_short"
   [(set (match_operand:SI 0 "low_register_operand" "=l")
 	(neg:SI (match_operand:SI 1 "low_register_operand" "l")))
diff --git a/gcc/testsuite/gcc.target/arm/thumb-ifcvt.c b/gcc/testsuite/gcc.target/arm/thumb-ifcvt.c
new file mode 100644
index 0000000..b03bbce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/thumb-ifcvt.c
@@ -0,0 +1,19 @@ 
+/* Check that Thumb 16-bit shifts can be if-converted.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-options "-O2" } */
+
+int
+foo (int a, int b)
+{
+  if (a != b)
+    {
+      a = a << b;
+      a = a >> 1;
+    }
+
+  return a + b;
+}
+
+/* { dg-final { scan-assembler "lslne" } } */
+/* { dg-final { scan-assembler "asrne" } } */