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[5/6] mmc: hi6220_dw_mmc: Add hi6220 glue code for dw_mmc controller.

Message ID 1431437912-18988-6-git-send-email-peter.griffin@linaro.org
State New
Headers show

Commit Message

Peter Griffin May 12, 2015, 1:38 p.m. UTC 
This patch adds the glue code for hi6220 SoC which has 2x synopsis
dw_mmc controllers. This will be used by the hikey board support
in subsequent patches.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 arch/arm/include/asm/arch-armv8/dwmmc.h |  8 +++++
 drivers/mmc/Makefile                    |  1 +
 drivers/mmc/hi6220_dw_mmc.c             | 63 +++++++++++++++++++++++++++++++++
 3 files changed, 72 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-armv8/dwmmc.h
 create mode 100644 drivers/mmc/hi6220_dw_mmc.c

Comments

Peter Griffin May 13, 2015, 12:10 p.m. UTC | #1 
Hi Marek,

On Tue, 12 May 2015, Marek Vasut wrote:

> On Tuesday, May 12, 2015 at 03:38:31 PM, Peter Griffin wrote:
> > This patch adds the glue code for hi6220 SoC which has 2x synopsis
> > dw_mmc controllers. This will be used by the hikey board support
> > in subsequent patches.
> > 
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> 
> [...]
> 
> > diff --git a/drivers/mmc/hi6220_dw_mmc.c b/drivers/mmc/hi6220_dw_mmc.c
> > new file mode 100644
> > index 0000000..a3880a3
> > --- /dev/null
> > +++ b/drivers/mmc/hi6220_dw_mmc.c
> > @@ -0,0 +1,63 @@
> > +/*
> > + * (C) Copyright 2015 Linaro
> > + * peter.griffin <peter.griffin@linaro.org>
> > + *
> > + * SPDX-License-Identifier:	GPL-2.0+
> > + */
> > +
> > +#include <common.h>
> > +#include <dwmmc.h>
> > +#include <malloc.h>
> > +#include <asm-generic/errno.h>
> > +
> > +#define	DWMMC_MAX_CH_NUM		4
> > +
> > +/*
> > +#define	DWMMC_MAX_FREQ			52000000
> > +#define	DWMMC_MIN_FREQ			400000
> > +*/
> 
> Please zap these dead macros.

Ok will fix in v2.
> 
> > +/*TODO we should probably use the frequencies above, but ATF uses
> > +  the ones below so stick with that for the moment */
> > +#define	DWMMC_MAX_FREQ			50000000
> > +#define	DWMMC_MIN_FREQ			378000
> > +
> > +/* Source clock is configured to 100Mhz by ATF bl1*/
> > +#define MMC0_DEFAULT_FREQ		100000000
> 
> [...]
> 
> > +int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width)
> > +{
> > +	struct dwmci_host *host = NULL;
> > +
> > +	host = malloc(sizeof(struct dwmci_host));
> 
> calloc(1, sizeof(...)) so the data are inited/zero'd out please.
> [...]

Ok will fix in v2

regards,

Peter.
diff mbox

Patch

diff --git a/arch/arm/include/asm/arch-armv8/dwmmc.h b/arch/arm/include/asm/arch-armv8/dwmmc.h
new file mode 100644
index 0000000..c747383
--- /dev/null
+++ b/arch/arm/include/asm/arch-armv8/dwmmc.h
@@ -0,0 +1,8 @@ 
+/*
+ * (C) Copyright 2015 Linaro
+ * Peter Griffin <peter.griffin@linaro.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width);
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index ed73687..81a1a8f 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -11,6 +11,7 @@  obj-$(CONFIG_BFIN_SDH) += bfin_sdh.o
 obj-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
 obj-$(CONFIG_DWMMC) += dw_mmc.o
 obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
+obj-$(CONFIG_HIKEY_DWMMC) += hi6220_dw_mmc.o
 obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
 obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o
 obj-$(CONFIG_FTSDC021) += ftsdc021_sdhci.o
diff --git a/drivers/mmc/hi6220_dw_mmc.c b/drivers/mmc/hi6220_dw_mmc.c
new file mode 100644
index 0000000..a3880a3
--- /dev/null
+++ b/drivers/mmc/hi6220_dw_mmc.c
@@ -0,0 +1,63 @@ 
+/*
+ * (C) Copyright 2015 Linaro
+ * peter.griffin <peter.griffin@linaro.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dwmmc.h>
+#include <malloc.h>
+#include <asm-generic/errno.h>
+
+#define	DWMMC_MAX_CH_NUM		4
+
+/*
+#define	DWMMC_MAX_FREQ			52000000
+#define	DWMMC_MIN_FREQ			400000
+*/
+
+/*TODO we should probably use the frequencies above, but ATF uses
+  the ones below so stick with that for the moment */
+#define	DWMMC_MAX_FREQ			50000000
+#define	DWMMC_MIN_FREQ			378000
+
+/* Source clock is configured to 100Mhz by ATF bl1*/
+#define MMC0_DEFAULT_FREQ		100000000
+
+static int hi6220_dwmci_core_init(struct dwmci_host *host, int index)
+{
+	host->name = "HiKey DWMMC";
+
+	host->dev_index = index;
+
+	/* Add the mmc channel to be registered with mmc core */
+	if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
+		printf("DWMMC%d registration failed\n", index);
+		return -1;
+	}
+	return 0;
+}
+
+/*
+ * This function adds the mmc channel to be registered with mmc core.
+ * index -	mmc channel number.
+ * regbase -	register base address of mmc channel specified in 'index'.
+ * bus_width -	operating bus width of mmc channel specified in 'index'.
+ */
+int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width)
+{
+	struct dwmci_host *host = NULL;
+
+	host = malloc(sizeof(struct dwmci_host));
+	if (!host) {
+		error("dwmci_host malloc fail!\n");
+		return -ENOMEM;
+	}
+
+	host->ioaddr = (void *)regbase;
+	host->buswidth = bus_width;
+	host->bus_hz = MMC0_DEFAULT_FREQ;
+
+	return hi6220_dwmci_core_init(host, index);
+}