| Message ID | 1477538129-118465-2-git-send-email-heyi.guo@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
On Thu, Oct 27, 2016 at 11:15:06AM +0800, Heyi Guo wrote: > Add Spd mirror mode related registers definitioni Truncated commit message? > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Heyi Guo <heyi.guo@linaro.org> > --- > Chips/Hisilicon/Include/Library/HwMemInitLib.h | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h > index 955b9e4..305040a 100644 > --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h > +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h > @@ -161,6 +161,7 @@ typedef struct _DDR_DIMM{ > UINT16 DimmSize; > UINT16 DimmSpeed; > UINT32 RankSize; > + UINT8 SpdMirror; //Denote the dram address mapping is standard mode or mirrored mode > struct DDR_RANK Rank[MAX_RANK_DIMM]; > }DDR_DIMM; > > @@ -336,7 +337,7 @@ typedef struct _NVRAM{ > typedef struct _MEMORY{ > UINT8 Config0; > UINT8 marginTest; > - UINT8 Config1[5]; > + UINT8 Config1[6]; This does not obviously belong with the described changeset. If it does, please explain why in commit message. > UINT32 Config2; > }MEMORY; > > @@ -789,6 +790,8 @@ struct ODT_ACTIVE_STRUCT { > #define SPD_FTB_TAA_DDR4 123 // Fine offset for TAA > #define SPD_FTB_MAX_TCK_DDR4 124 // Fine offset for max TCK > #define SPD_FTB_MIN_TCK_DDR4 125 // Fine offset for min TCK > +#define SPD_MIRROR_UNBUFFERED 131 // Unbuffered:Address Mapping from Edge Connector to DRAM > +#define SPD_MIRROR_REGISTERED 136 // Registered:Address Address Mapping from Register to DRAM > > #define SPD_MMID_LSB_DDR4 320 // Module Manufacturer ID Code, Least Significant Byte > #define SPD_MMID_MSB_DDR4 321 // Module Manufacturer ID Code, Most Significant Byte > -- > 1.9.1 >
diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h index 955b9e4..305040a 100644 --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h @@ -161,6 +161,7 @@ typedef struct _DDR_DIMM{ UINT16 DimmSize; UINT16 DimmSpeed; UINT32 RankSize; + UINT8 SpdMirror; //Denote the dram address mapping is standard mode or mirrored mode struct DDR_RANK Rank[MAX_RANK_DIMM]; }DDR_DIMM; @@ -336,7 +337,7 @@ typedef struct _NVRAM{ typedef struct _MEMORY{ UINT8 Config0; UINT8 marginTest; - UINT8 Config1[5]; + UINT8 Config1[6]; UINT32 Config2; }MEMORY; @@ -789,6 +790,8 @@ struct ODT_ACTIVE_STRUCT { #define SPD_FTB_TAA_DDR4 123 // Fine offset for TAA #define SPD_FTB_MAX_TCK_DDR4 124 // Fine offset for max TCK #define SPD_FTB_MIN_TCK_DDR4 125 // Fine offset for min TCK +#define SPD_MIRROR_UNBUFFERED 131 // Unbuffered:Address Mapping from Edge Connector to DRAM +#define SPD_MIRROR_REGISTERED 136 // Registered:Address Address Mapping from Register to DRAM #define SPD_MMID_LSB_DDR4 320 // Module Manufacturer ID Code, Least Significant Byte #define SPD_MMID_MSB_DDR4 321 // Module Manufacturer ID Code, Most Significant Byte
Add Spd mirror mode related registers definitioni Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> --- Chips/Hisilicon/Include/Library/HwMemInitLib.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)