diff mbox

[ARM] Fix decoding mask of the VCMLA instruction

Message ID 5878C7C1.6090607@arm.com
State New
Headers show

Commit Message

Szabolcs Nagy Jan. 13, 2017, 12:27 p.m. UTC 
Bit 24 of the indexed element vcmla decode mask was incorrectly
left unset.  This could cause incorrect disassembly of some
currently undefined instructions as vcmla.

opcodes/
2017-01-13  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* arm-dis.c (coprocessor_opcodes): Fix vcmla mask.

Comments

Nick Clifton Jan. 16, 2017, 10:56 a.m. UTC | #1 
Hi Szabolcs,

> opcodes/

> 2017-01-13  Szabolcs Nagy  <szabolcs.nagy@arm.com>

> 

> 	* arm-dis.c (coprocessor_opcodes): Fix vcmla mask.


Approved - please apply.

Cheers
  Nick
Jan Beulich Jan. 16, 2017, 11:11 a.m. UTC | #2 
>>> On 16.01.17 at 11:56, <nickc@redhat.com> wrote:

>> opcodes/

>> 2017-01-13  Szabolcs Nagy  <szabolcs.nagy@arm.com>

>> 

>> 	* arm-dis.c (coprocessor_opcodes): Fix vcmla mask.

> 

> Approved - please apply.


I'm sorry for having noticed only over the weekend, but I think
there's a second issue here: Aiui the instruction takes a 1-bit
immediate (selecting between 90° and 270°), yet doesn't
decode bit 20 (which would be required to always be 1 for only
those two value to be selectable). It is of no help that the test
case only ever tests #90 as the immediate operand.

Jan
Nick Clifton Jan. 18, 2017, 5:03 p.m. UTC | #3 
Hi Szabolcs,

> opcodes/

> 2017-01-17  Szabolcs Nagy  <szabolcs.nagy@arm.com>

> 

> 	* arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.

> 

> gas/

> 2017-01-17  Szabolcs Nagy  <szabolcs.nagy@arm.com>

> 

> 	* testsuite/gas/arm/armv8_3-a-simd.s: Add vcmla tests.

> 	* testsuite/gas/arm/armv8_3-a-simd.d: Update.


OK - revised patch approved - please apply.

Cheers
  Nick
diff mbox

Patch

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 167c668..11ee9c5 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -897,13 +897,13 @@  static const struct opcode32 coprocessor_opcodes[] =
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
     0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
-    0xfe000800, 0xfea00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
+    0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
-    0xfe200800, 0xfea00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%23?780"},
+    0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%23?780"},
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
-    0xfe800800, 0xfea00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
+    0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
-    0xfea00800, 0xfea00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%23?780"},
+    0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%23?780"},
 
   /* V5 coprocessor instructions.  */
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),