| Message ID | 1489762943-25849-2-git-send-email-leo.yan@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | coresight: enable debug module | expand |
Hi Mathieu, On Fri, Mar 17, 2017 at 10:13:35AM -0600, Mathieu Poirier wrote: [...] > > +- compatible : should be > > + * "arm,coresight-cpu-debug"; supplemented with "arm,primecell" > > + since this driver is using the AMBA bus interface. > > This description needs to be refactored - see my comment from an earlier post > for more details. I have refined this description according to your suggestion: http://archive.armlinux.org.uk/lurker/message/20170301.154550.f55a09d5.en.html Am I missing anthing for this? > > +- reg : physical base address and length of the register set. > > + > > +- clocks : the clock associated to this component. > > + > > +- clock-names : the name of the clock referenced by the code. Since we are > > + using the AMBA framework, the name of the clock providing > > + the interconnect should be "apb_pclk" and the clock is > > + mandatory. The interface between the debug logic and the > > + processor core is clocked by the internal CPU clock, so it > > + is enabled with CPU clock by default. > > + > > +- cpu : the cpu phandle the debug module is affined to. When omitted > > + the module is considered to belong to CPU0. > > + > > +Optional properties: > > s/properties/property > > > + > > +- power-domains: a phandle to power domain node for debug module. We can > > + use "nohlt" to ensure CPU power domain is enabled. > > The "power-domains" property is to take care of the debug power domain. The > "nohlt" is to make sure registers in the CPU power domain are accessible - both > are independent from one another. As such the description for this binding > shoudl be: > > "a phandle to the debug power domain". Will fix for upper two comments. Thanks, Leo Yan
diff --git a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt new file mode 100644 index 0000000..f6855c3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt @@ -0,0 +1,46 @@ +* CoreSight CPU Debug Component: + +CoreSight cpu debug component are compliant with the ARMv8 architecture +reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The +external debug module is mainly used for two modes: self-hosted debug and +external debug, and it can be accessed from mmio region from Coresight +and eventually the debug module connects with CPU for debugging. And the +debug module provides sample-based profiling extension, which can be used +to sample CPU program counter, secure state and exception level, etc; +usually every CPU has one dedicated debug module to be connected. + +Required properties: + +- compatible : should be + * "arm,coresight-cpu-debug"; supplemented with "arm,primecell" + since this driver is using the AMBA bus interface. + +- reg : physical base address and length of the register set. + +- clocks : the clock associated to this component. + +- clock-names : the name of the clock referenced by the code. Since we are + using the AMBA framework, the name of the clock providing + the interconnect should be "apb_pclk" and the clock is + mandatory. The interface between the debug logic and the + processor core is clocked by the internal CPU clock, so it + is enabled with CPU clock by default. + +- cpu : the cpu phandle the debug module is affined to. When omitted + the module is considered to belong to CPU0. + +Optional properties: + +- power-domains: a phandle to power domain node for debug module. We can + use "nohlt" to ensure CPU power domain is enabled. + + +Example: + + debug@f6590000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0 0xf6590000 0 0x1000>; + clocks = <&sys_ctrl HI6220_DAPB_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + };