| Message ID | 20180228181432.26847-1-manivannan.sadhasivam@linaro.org |
|---|---|
| Headers | show |
| Series | Add Actions Semi S900 pinctrl and gpio support | expand |
On Wed, Feb 28, 2018 at 8:14 PM, Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> wrote: > Add pinctrl driver for Actions Semi S900 SoC. The driver supports > pinctrl, pinmux and pinconf functionalities through a range of registers > common to both gpio driver and pinctrl driver. > > Pinmux functionality is available only for the pin groups while the > pinconf functionality is available for both pin groups and individual > pins. > +static int owl_set_mux(struct pinctrl_dev *pctrldev, > + unsigned int function, > + unsigned int group) > +{ > + mfpval = readl(pctrl->base + g->mfpctl_reg); > + mfpval &= ~mask; > + mfpval |= val; > + writel(mfpval, pctrl->base + g->mfpctl_reg); This is called owl_update_bits(). > +static int owl_pin_config_set(struct pinctrl_dev *pctrldev, > + unsigned int pin, > + unsigned long *configs, > + unsigned int num_configs) > +{ > + int ret = 0; Redundant assignment? > + mask = (1 << width) - 1; > + mask = mask << bit; > + tmp = readl(pctrl->base + reg); > + tmp &= ~mask; > + tmp |= arg << bit; > + writel(tmp, pctrl->base + reg); This is called owl_update_bits(). > +} > +static int owl_group_pinconf_val2arg(const struct owl_pingroup *g, > + unsigned int param, > + u32 *arg) > +{ > + case PIN_CONFIG_SLEW_RATE: > + if (*arg) > + *arg = 1; > + else > + *arg = 0; Doesn't slew rate allow a non-binary value? > + return 0; > +} > + > +static int owl_group_config_get(struct pinctrl_dev *pctrldev, > + unsigned int group, > + unsigned long *config) > +{ > + int ret = 0; Redundant assignment. > +} > +static int owl_group_config_set(struct pinctrl_dev *pctrldev, > + unsigned int group, > + unsigned long *configs, > + unsigned int num_configs) > +{ > + int ret = 0; Redundant assignment, see below. > + mask = (1 << width) - 1; > + mask = mask << bit; > + tmp = readl(pctrl->base + reg); > + tmp &= ~mask; > + tmp |= arg << bit; > + writel(tmp, pctrl->base + reg); This is called owl_update_bits(). > + return ret; return 0; ? > +} > +int owl_pinctrl_probe(struct platform_device *pdev, > + struct owl_pinctrl_soc_data *soc_data) > +{ > + clk_prepare_enable(pctrl->clk); This can fail. > +} > +static const struct of_device_id s900_pinctrl_of_match[] = { > + { .compatible = "actions,s900-pinctrl", }, > + { }, No comma needed. > +}; -- With Best Regards, Andy Shevchenko -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Linus, On Thu, Mar 01, 2018 at 10:20:29AM +0100, Linus Walleij wrote: > On Wed, Feb 28, 2018 at 7:14 PM, Manivannan Sadhasivam > <manivannan.sadhasivam@linaro.org> wrote: > > > Add pinctrl bindings for Actions Semi S900 SoC > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > The previous (v2) version had Rob's Review tag, did you just forget > to add it or has something changed? > My bad. Slipped through the cracks. > If nothing is changed I can add his tag when applying. > I will send out a new version of the whole series, incorporating Andy's pinctrl driver review. Also, FYI this pacthseries depends on Clock driver patchset I have submitted earlier. So far no reply from Stephen yet. He said that he is working on setting up his new environment and will begin reviewing shortly. Thanks, Mani > Yours, > Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html