| Message ID | 20180528174752.6806-1-linus.walleij@linaro.org |
|---|---|
| Headers | show |
| Series | Realtek SMI RTL836x DSA driver | expand |
On Mon, May 28, 2018 at 07:47:48PM +0200, Linus Walleij wrote: > This is a second RFC version of the DSA driver for Realtek > RTL8366x especially RTL8366RB. > > I've been beating my head against this one and I'm not really > clear on why my ethernet frames are not coming through to the > CPU port on the chip. > > It appears when using ethtool -S on the ports that packets > are passing fine into the router fabric and through to the > CPU port but the ethernet driver where the fixed link is > connected refuse to accept the packages. Hi Linus Have you played with RGMII delays? Andrew
On Mon, May 28, 2018 at 8:20 PM, Andrew Lunn <andrew@lunn.ch> wrote: > On Mon, May 28, 2018 at 07:47:48PM +0200, Linus Walleij wrote: >> This is a second RFC version of the DSA driver for Realtek >> RTL8366x especially RTL8366RB. >> >> I've been beating my head against this one and I'm not really >> clear on why my ethernet frames are not coming through to the >> CPU port on the chip. >> >> It appears when using ethtool -S on the ports that packets >> are passing fine into the router fabric and through to the >> CPU port but the ethernet driver where the fixed link is >> connected refuse to accept the packages. > > Hi Linus > > Have you played with RGMII delays? No not like I changed them or anything... the SoC has some set-up for skew and delay on the nanosecond level, but I used the vendor defaults, verified to be the same in their custom kernel tree. It's this stuff from the DTS: + conf0 { + pins = "V8 GMAC0 RXDV", "T10 GMAC1 RXDV"; + skew-delay = <0>; + }; + conf1 { + pins = "Y7 GMAC0 RXC", "Y11 GMAC1 RXC"; + skew-delay = <15>; + }; + conf2 { + pins = "T8 GMAC0 TXEN", "W11 GMAC1 TXEN"; + skew-delay = <7>; + }; + conf3 { + pins = "U8 GMAC0 TXC"; + skew-delay = <11>; + }; + conf4 { + pins = "V11 GMAC1 TXC"; + skew-delay = <10>; + }; Yours, Linus Walleij
On Tue, May 29, 2018 at 10:49:46AM +0200, Linus Walleij wrote: > On Mon, May 28, 2018 at 8:20 PM, Andrew Lunn <andrew@lunn.ch> wrote: > > On Mon, May 28, 2018 at 07:47:48PM +0200, Linus Walleij wrote: > >> This is a second RFC version of the DSA driver for Realtek > >> RTL8366x especially RTL8366RB. > >> > >> I've been beating my head against this one and I'm not really > >> clear on why my ethernet frames are not coming through to the > >> CPU port on the chip. > >> > >> It appears when using ethtool -S on the ports that packets > >> are passing fine into the router fabric and through to the > >> CPU port but the ethernet driver where the fixed link is > >> connected refuse to accept the packages. > > > > Hi Linus > > > > Have you played with RGMII delays? > > No not like I changed them or anything... the SoC has some > set-up for skew and delay on the nanosecond level, but I used the > vendor defaults, verified to be the same in their custom > kernel tree. Hi Linus Did you look at the switch end? I found a datasheet for the 8366/8369. Register at 0x0050, P8GCR. It has two bits for RGMII delays. With RGMII delays, you have 3 'choices'. 1) The hardware design includes the delay, by zig-zagging the clock line to make it longer. 2) The 'MAC' side does the delay. 3) The 'PHY' side does the delay. I normally recommend the PHY side doing it, because that's what most board do. Gives us some consistency. But it does not really matter. Just make sure one side, and only once side is inserting the delays. Andrew
On Tue, May 29, 2018 at 2:24 PM, Andrew Lunn <andrew@lunn.ch> wrote: > Did you look at the switch end? I found a datasheet for the > 8366/8369. Register at 0x0050, P8GCR. It has two bits for RGMII > delays. Unfortunately this datasheet is not applicable to RTL8366RB. RTL documentation and model numbers are a complete mess around the time when this chip came out, unfortunately... I even started to implement using that datasheet and had to toss a bunch of stuff away. There might not even be a proper datasheet for RTL8366RB, I'm afraid. The best we have is different (3 different AFAICT) vendor code drops. Here is one drop over at DD-WRT: https://svn.dd-wrt.com//browser/src/linux/universal/linux-3.2/drivers/net/ethernet/raeth/rb As you can see, the RTL8366RB vendor driver consists of a hacked version of their RTL8368S driver, so apparently those two ASICs are similar, they even kept the same filenames. For example the register defintions: https://svn.dd-wrt.com/browser/src/linux/universal/linux-3.2/drivers/net/ethernet/raeth/rb/rtl8368s_reg.h > With RGMII delays, you have 3 'choices'. > > 1) The hardware design includes the delay, by zig-zagging the clock > line to make it longer. > 2) The 'MAC' side does the delay. > 3) The 'PHY' side does the delay. > > I normally recommend the PHY side doing it, because that's what most > board do. Gives us some consistency. But it does not really > matter. Just make sure one side, and only once side is inserting the > delays. Makes sense! But I haven't found anything applicable in the RTL8366RB registers. There are some jam tables with magic values written all over the place that have no documentation, I fear this is one of the settings poked around with there. However, even if this router did not come with any code for the RTL8366RB driver, I disassembled the binary to verify that they use the same magic jam table, so the ASIC is initialized in the same way. Yours, Linus Walleij
> On 29 May 2018, at 19:41, Linus Walleij <linus.walleij@linaro.org> wrote: > > On Tue, May 29, 2018 at 2:24 PM, Andrew Lunn <andrew@lunn.ch> wrote: > >> Did you look at the switch end? I found a datasheet for the >> 8366/8369. Register at 0x0050, P8GCR. It has two bits for RGMII >> delays. > > Unfortunately this datasheet is not applicable to RTL8366RB. > > RTL documentation and model numbers are a complete mess > around the time when this chip came out, unfortunately... I even > started to implement using that datasheet and had to toss a bunch > of stuff away. > > There might not even be a proper datasheet for RTL8366RB, > I'm afraid. The best we have is different (3 different AFAICT) > vendor code drops. Here is one drop over at DD-WRT: > https://svn.dd-wrt.com//browser/src/linux/universal/linux-3.2/drivers/net/ethernet/raeth/rb > > As you can see, the RTL8366RB vendor driver consists of > a hacked version of their RTL8368S driver, so apparently those > two ASICs are similar, they even kept the same filenames. > > For example the register defintions: > https://svn.dd-wrt.com/browser/src/linux/universal/linux-3.2/drivers/net/ethernet/raeth/rb/rtl8368s_reg.h > >> With RGMII delays, you have 3 'choices'. >> >> 1) The hardware design includes the delay, by zig-zagging the clock >> line to make it longer. >> 2) The 'MAC' side does the delay. >> 3) The 'PHY' side does the delay. >> >> I normally recommend the PHY side doing it, because that's what most >> board do. Gives us some consistency. But it does not really >> matter. Just make sure one side, and only once side is inserting the >> delays. > > Makes sense! But I haven't found anything applicable in the > RTL8366RB registers. > > There are some jam tables with magic values written all over > the place that have no documentation, I fear this is one of the > settings poked around with there. > > However, even if this router did not come with any code for > the RTL8366RB driver, I disassembled the binary to verify > that they use the same magic jam table, so the ASIC is > initialized in the same way. > > Yours, > Linus Walleij > > _______________________________________________ > openwrt-devel mailing list > openwrt-devel@lists.openwrt.org > https://lists.openwrt.org/listinfo/openwrt-devel Oh lordy, that horrible device as exhibited in the netgear DGN3500. Talk about magic values https://git.openwrt.org/?p=openwrt/openwrt.git;a=commit;h=42120bd7f323ff7170b32a5fd4674babd8b184bc Cheers, Kevin D-B 012C ACB2 28C6 C53E 9775 9123 B3A2 389B 9DE2 334A
On 05/28/2018 10:47 AM, Linus Walleij wrote: > The Realtek SMI family is a set of DSA chips that provide > switching in routers. This binding just follows the pattern > set by other switches but with the introduction of an embedded > irqchip to demux and handle the interrupts fired by the single > line from the chip. > > This interrupt construction is similar to how we handle > interrupt controllers inside PCI bridges etc. > > Cc: Antti Seppälä <a.seppala@gmail.com> > Cc: Roman Yeryomin <roman@advem.lv> > Cc: Colin Leitner <colin.leitner@googlemail.com> > Cc: Gabor Juhos <juhosg@openwrt.org> > Cc: Florian Fainelli <f.fainelli@gmail.com> > Cc: devicetree@vger.kernel.org > Signed-off-by: Linus Walleij <linus.walleij@linaro.org> > --- > + > + mdio { > + compatible = "realtek,smi-mdio", "dsa-mdio"; You should drop the "dsa-mdio" compatible string here since it both non documented and not matched either. Other than that, this looks great, with that fixed: Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> -- Florian
On Tue, May 29, 2018 at 8:57 PM, Kevin Darbyshire-Bryant <kevin@darbyshire-bryant.me.uk> wrote: > Oh lordy, that horrible device as exhibited in the netgear DGN3500. Talk about magic values > https://git.openwrt.org/?p=openwrt/openwrt.git;a=commit;h=42120bd7f323ff7170b32a5fd4674babd8b184bc Yeah I even copied that init sequence over to this driver, however I actually think I have the LED activity somewhat under control in this new driver as those registers were kind-of-sort-of documented in the vendor code drop. It turns out the D-Link thing I am playing with doesn't even have any LEDs mounted so I can't test it though. Yours, Linus Walleij