Message ID | 20180814124254.5229-7-peter.maydell@linaro.org |
---|---|
State | Superseded |
Headers | show |
Series | target/arm: Some pieces of support for 32-bit Hyp mode | expand |
On Tue, Aug 14, 2018 at 01:42:50PM +0100, Peter Maydell wrote: > The AArch32 virtualization extensions support these fault address > registers: > * HDFAR: aliased with AArch64 FAR_EL2[31:0] and AArch32 DFAR(S) > * HIFAR: aliased with AArch64 FAR_EL2[63:32] and AArch32 IFAR(S) > > Implement the accessors for these. This fixes in passing a bug > where we weren't implementing the "RES0 from EL3 if EL2 not > implemented" behaviour for AArch64 FAR_EL2. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > --- > target/arm/helper.c | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 9701e413859..d6e98e9d606 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -3847,6 +3847,13 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { > { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, > .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, > + { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, > + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, > + .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, > + { .name = "HIFAR", .state = ARM_CP_STATE_AA32, > + .type = ARM_CP_CONST, > + .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, > + .access = PL2_RW, .resetvalue = 0 }, > REGINFO_SENTINEL > }; > > @@ -3922,9 +3929,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, > .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, > - { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, > + { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, > .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, > + { .name = "HIFAR", .state = ARM_CP_STATE_AA32, > + .type = ARM_CP_ALIAS, > + .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, > + .access = PL2_RW, > + .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[2]) }, > { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, > .type = ARM_CP_ALIAS, > .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, > -- > 2.18.0 >
On 8/14/18 2:42 PM, Peter Maydell wrote: > The AArch32 virtualization extensions support these fault address > registers: > * HDFAR: aliased with AArch64 FAR_EL2[31:0] and AArch32 DFAR(S) > * HIFAR: aliased with AArch64 FAR_EL2[63:32] and AArch32 IFAR(S) > > Implement the accessors for these. This fixes in passing a bug > where we weren't implementing the "RES0 from EL3 if EL2 not > implemented" behaviour for AArch64 FAR_EL2. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-By: Luc Michel <luc.michel@greensocs.com> > --- > target/arm/helper.c | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 9701e413859..d6e98e9d606 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -3847,6 +3847,13 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { > { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, > .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, > + { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, > + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, > + .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, > + { .name = "HIFAR", .state = ARM_CP_STATE_AA32, > + .type = ARM_CP_CONST, > + .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, > + .access = PL2_RW, .resetvalue = 0 }, > REGINFO_SENTINEL > }; > > @@ -3922,9 +3929,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, > .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, > - { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, > + { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, > .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, > + { .name = "HIFAR", .state = ARM_CP_STATE_AA32, > + .type = ARM_CP_ALIAS, > + .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, > + .access = PL2_RW, > + .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[2]) }, > { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, > .type = ARM_CP_ALIAS, > .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, >
diff --git a/target/arm/helper.c b/target/arm/helper.c index 9701e413859..d6e98e9d606 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3847,6 +3847,13 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, + .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "HIFAR", .state = ARM_CP_STATE_AA32, + .type = ARM_CP_CONST, + .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, + .access = PL2_RW, .resetvalue = 0 }, REGINFO_SENTINEL }; @@ -3922,9 +3929,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, - { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, + { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, + { .name = "HIFAR", .state = ARM_CP_STATE_AA32, + .type = ARM_CP_ALIAS, + .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, + .access = PL2_RW, + .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[2]) }, { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, .type = ARM_CP_ALIAS, .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
The AArch32 virtualization extensions support these fault address registers: * HDFAR: aliased with AArch64 FAR_EL2[31:0] and AArch32 DFAR(S) * HIFAR: aliased with AArch64 FAR_EL2[63:32] and AArch32 IFAR(S) Implement the accessors for these. This fixes in passing a bug where we weren't implementing the "RES0 from EL3 if EL2 not implemented" behaviour for AArch64 FAR_EL2. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/helper.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) -- 2.18.0