Message ID | 088724896f21d556ecf1e16a6c59c0e404444fa6.1536744310.git.amit.kucheria@linaro.org |
---|---|
State | Accepted |
Commit | 58443fd91057f073306cbbfc9db3b6a292fd51e5 |
Headers | show |
Series | None | expand |
On Wed, Sep 12, 2018 at 03:22:54PM +0530, Amit Kucheria wrote: > We've earlier added support to split the register address space into TM > and SROT regions. Split up the regmap address space into two for msm8974 > that has a similar register layout. > > Since tsens-common.c/init_common() currently only registers one address > space, the order is important (TM before SROT). This is OK since the > code doesn't really use the SROT functionality yet. > > Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> > Reviewed-by: Matthias Kaehlcke <mka@chromium.org> > --- Acked-by: Andy Gross <andy.gross@linaro.org>
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index d9019a49b292..56dbbf788d15 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -427,9 +427,10 @@ }; }; - tsens: thermal-sensor@fc4a8000 { + tsens: thermal-sensor@fc4a9000 { compatible = "qcom,msm8974-tsens"; - reg = <0xfc4a8000 0x2000>; + reg = <0xfc4a9000 0x1000>, /* TM */ + <0xfc4a8000 0x1000>; /* SROT */ nvmem-cells = <&tsens_calib>, <&tsens_backup>; nvmem-cell-names = "calib", "calib_backup"; #thermal-sensor-cells = <1>;