| Message ID | 20181128164939.8329-2-julien.grall@arm.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | xen/arm: Workaround for Cortex-A76 erratum 1165522 | expand |
On 28.11.18 18:49, Julien Grall wrote: > Only {A,F,I}MO are necessary to receive interrupts until a guest vCPU is > loaded. > > The rest have no effect on Xen and it is better to avoid setting them. > > Signed-off-by: Julien Grall <julien.grall@arm.com> > --- > xen/arch/arm/traps.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) Reviewed-by: Andrii Anisov <andrii_anisov@epam.com>
On Wed, 28 Nov 2018, Julien Grall wrote: > Only {A,F,I}MO are necessary to receive interrupts until a guest vCPU is > loaded. > > The rest have no effect on Xen and it is better to avoid setting them. > > Signed-off-by: Julien Grall <julien.grall@arm.com> > --- > xen/arch/arm/traps.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c > index 88ffeeb480..1eec966299 100644 > --- a/xen/arch/arm/traps.c > +++ b/xen/arch/arm/traps.c > @@ -181,8 +181,12 @@ void init_traps(void) > WRITE_SYSREG((HCPTR_CP_MASK & ~(HCPTR_CP(10) | HCPTR_CP(11))) | HCPTR_TTA, > CPTR_EL2); > > - /* Setup hypervisor traps */ > - WRITE_SYSREG(get_default_hcr_flags(), HCR_EL2); > + /* > + * Configure HCR_EL2 with the bareminimum to run Xen until a guest ^ bare minimum > + * is scheduled. {A,I,F}MO bits are set to allow EL2 receiving > + * interrupts. > + */ > + WRITE_SYSREG(HCR_AMO | HCR_FMO | HCR_IMO, HCR_EL2); > isb(); > } Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 88ffeeb480..1eec966299 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -181,8 +181,12 @@ void init_traps(void) WRITE_SYSREG((HCPTR_CP_MASK & ~(HCPTR_CP(10) | HCPTR_CP(11))) | HCPTR_TTA, CPTR_EL2); - /* Setup hypervisor traps */ - WRITE_SYSREG(get_default_hcr_flags(), HCR_EL2); + /* + * Configure HCR_EL2 with the bareminimum to run Xen until a guest + * is scheduled. {A,I,F}MO bits are set to allow EL2 receiving + * interrupts. + */ + WRITE_SYSREG(HCR_AMO | HCR_FMO | HCR_IMO, HCR_EL2); isb(); }
Only {A,F,I}MO are necessary to receive interrupts until a guest vCPU is loaded. The rest have no effect on Xen and it is better to avoid setting them. Signed-off-by: Julien Grall <julien.grall@arm.com> --- xen/arch/arm/traps.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)