| Message ID | 1544519572-21921-1-git-send-email-zhang.chunyan@linaro.org |
|---|---|
| Headers | show |
| Series | Add support for using external dma in SDHCI | expand |
Hi Chunyan, On 11/12/18 2:42 PM, Chunyan Zhang wrote: > Some standard SD host controllers can support both external dma > controllers as well as ADMA/SDMA in which the SD host controller > acts as DMA master. TI's omap controller is the case as an example. > > Currently the generic SDHCI code supports ADMA/SDMA integrated in > the host controller but does not have any support for external DMA > controllers implemented using dmaengine, meaning that custom code is > needed for any systems that use an external DMA controller with SDHCI. > > Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> > --- > drivers/mmc/host/Kconfig | 3 + > drivers/mmc/host/sdhci.c | 250 ++++++++++++++++++++++++++++++++++++++++++++++- > drivers/mmc/host/sdhci.h | 8 ++ > 3 files changed, 260 insertions(+), 1 deletion(-) > > diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig > index 1b58739..3101da6 100644 > --- a/drivers/mmc/host/Kconfig > +++ b/drivers/mmc/host/Kconfig > @@ -977,3 +977,6 @@ config MMC_SDHCI_OMAP > If you have a controller with this interface, say Y or M here. > > If unsure, say N. > + > +config MMC_SDHCI_EXTERNAL_DMA > + bool > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c > index 99bdae5..3162e60 100644 > --- a/drivers/mmc/host/sdhci.c > +++ b/drivers/mmc/host/sdhci.c > @@ -14,6 +14,7 @@ > */ > > #include <linux/delay.h> > +#include <linux/dmaengine.h> > #include <linux/ktime.h> > #include <linux/highmem.h> > #include <linux/io.h> > @@ -1097,6 +1098,221 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) > } > } > > +#if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA) > +static int sdhci_external_dma_init(struct sdhci_host *host) > +{ > + int ret = 0; > + struct mmc_host *mmc = host->mmc; > + > + host->tx_chan = dma_request_chan(mmc->parent, "tx"); > + if (IS_ERR(host->tx_chan)) { > + ret = PTR_ERR(host->tx_chan); > + if (ret != -EPROBE_DEFER) > + pr_warn("Failed to request TX DMA channel.\n"); > + host->tx_chan = NULL; > + return ret; > + } > + > + host->rx_chan = dma_request_chan(mmc->parent, "rx"); > + if (IS_ERR(host->rx_chan)) { > + if (host->tx_chan) { > + dma_release_channel(host->tx_chan); > + host->tx_chan = NULL; > + } > + > + ret = PTR_ERR(host->rx_chan); > + if (ret != -EPROBE_DEFER) > + pr_warn("Failed to request RX DMA channel.\n"); > + host->rx_chan = NULL; > + } > + > + return ret; > +} > + > +static inline struct dma_chan * > +sdhci_external_dma_channel(struct sdhci_host *host, struct mmc_data *data) > +{ > + return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; > +} > + > +static int sdhci_external_dma_setup(struct sdhci_host *host, > + struct mmc_command *cmd) > +{ > + int ret, i; > + struct dma_async_tx_descriptor *desc; > + struct mmc_data *data = cmd->data; > + struct dma_chan *chan; > + struct dma_slave_config cfg; > + dma_cookie_t cookie; > + > + if (!host->mapbase) > + return -EINVAL; > + > + cfg.src_addr = host->mapbase + SDHCI_BUFFER; > + cfg.dst_addr = host->mapbase + SDHCI_BUFFER; > + cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; > + cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; > + cfg.src_maxburst = data->blksz / 4; > + cfg.dst_maxburst = data->blksz / 4; > + > + /* Sanity check: all the SG entries must be aligned by block size. */ > + for (i = 0; i < data->sg_len; i++) { > + if ((data->sg + i)->length % data->blksz) > + return -EINVAL; > + } > + > + chan = sdhci_external_dma_channel(host, data); > + > + ret = dmaengine_slave_config(chan, &cfg); > + if (ret) > + return ret; > + > + desc = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, > + mmc_get_dma_dir(data), > + DMA_PREP_INTERRUPT | DMA_CTRL_ACK); > + if (!desc) > + return -EINVAL; > + > + desc->callback = NULL; > + desc->callback_param = NULL; > + > + cookie = dmaengine_submit(desc); > + if (cookie < 0) > + ret = cookie; > + > + return ret; > +} > + > +static void sdhci_external_dma_release(struct sdhci_host *host) > +{ > + if (host->tx_chan) { > + dma_release_channel(host->tx_chan); > + host->tx_chan = NULL; > + } > + > + if (host->rx_chan) { > + dma_release_channel(host->rx_chan); > + host->rx_chan = NULL; > + } > + > + sdhci_switch_external_dma(host, false); > +} > + > +static int __sdhci_external_dma_prepare_data(struct sdhci_host *host, > + struct mmc_command *cmd) > +{ > + struct mmc_data *data = cmd->data; > + int sg_cnt; > + > + host->data_timeout = 0; > + > + if (sdhci_data_line_cmd(cmd)) > + sdhci_set_timeout(host, cmd); > + > + WARN_ON(host->data); > + > + /* Sanity checks */ > + WARN_ON(data->blksz * data->blocks > 524288); > + WARN_ON(data->blksz > host->mmc->max_blk_size); > + WARN_ON(data->blocks > 65535); > + > + host->flags |= SDHCI_REQ_USE_DMA; > + host->data = data; > + host->data_early = 0; > + host->data->bytes_xfered = 0; > + > + sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED); > + if (sg_cnt <= 0) > + return -EINVAL; > + > + sdhci_set_transfer_irqs(host); > + > + /* > + * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count > + * can be supported, in that case 16-bit block count register must be 0. > + */ > + if (host->version >= SDHCI_SPEC_410 && host->v4_mode && > + (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) { > + if (sdhci_readw(host, SDHCI_BLOCK_COUNT)) > + sdhci_writew(host, 0, SDHCI_BLOCK_COUNT); > + sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT); > + } else { > + sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); > + } > + > + return 0; > +} > + > +static void sdhci_external_dma_prepare_data(struct sdhci_host *host, > + struct mmc_command *cmd) > +{ > + struct mmc_data *data = cmd->data; > + > + if (!data) > + return; > + > + if (sdhci_external_dma_setup(host, cmd) || > + __sdhci_external_dma_prepare_data(host, cmd)) { > + sdhci_external_dma_release(host); > + pr_err("%s: Cannot use external DMA, switch to the DMA/PIO which standard SDHCI provides.\n", > + mmc_hostname(host->mmc)); > + sdhci_prepare_data(host, cmd); > + } > +} > + > +static void sdhci_external_dma_pre_transfer(struct sdhci_host *host, > + struct mmc_command *cmd) > +{ > + struct dma_chan *chan = sdhci_external_dma_channel(host, cmd->data); Again, cmd->data can be NULL. Even after fixing above, I get some l3_noc issues. [ 3.589896] omap_l3_noc 44000000.ocp: L3 application error: target 5 mod:1 (unclearable) [ 3.598157] omap_l3_noc 44000000.ocp: L3 debug error: target 5 mod:1 (unclearable) [ 3.630934] softirq: Attempt to kill tasklet from interrupt [ 3.636790] mmc0: error -84 whilst initialising SD card Full log: https://pastebin.ubuntu.com/p/wdG88hX5By/ I am in the process of debugging this. Please ping if you need any further logs. Thanks, Faiz
On 11/12/18 11:12 AM, Chunyan Zhang wrote: > Some standard SD host controllers can support both external dma > controllers as well as ADMA/SDMA in which the SD host controller > acts as DMA master. TI's omap controller is the case as an example. > > Currently the generic SDHCI code supports ADMA/SDMA integrated in > the host controller but does not have any support for external DMA > controllers implemented using dmaengine, meaning that custom code is > needed for any systems that use an external DMA controller with SDHCI. > > Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> FYI, I am waiting on successful testing before reviewing these patches again.
On Thu, 27 Dec 2018 at 15:44, Adrian Hunter <adrian.hunter@intel.com> wrote: > > On 11/12/18 11:12 AM, Chunyan Zhang wrote: > > Some standard SD host controllers can support both external dma > > controllers as well as ADMA/SDMA in which the SD host controller > > acts as DMA master. TI's omap controller is the case as an example. > > > > Currently the generic SDHCI code supports ADMA/SDMA integrated in > > the host controller but does not have any support for external DMA > > controllers implemented using dmaengine, meaning that custom code is > > needed for any systems that use an external DMA controller with SDHCI. > > > > Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> > > FYI, I am waiting on successful testing before reviewing these patches again. Yeah, that makes sense, thanks Adrian! I intend to send out another new patchset after the holidays. After had another look at omap_hsmmc, I knew something need to be modified (emailed Faiz about this privately), but I was still not sure if it can fix the problem Faiz found. Happy new year to all, Chunyan
Adrian, On 27/12/18 1:32 PM, Chunyan Zhang wrote: > On Thu, 27 Dec 2018 at 15:44, Adrian Hunter <adrian.hunter@intel.com> wrote: >> >> On 11/12/18 11:12 AM, Chunyan Zhang wrote: >>> Some standard SD host controllers can support both external dma >>> controllers as well as ADMA/SDMA in which the SD host controller >>> acts as DMA master. TI's omap controller is the case as an example. >>> >>> Currently the generic SDHCI code supports ADMA/SDMA integrated in >>> the host controller but does not have any support for external DMA >>> controllers implemented using dmaengine, meaning that custom code is >>> needed for any systems that use an external DMA controller with SDHCI. >>> >>> Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> >> >> FYI, I am waiting on successful testing before reviewing these patches again. > > Yeah, that makes sense, thanks Adrian! > > I intend to send out another new patchset after the holidays. > After had another look at omap_hsmmc, I knew something need to be > modified (emailed Faiz about this privately), but I was still not sure > if it can fix the problem Faiz found. > I am currently working on moving am335 and am43 devices from omap_hsmmc to sdhci-omap driver. External DMA would be an integral part of this. The plan is to post these patches as a part of my series after testing on all those devices. Thanks, Faiz