Message ID | 20190211193008.24101-2-ndesaulniers@google.com |
---|---|
State | Accepted |
Commit | ad15006cc78459d059af56729c4d9bed7c7fd860 |
Headers | show |
Series | [v2,1/4] init/Kconfig: add config support for detecting linker | expand |
On Tue, Feb 12, 2019 at 5:42 AM <ndesaulniers@google.com> wrote: > > This causes an issue when trying to build with `make LD=ld.lld` if > ld.lld and the rest of your cross tools aren't in the same directory > (ex. /usr/local/bin) (as is the case for Android's build system), as the > GCC_TOOLCHAIN_DIR then gets set based on `which $(LD)` which will point > where LLVM tools are, not GCC/binutils tools are located. > > Instead, select the GCC_TOOLCHAIN_DIR based on another tool provided by > binutils for which LLVM does not provide a substitute for, such as > elfedit. > > Fixes commit 785f11aa595b ("kbuild: Add better clang cross build support") > > Link: https://github.com/ClangBuiltLinux/linux/issues/341 > Suggested-by: Nathan Chancellor <natechancellor@gmail.com> > Reviewed-by: Nathan Chancellor <natechancellor@gmail.com> > Tested-by: Nathan Chancellor <natechancellor@gmail.com> > Signed-off-by: Nick Desaulniers <ndesaulniers@google.com> > --- This one looks correct to me. Applied to linux-kbuild. > Changes V1->V2: > * add reviewed and tested tags. > > Makefile | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Makefile b/Makefile > index 86cf35d1d79d..d3b65e96d183 100644 > --- a/Makefile > +++ b/Makefile > @@ -492,7 +492,7 @@ endif > ifneq ($(shell $(CC) --version 2>&1 | head -n 1 | grep clang),) > ifneq ($(CROSS_COMPILE),) > CLANG_FLAGS := --target=$(notdir $(CROSS_COMPILE:%-=%)) > -GCC_TOOLCHAIN_DIR := $(dir $(shell which $(LD))) > +GCC_TOOLCHAIN_DIR := $(dir $(shell which $(CROSS_COMPILE)elfedit)) > CLANG_FLAGS += --prefix=$(GCC_TOOLCHAIN_DIR) > GCC_TOOLCHAIN := $(realpath $(GCC_TOOLCHAIN_DIR)/..) > endif > -- > 2.20.1.791.gb4d0f1c61a-goog > -- Best Regards Masahiro Yamada
diff --git a/Makefile b/Makefile index 86cf35d1d79d..d3b65e96d183 100644 --- a/Makefile +++ b/Makefile @@ -492,7 +492,7 @@ endif ifneq ($(shell $(CC) --version 2>&1 | head -n 1 | grep clang),) ifneq ($(CROSS_COMPILE),) CLANG_FLAGS := --target=$(notdir $(CROSS_COMPILE:%-=%)) -GCC_TOOLCHAIN_DIR := $(dir $(shell which $(LD))) +GCC_TOOLCHAIN_DIR := $(dir $(shell which $(CROSS_COMPILE)elfedit)) CLANG_FLAGS += --prefix=$(GCC_TOOLCHAIN_DIR) GCC_TOOLCHAIN := $(realpath $(GCC_TOOLCHAIN_DIR)/..) endif