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[00/67] target/arm: Convert aa32 base isa to decodetree

Message ID 20190726175032.6769-1-richard.henderson@linaro.org
Headers show
Series target/arm: Convert aa32 base isa to decodetree | expand

Message

Richard Henderson July 26, 2019, 5:49 p.m. UTC 
This unifies the implementation of the actual instructions
for a32, t32, and t16.  In order to make this happen, we
need several preliminary cleanups.  Most importantly to how
we handle the architectural representation of PC.

I attempt to convert single groups of instructions at once,
as they are grouped in the sections of the encoding sections
of the manual.

This has been tested by running the debian 9 armhf installer,
which does a far amount of switching between arm and thumb modes.
I've also run Peter's ARM TFM image, and all of the existing
RISU tests that we have.  (Our RISU test cases are nowhere near
complete for 32-bit mode, but it did find 3 bugs, so not useless.)

What's left is converting NEON and iwmmxt, then we could start
merging some of the decoders and tidying the top-level interface
further.

We will need to convert NEON in order to have a good chance at
finishing the ARMv8.2-FHP extension.


r~


Richard Henderson (67):
  decodetree: Allow !function with no input bits
  target/arm: Remove offset argument to gen_exception_insn
  target/arm: Remove offset argument to gen_exception_bkpt_insn
  target/arm: Remove offset argument to gen_exception_internal_insn
  target/arm: Use the saved value of the insn address
  target/arm: Introduce pc_read
  target/arm: Introduce add_reg_for_lit
  target/arm: Use store_reg_from_load in thumb2 code
  target/arm: Fold a pc load into load_reg
  target/arm: Move test for AL into arm_skip_unless
  target/arm: Add stubs for aa32 decodetree
  target/arm: Introduce gen_illegal_op
  target/arm: Convert Data Processing (reg, reg-shifted-reg, imm)
  target/arm: Convert multiply and multiply accumulate
  target/arm: Convert Saturating addition and subtraction
  target/arm: Convert Halfword multiply and multiply accumulate
  target/arm: Convert MSR (immediate) and hints
  target/arm: Convert MRS/MSR (banked, register)
  target/arm: Convert Cyclic Redundancy Check
  target/arm: Convert the rest of A32 Miscelaneous instructions
  target/arm: Convert T32 ADDW/SUBW
  target/arm: Convert load/store (register, immediate, literal)
  target/arm: Convert Synchronization primitives
  target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF
  target/arm: Convert Parallel addition and subtraction
  target/arm: Convert Packing, unpacking, saturation, and reversal
  target/arm: Convert Signed multiply, signed and unsigned divide
  target/arm: Convert MOVW, MOVT
  target/arm: Convert LDM, STM
  target/arm: Convert B, BL, BLX (immediate)
  target/arm: Convert SVC
  target/arm: Convert RFE and SRS
  target/arm: Convert Clear-Exclusive, Barriers
  target/arm: Convert CPS (privileged)
  target/arm: Convert SETEND
  target/arm: Convert PLI, PLD, PLDW
  target/arm: Convert Unallocated memory hint
  target/arm: Convert Table Branch
  target/arm: Convert SG
  target/arm: Convert TT
  target/arm: Simplify disas_thumb2_insn
  target/arm: Simplify disas_arm_insn
  target/arm: Add skeleton for T16 decodetree
  target/arm: Convert T16 data-processing (two low regs)
  target/arm: Convert T16 load/store (register offset)
  target/arm: Convert T16 load/store (immediate offset)
  target/arm: Convert T16 add pc/sp (immediate)
  target/arm: Convert T16 load/store multiple
  target/arm: Convert T16 add/sub (3 low, 2 low and imm)
  target/arm: Convert T16 one low register and immediate
  target/arm: Convert T16 branch and exchange
  target/arm: Convert T16 add, compare, move (two high registers)
  target/arm: Convert T16 adjust sp (immediate)
  target/arm: Convert T16, extract
  target/arm: Convert T16, Change processor state
  target/arm: Convert T16, Reverse bytes
  target/arm: Convert T16, nop hints
  target/arm: Convert T16, push and pop
  target/arm: Convert T16, Conditional branches, Supervisor call
  target/arm: Convert T16, Miscellaneous 16-bit instructions
  target/arm: Convert T16, shift immediate
  target/arm: Convert T16, load (literal)
  target/arm: Convert T16, Unconditional branch
  target/arm: Convert T16, long branches
  target/arm: Clean up disas_thumb_insn
  target/arm: Move singlestep check from gen_jmp to gen_goto_tb
  target/arm: Merge gen_bx_im into trans_BLX_i

 target/arm/helper.h               |    1 -
 target/arm/translate.h            |   10 +
 target/arm/op_helper.c            |   15 -
 target/arm/translate-vfp.inc.c    |   41 +-
 target/arm/translate.c            | 7142 ++++++++++++-----------------
 scripts/decodetree.py             |    5 +-
 target/arm/Makefile.objs          |   24 +
 target/arm/a32-uncond.decode      |   74 +
 target/arm/a32.decode             |  534 +++
 target/arm/t16.decode             |  279 ++
 target/arm/t32.decode             |  629 +++
 tests/decode/succ_function.decode |    2 +
 12 files changed, 4559 insertions(+), 4197 deletions(-)
 create mode 100644 target/arm/a32-uncond.decode
 create mode 100644 target/arm/a32.decode
 create mode 100644 target/arm/t16.decode
 create mode 100644 target/arm/t32.decode
 create mode 100644 tests/decode/succ_function.decode

-- 
2.17.1

Comments

no-reply@patchew.org July 26, 2019, 6:40 p.m. UTC | #1 
Patchew URL: https://patchew.org/QEMU/20190726175032.6769-1-richard.henderson@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Subject: [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree
Message-id: 20190726175032.6769-1-richard.henderson@linaro.org

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]         patchew/20190726175032.6769-1-richard.henderson@linaro.org -> patchew/20190726175032.6769-1-richard.henderson@linaro.org
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/edk2' (https://git.qemu.org/git/edk2.git) registered for path 'roms/edk2'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/opensbi' (https://git.qemu.org/git/opensbi.git) registered for path 'roms/opensbi'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://git.qemu.org/git/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'slirp' (https://git.qemu.org/git/libslirp.git) registered for path 'slirp'
Submodule 'tests/fp/berkeley-softfloat-3' (https://git.qemu.org/git/berkeley-softfloat-3.git) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://git.qemu.org/git/berkeley-testfloat-3.git) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out '90c488d5f4a407342247b9ea869df1c2d9c8e266'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 'ba1ab360eebe6338bb8d7d83a9220ccf7e213af3'
Cloning into 'roms/edk2'...
Submodule path 'roms/edk2': checked out '20d2e5a125e34fc8501026613a71549b2a1a3e54'
Submodule 'SoftFloat' (https://github.com/ucb-bar/berkeley-softfloat-3.git) registered for path 'ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3'
Submodule 'CryptoPkg/Library/OpensslLib/openssl' (https://github.com/openssl/openssl) registered for path 'CryptoPkg/Library/OpensslLib/openssl'
Cloning into 'ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3'...
Submodule path 'roms/edk2/ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'CryptoPkg/Library/OpensslLib/openssl'...
Submodule path 'roms/edk2/CryptoPkg/Library/OpensslLib/openssl': checked out '50eaac9f3337667259de725451f201e784599687'
Submodule 'boringssl' (https://boringssl.googlesource.com/boringssl) registered for path 'boringssl'
Submodule 'krb5' (https://github.com/krb5/krb5) registered for path 'krb5'
Submodule 'pyca.cryptography' (https://github.com/pyca/cryptography.git) registered for path 'pyca-cryptography'
Cloning into 'boringssl'...
Submodule path 'roms/edk2/CryptoPkg/Library/OpensslLib/openssl/boringssl': checked out '2070f8ad9151dc8f3a73bffaa146b5e6937a583f'
Cloning into 'krb5'...
Submodule path 'roms/edk2/CryptoPkg/Library/OpensslLib/openssl/krb5': checked out 'b9ad6c49505c96a088326b62a52568e3484f2168'
Cloning into 'pyca-cryptography'...
Submodule path 'roms/edk2/CryptoPkg/Library/OpensslLib/openssl/pyca-cryptography': checked out '09403100de2f6f1cdd0d484dcb8e620f1c335c8f'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out 'c79e0ecb84f4f1ee3f73f521622e264edd1bf174'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/opensbi'...
Submodule path 'roms/opensbi': checked out 'ce228ee0919deb9957192d723eecc8aaae2697c6'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out 'bf0e13698872450164fa7040da36a95d2d4b326f'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a5cab58e9a3fb6e168aba919c5669bea406573b4'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '0f4fe84658165e96ce35870fd19fc634e182e77b'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out '261ca8e779e5138869a45f174caa49be6a274501'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd3689267f92c5956e09cc7d1baa4700141662bff'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'slirp'...
Submodule path 'slirp': checked out 'f0da6726207b740f6101028b2992f918477a4b08'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
3e96cf9 target/arm: Merge gen_bx_im into trans_BLX_i
773c770 target/arm: Move singlestep check from gen_jmp to gen_goto_tb
2a5246b target/arm: Clean up disas_thumb_insn
f985ef5 target/arm: Convert T16, long branches
2faac2a target/arm: Convert T16, Unconditional branch
1fb21ac target/arm: Convert T16, load (literal)
3624e32 target/arm: Convert T16, shift immediate
4fe1b9f target/arm: Convert T16, Miscellaneous 16-bit instructions
6a11d6a target/arm: Convert T16, Conditional branches, Supervisor call
ef85099 target/arm: Convert T16, push and pop
8e66d6c target/arm: Convert T16, nop hints
bbf4fab target/arm: Convert T16, Reverse bytes
b9d3b3d target/arm: Convert T16, Change processor state
8a316ac target/arm: Convert T16, extract
11f12d3 target/arm: Convert T16 adjust sp (immediate)
db70a80 target/arm: Convert T16 add, compare, move (two high registers)
a4baf44 target/arm: Convert T16 branch and exchange
b1de765 target/arm: Convert T16 one low register and immediate
521cb4f target/arm: Convert T16 add/sub (3 low, 2 low and imm)
ea841ad target/arm: Convert T16 load/store multiple
a24f7c2 target/arm: Convert T16 add pc/sp (immediate)
23702d1 target/arm: Convert T16 load/store (immediate offset)
e018c38 target/arm: Convert T16 load/store (register offset)
d375237 target/arm: Convert T16 data-processing (two low regs)
e2b0a6c target/arm: Add skeleton for T16 decodetree
36b9fa0 target/arm: Simplify disas_arm_insn
587b818 target/arm: Simplify disas_thumb2_insn
c030f15 target/arm: Convert TT
f07ccb6 target/arm: Convert SG
5b658a2 target/arm: Convert Table Branch
44ae137 target/arm: Convert Unallocated memory hint
22dc1ab target/arm: Convert PLI, PLD, PLDW
48b0cc4 target/arm: Convert SETEND
396f9b0 target/arm: Convert CPS (privileged)
9f42967 target/arm: Convert Clear-Exclusive, Barriers
6d7832b target/arm: Convert RFE and SRS
6baefa5 target/arm: Convert SVC
66bdd2b target/arm: Convert B, BL, BLX (immediate)
bb053c6 target/arm: Convert LDM, STM
129900f target/arm: Convert MOVW, MOVT
6cd498d target/arm: Convert Signed multiply, signed and unsigned divide
5f3c9f7 target/arm: Convert Packing, unpacking, saturation, and reversal
e2a764f target/arm: Convert Parallel addition and subtraction
837c8be target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF
f4c9598 target/arm: Convert Synchronization primitives
e74158e target/arm: Convert load/store (register, immediate, literal)
c2962d5 target/arm: Convert T32 ADDW/SUBW
f41f8e6 target/arm: Convert the rest of A32 Miscelaneous instructions
a063450 target/arm: Convert Cyclic Redundancy Check
670924b target/arm: Convert MRS/MSR (banked, register)
0ca68c3 target/arm: Convert MSR (immediate) and hints
76ae2b1 target/arm: Convert Halfword multiply and multiply accumulate
b9c7121 target/arm: Convert Saturating addition and subtraction
4cf0de3 target/arm: Convert multiply and multiply accumulate
8f08e2c target/arm: Convert Data Processing (reg, reg-shifted-reg, imm)
9ff2962 target/arm: Introduce gen_illegal_op
9203cc5 target/arm: Add stubs for aa32 decodetree
c652286 target/arm: Move test for AL into arm_skip_unless
862414e target/arm: Fold a pc load into load_reg
69b8001 target/arm: Use store_reg_from_load in thumb2 code
b6cabf9 target/arm: Introduce add_reg_for_lit
840fdc0 target/arm: Introduce pc_read
5fa3ae2 target/arm: Use the saved value of the insn address
77512cc target/arm: Remove offset argument to gen_exception_internal_insn
17825b7 target/arm: Remove offset argument to gen_exception_bkpt_insn
eeda82e target/arm: Remove offset argument to gen_exception_insn
79d20cd decodetree: Allow !function with no input bits

=== OUTPUT BEGIN ===
1/67 Checking commit 79d20cda7b96 (decodetree: Allow !function with no input bits)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#29: 
new file mode 100644

total: 0 errors, 1 warnings, 13 lines checked

Patch 1/67 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
2/67 Checking commit eeda82e2506e (target/arm: Remove offset argument to gen_exception_insn)
3/67 Checking commit 17825b7218c5 (target/arm: Remove offset argument to gen_exception_bkpt_insn)
4/67 Checking commit 77512ccb9bdc (target/arm: Remove offset argument to gen_exception_internal_insn)
5/67 Checking commit 5fa3ae205e44 (target/arm: Use the saved value of the insn address)
6/67 Checking commit 840fdc031133 (target/arm: Introduce pc_read)
7/67 Checking commit b6cabf97a6e9 (target/arm: Introduce add_reg_for_lit)
8/67 Checking commit 69b8001fbec9 (target/arm: Use store_reg_from_load in thumb2 code)
9/67 Checking commit 862414ea9430 (target/arm: Fold a pc load into load_reg)
10/67 Checking commit c65228636caf (target/arm: Move test for AL into arm_skip_unless)
11/67 Checking commit 9203cc5c93cb (target/arm: Add stubs for aa32 decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#46: 
new file mode 100644

WARNING: architecture specific defines should be avoided
#147: FILE: target/arm/translate.c:7728:
+# ifdef __clang__

total: 0 errors, 2 warnings, 168 lines checked

Patch 11/67 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
12/67 Checking commit 9ff2962de826 (target/arm: Introduce gen_illegal_op)
13/67 Checking commit 8f08e2cadfd9 (target/arm: Convert Data Processing (reg, reg-shifted-reg, imm))
ERROR: suspect code indent for conditional statements (13, 17)
#551: FILE: target/arm/translate.c:8014:
+             if (a->s && a->rd == 15) {
+                 if (IS_USER(s)) {

ERROR: suspect code indent for conditional statements (17, 21)
#552: FILE: target/arm/translate.c:8015:
+                 if (IS_USER(s)) {
+                     return false;

ERROR: suspect code indent for conditional statements (13, 17)
#575: FILE: target/arm/translate.c:8038:
+             if (a->s && a->rd == 15) {
+                 if (IS_USER(s)) {

ERROR: suspect code indent for conditional statements (17, 21)
#576: FILE: target/arm/translate.c:8039:
+                 if (IS_USER(s)) {
+                     return false;

ERROR: suspect code indent for conditional statements (13, 17)
#580: FILE: target/arm/translate.c:8043:
+             } else if (a->rn == 13) {
+                 result = STREG_SP_CHECK;

total: 5 errors, 0 warnings, 988 lines checked

Patch 13/67 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

14/67 Checking commit 4cf0de31365c (target/arm: Convert multiply and multiply accumulate)
15/67 Checking commit b9c7121e3e94 (target/arm: Convert Saturating addition and subtraction)
16/67 Checking commit 76ae2b182e23 (target/arm: Convert Halfword multiply and multiply accumulate)
17/67 Checking commit 0ca68c3e6e2d (target/arm: Convert MSR (immediate) and hints)
18/67 Checking commit 670924bed154 (target/arm: Convert MRS/MSR (banked, register))
19/67 Checking commit a06345040de2 (target/arm: Convert Cyclic Redundancy Check)
20/67 Checking commit f41f8e6227d0 (target/arm: Convert the rest of A32 Miscelaneous instructions)
21/67 Checking commit c2962d5d2129 (target/arm: Convert T32 ADDW/SUBW)
22/67 Checking commit e74158ee8bb6 (target/arm: Convert load/store (register, immediate, literal))
23/67 Checking commit f4c9598830eb (target/arm: Convert Synchronization primitives)
24/67 Checking commit 837c8be4e20e (target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF)
25/67 Checking commit e2a764fd4e94 (target/arm: Convert Parallel addition and subtraction)
26/67 Checking commit 5f3c9f750009 (target/arm: Convert Packing, unpacking, saturation, and reversal)
ERROR: trailing statements should be on next line
#803: FILE: target/arm/translate.c:11485:
+            case 1: gen_rev16(tmp, tmp); break;

ERROR: trailing statements should be on next line
#804: FILE: target/arm/translate.c:11486:
+            case 3: gen_revsh(tmp, tmp); break;

total: 2 errors, 0 warnings, 766 lines checked

Patch 26/67 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

27/67 Checking commit 6cd498dafa86 (target/arm: Convert Signed multiply, signed and unsigned divide)
28/67 Checking commit 129900feabf2 (target/arm: Convert MOVW, MOVT)
29/67 Checking commit bb053c64948b (target/arm: Convert LDM, STM)
30/67 Checking commit 66bdd2bc9873 (target/arm: Convert B, BL, BLX (immediate))
31/67 Checking commit 6baefa579e7f (target/arm: Convert SVC)
32/67 Checking commit 6d7832b65962 (target/arm: Convert RFE and SRS)
ERROR: trailing statements should be on next line
#72: FILE: target/arm/translate.c:10010:
+    case 0: offset = -4; break; /* DA */

ERROR: trailing statements should be on next line
#73: FILE: target/arm/translate.c:10011:
+    case 1: offset =  0; break; /* IA */

ERROR: trailing statements should be on next line
#74: FILE: target/arm/translate.c:10012:
+    case 2: offset = -8; break; /* DB */

ERROR: trailing statements should be on next line
#75: FILE: target/arm/translate.c:10013:
+    case 3: offset =  4; break; /* IB */

ERROR: trailing statements should be on next line
#91: FILE: target/arm/translate.c:10029:
+        case 0: offset = -8; break;

ERROR: trailing statements should be on next line
#92: FILE: target/arm/translate.c:10030:
+        case 1: offset =  4; break;

ERROR: trailing statements should be on next line
#93: FILE: target/arm/translate.c:10031:
+        case 2: offset = -4; break;

ERROR: trailing statements should be on next line
#94: FILE: target/arm/translate.c:10032:
+        case 3: offset =  0; break;

total: 8 errors, 0 warnings, 208 lines checked

Patch 32/67 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

33/67 Checking commit 9f42967c7dfa (target/arm: Convert Clear-Exclusive, Barriers)
34/67 Checking commit 396f9b0af3b2 (target/arm: Convert CPS (privileged))
35/67 Checking commit 48b0cc4253ea (target/arm: Convert SETEND)
36/67 Checking commit 22dc1abca836 (target/arm: Convert PLI, PLD, PLDW)
37/67 Checking commit 44ae1372a386 (target/arm: Convert Unallocated memory hint)
38/67 Checking commit 5b658a206f20 (target/arm: Convert Table Branch)
39/67 Checking commit f07ccb66063e (target/arm: Convert SG)
40/67 Checking commit c030f15fdeb5 (target/arm: Convert TT)
41/67 Checking commit 587b818c6c56 (target/arm: Simplify disas_thumb2_insn)
42/67 Checking commit 36b9fa03aa30 (target/arm: Simplify disas_arm_insn)
43/67 Checking commit e2b0a6c5f0d1 (target/arm: Add skeleton for T16 decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

total: 0 errors, 1 warnings, 56 lines checked

Patch 43/67 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
44/67 Checking commit d375237de41a (target/arm: Convert T16 data-processing (two low regs))
45/67 Checking commit e018c3808763 (target/arm: Convert T16 load/store (register offset))
46/67 Checking commit 23702d173572 (target/arm: Convert T16 load/store (immediate offset))
47/67 Checking commit a24f7c2e5272 (target/arm: Convert T16 add pc/sp (immediate))
48/67 Checking commit ea841adddfbd (target/arm: Convert T16 load/store multiple)
49/67 Checking commit 521cb4f43ad1 (target/arm: Convert T16 add/sub (3 low, 2 low and imm))
50/67 Checking commit b1de765a80aa (target/arm: Convert T16 one low register and immediate)
51/67 Checking commit a4baf4481285 (target/arm: Convert T16 branch and exchange)
52/67 Checking commit db70a8090d99 (target/arm: Convert T16 add, compare, move (two high registers))
53/67 Checking commit 11f12d392985 (target/arm: Convert T16 adjust sp (immediate))
54/67 Checking commit 8a316ac286d3 (target/arm: Convert T16, extract)
55/67 Checking commit b9d3b3d6009e (target/arm: Convert T16, Change processor state)
56/67 Checking commit bbf4fabc01bb (target/arm: Convert T16, Reverse bytes)
57/67 Checking commit 8e66d6c87967 (target/arm: Convert T16, nop hints)
58/67 Checking commit ef8509911c56 (target/arm: Convert T16, push and pop)
59/67 Checking commit 6a11d6ac1c7e (target/arm: Convert T16, Conditional branches, Supervisor call)
60/67 Checking commit 4fe1b9f79975 (target/arm: Convert T16, Miscellaneous 16-bit instructions)
61/67 Checking commit 3624e32c47c1 (target/arm: Convert T16, shift immediate)
62/67 Checking commit 1fb21acaaff4 (target/arm: Convert T16, load (literal))
63/67 Checking commit 2faac2abfb65 (target/arm: Convert T16, Unconditional branch)
64/67 Checking commit f985ef5169f0 (target/arm: Convert T16, long branches)
65/67 Checking commit 2a5246bd4d7d (target/arm: Clean up disas_thumb_insn)
66/67 Checking commit 773c770a22d0 (target/arm: Move singlestep check from gen_jmp to gen_goto_tb)
67/67 Checking commit 3e96cf95bd0e (target/arm: Merge gen_bx_im into trans_BLX_i)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20190726175032.6769-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
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Please send your feedback to patchew-devel@redhat.com
Peter Maydell Aug. 5, 2019, 3:44 p.m. UTC | #2 
On Fri, 26 Jul 2019 at 18:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> This unifies the implementation of the actual instructions

> for a32, t32, and t16.  In order to make this happen, we

> need several preliminary cleanups.  Most importantly to how

> we handle the architectural representation of PC.


I'd be happy to take the preliminary-cleanups part (subject
to the various review comments) without waiting for the
rest of the series to get respun.

thanks
-- PMM
Richard Henderson Aug. 5, 2019, 9:26 p.m. UTC | #3 
On 8/5/19 8:44 AM, Peter Maydell wrote:
> On Fri, 26 Jul 2019 at 18:50, Richard Henderson

> <richard.henderson@linaro.org> wrote:

>>

>> This unifies the implementation of the actual instructions

>> for a32, t32, and t16.  In order to make this happen, we

>> need several preliminary cleanups.  Most importantly to how

>> we handle the architectural representation of PC.

> 

> I'd be happy to take the preliminary-cleanups part (subject

> to the various review comments) without waiting for the

> rest of the series to get respun.


I had an outstanding question re patch 4:
Message-ID: <c7a3ef78-d541-aa0a-21a5-8b4f48db1fd7@linaro.org>
https://lists.gnu.org/archive/html/qemu-devel/2019-07/msg06520.html

and another re patch 6:
Message-ID: <09b930e2-0a92-25a3-4e26-8bea1f437039@linaro.org>
https://lists.gnu.org/archive/html/qemu-devel/2019-07/msg06508.html


r~
Peter Maydell Aug. 6, 2019, 10:01 a.m. UTC | #4 
On Mon, 5 Aug 2019 at 22:26, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> On 8/5/19 8:44 AM, Peter Maydell wrote:

> > On Fri, 26 Jul 2019 at 18:50, Richard Henderson

> > <richard.henderson@linaro.org> wrote:

> >>

> >> This unifies the implementation of the actual instructions

> >> for a32, t32, and t16.  In order to make this happen, we

> >> need several preliminary cleanups.  Most importantly to how

> >> we handle the architectural representation of PC.

> >

> > I'd be happy to take the preliminary-cleanups part (subject

> > to the various review comments) without waiting for the

> > rest of the series to get respun.

>

> I had an outstanding question re patch 4:

> Message-ID: <c7a3ef78-d541-aa0a-21a5-8b4f48db1fd7@linaro.org>

> https://lists.gnu.org/archive/html/qemu-devel/2019-07/msg06520.html

>

> and another re patch 6:

> Message-ID: <09b930e2-0a92-25a3-4e26-8bea1f437039@linaro.org>

> https://lists.gnu.org/archive/html/qemu-devel/2019-07/msg06508.html


I've followed up to 4, 6 and 7 giving some thoughts on those.
Anywhere I've still not been very specific it's because I don't
have a clear idea of the right thing, so use your own judgement :-)

thanks
-- PMM