| Message ID | 1570733080-21015-9-git-send-email-Dave.Martin@arm.com |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: ARMv8.5-A: Branch Target Identification support | expand |
On 10/10/19 2:44 PM, Dave Martin wrote: > #define PSR_IL_BIT (1 << 20) > -#define PSR_BTYPE_CALL (2 << PSR_BTYPE_SHIFT) > + > +/* Convenience names for the values of PSTATE.BTYPE */ > +#define PSR_BTYPE_NONE (0b00 << PSR_BTYPE_SHIFT) > +#define PSR_BTYPE_JC (0b01 << PSR_BTYPE_SHIFT) > +#define PSR_BTYPE_C (0b10 << PSR_BTYPE_SHIFT) > +#define PSR_BTYPE_J (0b11 << PSR_BTYPE_SHIFT) It'd be nice to sort this patch earlier, so that ... > diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c > index 4a3bd32..452ac5b 100644 > --- a/arch/arm64/kernel/signal.c > +++ b/arch/arm64/kernel/signal.c > @@ -732,7 +732,7 @@ static void setup_return(struct pt_regs *regs, struct k_sigaction *ka, > > if (system_supports_bti()) { > regs->pstate &= ~PSR_BTYPE_MASK; > - regs->pstate |= PSR_BTYPE_CALL; > + regs->pstate |= PSR_BTYPE_C; > } > > if (ka->sa.sa_flags & SA_RESTORER) ... setup_return does not need to be adjusted a second time. I don't see any other conflicts vs patch 5. r~
On Fri, Oct 11, 2019 at 11:31:02AM -0400, Richard Henderson wrote: > On 10/10/19 2:44 PM, Dave Martin wrote: > > #define PSR_IL_BIT (1 << 20) > > -#define PSR_BTYPE_CALL (2 << PSR_BTYPE_SHIFT) > > + > > +/* Convenience names for the values of PSTATE.BTYPE */ > > +#define PSR_BTYPE_NONE (0b00 << PSR_BTYPE_SHIFT) > > +#define PSR_BTYPE_JC (0b01 << PSR_BTYPE_SHIFT) > > +#define PSR_BTYPE_C (0b10 << PSR_BTYPE_SHIFT) > > +#define PSR_BTYPE_J (0b11 << PSR_BTYPE_SHIFT) > > It'd be nice to sort this patch earlier, so that ... > > > diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c > > index 4a3bd32..452ac5b 100644 > > --- a/arch/arm64/kernel/signal.c > > +++ b/arch/arm64/kernel/signal.c > > @@ -732,7 +732,7 @@ static void setup_return(struct pt_regs *regs, struct k_sigaction *ka, > > > > if (system_supports_bti()) { > > regs->pstate &= ~PSR_BTYPE_MASK; > > - regs->pstate |= PSR_BTYPE_CALL; > > + regs->pstate |= PSR_BTYPE_C; > > } > > > > if (ka->sa.sa_flags & SA_RESTORER) > > ... setup_return does not need to be adjusted a second time. > > I don't see any other conflicts vs patch 5. Ack, looks like I mis-split this during rebase. Will fix. Cheers ---Dave
diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h index 7d4cd59..212bba1 100644 --- a/arch/arm64/include/asm/ptrace.h +++ b/arch/arm64/include/asm/ptrace.h @@ -38,7 +38,12 @@ #define PSR_BTYPE_SHIFT 10 #define PSR_IL_BIT (1 << 20) -#define PSR_BTYPE_CALL (2 << PSR_BTYPE_SHIFT) + +/* Convenience names for the values of PSTATE.BTYPE */ +#define PSR_BTYPE_NONE (0b00 << PSR_BTYPE_SHIFT) +#define PSR_BTYPE_JC (0b01 << PSR_BTYPE_SHIFT) +#define PSR_BTYPE_C (0b10 << PSR_BTYPE_SHIFT) +#define PSR_BTYPE_J (0b11 << PSR_BTYPE_SHIFT) /* AArch32-specific ptrace requests */ #define COMPAT_PTRACE_GETREGS 12 diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 4c78937..a2b555a 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -209,6 +209,15 @@ void machine_restart(char *cmd) while (1); } +#define bstr(suffix, str) [PSR_BTYPE_ ## suffix >> PSR_BTYPE_SHIFT] = str +static const char *const btypes[] = { + bstr(NONE, "--"), + bstr( JC, "jc"), + bstr( C, "-c"), + bstr( J , "j-") +}; +#undef bstr + static void print_pstate(struct pt_regs *regs) { u64 pstate = regs->pstate; @@ -227,7 +236,10 @@ static void print_pstate(struct pt_regs *regs) pstate & PSR_AA32_I_BIT ? 'I' : 'i', pstate & PSR_AA32_F_BIT ? 'F' : 'f'); } else { - printk("pstate: %08llx (%c%c%c%c %c%c%c%c %cPAN %cUAO)\n", + const char *btype_str = btypes[(pstate & PSR_BTYPE_MASK) >> + PSR_BTYPE_SHIFT]; + + printk("pstate: %08llx (%c%c%c%c %c%c%c%c %cPAN %cUAO BTYPE=%s)\n", pstate, pstate & PSR_N_BIT ? 'N' : 'n', pstate & PSR_Z_BIT ? 'Z' : 'z', @@ -238,7 +250,8 @@ static void print_pstate(struct pt_regs *regs) pstate & PSR_I_BIT ? 'I' : 'i', pstate & PSR_F_BIT ? 'F' : 'f', pstate & PSR_PAN_BIT ? '+' : '-', - pstate & PSR_UAO_BIT ? '+' : '-'); + pstate & PSR_UAO_BIT ? '+' : '-', + btype_str); } } diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c index 4a3bd32..452ac5b 100644 --- a/arch/arm64/kernel/signal.c +++ b/arch/arm64/kernel/signal.c @@ -732,7 +732,7 @@ static void setup_return(struct pt_regs *regs, struct k_sigaction *ka, if (system_supports_bti()) { regs->pstate &= ~PSR_BTYPE_MASK; - regs->pstate |= PSR_BTYPE_CALL; + regs->pstate |= PSR_BTYPE_C; } if (ka->sa.sa_flags & SA_RESTORER)
The current code to print PSTATE symbolically when generating backtraces etc., does not include the BYTPE field used by Branch Target Identification. So, decode BYTPE and print it too. In the interests of human-readability, print the classes of BTI matched. The symbolic notation, BYTPE (PSTATE[11:10]) and permitted classes of subsequent instruction are: -- (BTYPE=0b00): any insn jc (BTYPE=0b01): BTI jc, BTI j, BTI c, PACIxSP -c (BYTPE=0b10): BTI jc, BTI c, PACIxSP j- (BTYPE=0b11): BTI jc, BTI j Signed-off-by: Dave Martin <Dave.Martin@arm.com> --- Changes since v1: * Add convenience definitions for all the BTYPE codes, even if we don't directly use them all yet. * For consistency, align PSR_BTYPE_foo names with the above print format: PSR_BTYPE_NONE -> -- (BTYPE=0b00) PSR_BTYPE_JC -> jc (BTYPE=0b01) etc. --- arch/arm64/include/asm/ptrace.h | 7 ++++++- arch/arm64/kernel/process.c | 17 +++++++++++++++-- arch/arm64/kernel/signal.c | 2 +- 3 files changed, 22 insertions(+), 4 deletions(-) -- 2.1.4