| Message ID | 20200408165737.v5.9.Iff8dfbeef5f76f776cf3a84807b0ff3fd5a491ac@changeid |
|---|---|
| State | Superseded |
| Headers | show |
| Series | dm: Add programmatic generation of ACPI tables (part A) | expand |
On Thu, Apr 9, 2020 at 6:58 AM Simon Glass <sjg at chromium.org> wrote: > > With P2SB the initial BAR (base-address register) is set up by TPL and > this is used unchanged right through U-Boot. > > At present the reading of this address is split between the ofdata() and > probe() methods. There are a few problems that are unique to the p2sb. > One is that its children need to call pcr_read32(), etc. which needs to > have the p2sb address correct. Also some of its children are pinctrl > devices and pinctrl is used when any device is probed. So p2sb really > needs to get its base address set up in ofdata_to_platdata(), before it is > probed. > > Another point is that reading the p2sb BAR will not work if the p2sb is > hidden. The FSP-S seems to hide it, presumably to avoid confusing PCI > enumeration. > > Reading ofdata in ofdata_to_platdata() is the correct place anyway, so > this is easy to fix. > > Move the code into one place and use the early-regs property in all cases > for simplicity and to avoid needing to probe any PCI devices just to read > the BAR. > > Signed-off-by: Simon Glass <sjg at chromium.org> > Reviewed-by: Wolfgang Wallner <wolfgang.wallner at br-automation.com> > Tested-by: Wolfgang Wallner <wolfgang.wallner at br-automation.com> > --- > > Changes in v5: None > Changes in v4: None > Changes in v3: > - Fix indenting error mentioned by Andy Shevchenko > > Changes in v2: None > > arch/x86/cpu/intel_common/p2sb.c | 33 +++++++++++--------------------- > 1 file changed, 11 insertions(+), 22 deletions(-) > applied to u-boot-x86, thanks!
diff --git a/arch/x86/cpu/intel_common/p2sb.c b/arch/x86/cpu/intel_common/p2sb.c index d5b4846e0a2..6f3c4416186 100644 --- a/arch/x86/cpu/intel_common/p2sb.c +++ b/arch/x86/cpu/intel_common/p2sb.c @@ -92,46 +92,35 @@ int p2sb_ofdata_to_platdata(struct udevice *dev) #if !CONFIG_IS_ENABLED(OF_PLATDATA) int ret; + u32 base[2]; + ret = dev_read_u32_array(dev, "early-regs", base, ARRAY_SIZE(base)); + if (ret) + return log_msg_ret("Missing/short early-regs", ret); + plat->mmio_base = base[0]; + /* TPL sets up the initial BAR */ if (spl_phase() == PHASE_TPL) { - u32 base[2]; - - /* TPL sets up the initial BAR */ - ret = dev_read_u32_array(dev, "early-regs", base, - ARRAY_SIZE(base)); - if (ret) - return log_msg_ret("Missing/short early-regs", ret); - plat->mmio_base = base[0]; plat->bdf = pci_get_devfn(dev); if (plat->bdf < 0) return log_msg_ret("Cannot get p2sb PCI address", plat->bdf); } + upriv->mmio_base = plat->mmio_base; #else plat->mmio_base = plat->dtplat.early_regs[0]; plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]); -#endif upriv->mmio_base = plat->mmio_base; - debug("p2sb: mmio_base=%x\n", (uint)plat->mmio_base); +#endif return 0; } static int p2sb_probe(struct udevice *dev) { - if (spl_phase() == PHASE_TPL) { + if (spl_phase() == PHASE_TPL) return p2sb_early_init(dev); - } else { - struct p2sb_platdata *plat = dev_get_platdata(dev); - - plat->mmio_base = dev_read_addr_pci(dev); - /* Don't set BDF since it should not be used */ - if (!plat->mmio_base || plat->mmio_base == FDT_ADDR_T_NONE) - return -EINVAL; - - if (spl_phase() == PHASE_SPL) - return p2sb_spl_init(dev); - } + else if (spl_phase() == PHASE_SPL) + return p2sb_spl_init(dev); return 0; }