| Message ID | 1583807731-16484-3-git-send-email-bmeng.cn@gmail.com |
|---|---|
| State | Accepted |
| Commit | f58fc34a2b215a80adcf62c6e90793e23d6f915c |
| Headers | show |
| Series | riscv: Add new SBI v0.2 extensions support | expand |
Hi Bin, >-----Original Message----- >From: U-Boot <u-boot-bounces at lists.denx.de> On Behalf Of Bin Meng >Sent: 10 March 2020 08:05 >To: Rick Chen <rick at andestech.com>; Anup Patel <anup.patel at wdc.com>; >Atish Patra <atish.patra at wdc.com>; Lukas Auer ><lukas.auer at aisec.fraunhofer.de>; U-Boot Mailing List <u- >boot at lists.denx.de> >Subject: [PATCH 2/5] riscv: Add basic support for SBI v0.2 > >The SBI v0.2 introduces a base extension which is backward compatible with >v0.1. Implement all helper functions and minimum required SBI calls from >v0.2 for now. All other base extension function will be added later as per >need. > >As v0.2 calling convention is backward compatible with v0.1, remove the v0.1 >helper functions and just use v0.2 calling convention. > >Add a new Kconfig options CONFIG_SBI for the new SBI v0.2 codes, and let >CONFIG_SBI_IPI depend on it. > >This commit is inspired from Linux kernel patch: >https://patchwork.kernel.org/patch/11407363/ > >Signed-off-by: Bin Meng <bmeng.cn at gmail.com> >--- > > arch/riscv/Kconfig | 5 ++ > arch/riscv/include/asm/sbi.h | 135 +++++++++++++------------------- > arch/riscv/lib/Makefile | 1 + > arch/riscv/lib/sbi.c | 181 >+++++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 243 insertions(+), 79 deletions(-) create mode 100644 >arch/riscv/lib/sbi.c > >diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 3338b78..09fff05 >100644 >--- a/arch/riscv/Kconfig >+++ b/arch/riscv/Kconfig >@@ -210,8 +210,13 @@ config NR_CPUS > Stack memory is pre-allocated. U-Boot must therefore know the > maximum number of CPUs that may be present. > >+config SBI >+ bool >+ default y if RISCV_SMODE || SPL_RISCV_SMODE >+ > config SBI_IPI > bool >+ depends on SBI > default y if RISCV_SMODE || SPL_RISCV_SMODE > depends on SMP > >diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index >187ca58..fc8637c 100644 >--- a/arch/riscv/include/asm/sbi.h >+++ b/arch/riscv/include/asm/sbi.h >@@ -11,91 +11,68 @@ > > #include <linux/types.h> > >-#define SBI_EXT_0_1_SET_TIMER 0x0 >-#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1 -#define >SBI_EXT_0_1_CONSOLE_GETCHAR 0x2 -#define SBI_EXT_0_1_CLEAR_IPI 0x3 - >#define SBI_EXT_0_1_SEND_IPI 0x4 -#define SBI_EXT_0_1_REMOTE_FENCE_I >0x5 -#define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6 -#define >SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7 -#define >SBI_EXT_0_1_SHUTDOWN 0x8 >+enum sbi_ext_id { >+ SBI_EXT_0_1_SET_TIMER = 0x0, >+ SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1, >+ SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2, >+ SBI_EXT_0_1_CLEAR_IPI = 0x3, >+ SBI_EXT_0_1_SEND_IPI = 0x4, >+ SBI_EXT_0_1_REMOTE_FENCE_I = 0x5, >+ SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6, >+ SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7, >+ SBI_EXT_0_1_SHUTDOWN = 0x8, >+ SBI_EXT_BASE = 0x10, >+}; > >-#define SBI_CALL(which, arg0, arg1, arg2, arg3) ({ \ >- register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \ >- register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); \ >- register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); \ >- register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3); \ >- register uintptr_t a7 asm ("a7") = (uintptr_t)(which); \ >- asm volatile ("ecall" \ >- : "+r" (a0) \ >- : "r" (a1), "r" (a2), "r" (a3), "r" (a7) \ >- : "memory"); \ >- a0; \ >-}) >+enum sbi_ext_base_fid { >+ SBI_EXT_BASE_GET_SPEC_VERSION = 0, >+ SBI_EXT_BASE_GET_IMP_ID, >+ SBI_EXT_BASE_GET_IMP_VERSION, >+ SBI_EXT_BASE_PROBE_EXT, >+ SBI_EXT_BASE_GET_MVENDORID, >+ SBI_EXT_BASE_GET_MARCHID, >+ SBI_EXT_BASE_GET_MIMPID, >+}; > >-/* Lazy implementations until SBI is finalized */ -#define SBI_CALL_0(which) >SBI_CALL(which, 0, 0, 0, 0) -#define SBI_CALL_1(which, arg0) SBI_CALL(which, >arg0, 0, 0, 0) -#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, >arg1, 0, 0) -#define SBI_CALL_3(which, arg0, arg1, arg2) \ >- SBI_CALL(which, arg0, arg1, arg2, 0) >-#define SBI_CALL_4(which, arg0, arg1, arg2, arg3) \ >- SBI_CALL(which, arg0, arg1, arg2, arg3) >+#define SBI_SPEC_VERSION_DEFAULT 0x1 >+#define SBI_SPEC_VERSION_MAJOR_SHIFT 24 >+#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f >+#define SBI_SPEC_VERSION_MINOR_MASK 0xffffff > >-static inline void sbi_console_putchar(int ch) -{ >- SBI_CALL_1(SBI_EXT_0_1_CONSOLE_PUTCHAR, ch); >-} >+/* SBI return error codes */ >+#define SBI_SUCCESS 0 >+#define SBI_ERR_FAILURE -1 >+#define SBI_ERR_NOT_SUPPORTED -2 >+#define SBI_ERR_INVALID_PARAM -3 >+#define SBI_ERR_DENIED -4 >+#define SBI_ERR_INVALID_ADDRESS -5 > >-static inline int sbi_console_getchar(void) -{ >- return SBI_CALL_0(SBI_EXT_0_1_CONSOLE_GETCHAR); >-} >+extern unsigned long sbi_spec_version; >+struct sbiret { >+ long error; >+ long value; >+}; > >-static inline void sbi_set_timer(uint64_t stime_value) -{ -#if __riscv_xlen == 32 >- SBI_CALL_2(SBI_EXT_0_1_SET_TIMER, stime_value, stime_value >> >32); >-#else >- SBI_CALL_1(SBI_EXT_0_1_SET_TIMER, stime_value); >-#endif >-} >- >-static inline void sbi_shutdown(void) >-{ >- SBI_CALL_0(SBI_EXT_0_1_SHUTDOWN); >-} >- >-static inline void sbi_clear_ipi(void) >-{ >- SBI_CALL_0(SBI_EXT_0_1_CLEAR_IPI); >-} >- >-static inline void sbi_send_ipi(const unsigned long *hart_mask) -{ >- SBI_CALL_1(SBI_EXT_0_1_SEND_IPI, hart_mask); >-} >- >-static inline void sbi_remote_fence_i(const unsigned long *hart_mask) -{ >- SBI_CALL_1(SBI_EXT_0_1_REMOTE_FENCE_I, hart_mask); >-} >+struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, >+ unsigned long arg1, unsigned long arg2, >+ unsigned long arg3, unsigned long arg4, >+ unsigned long arg5); > >-static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask, >- unsigned long start, >- unsigned long size) >-{ >- SBI_CALL_3(SBI_EXT_0_1_REMOTE_SFENCE_VMA, hart_mask, start, >size); >-} >+void sbi_console_putchar(int ch); >+int sbi_console_getchar(void); >+void sbi_clear_ipi(void); >+void sbi_shutdown(void); >+void sbi_set_timer(uint64_t stime_value); void sbi_send_ipi(const >+unsigned long *hart_mask); void sbi_remote_fence_i(const unsigned long >+*hart_mask); void sbi_remote_sfence_vma(const unsigned long *hart_mask, >+ unsigned long start, >+ unsigned long size); >+void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, >+ unsigned long start, >+ unsigned long size, >+ unsigned long asid); > >-static inline void sbi_remote_sfence_vma_asid(const unsigned long >*hart_mask, >- unsigned long start, >- unsigned long size, >- unsigned long asid) >-{ >- SBI_CALL_4(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, hart_mask, >- start, size, asid); >-} >+int sbi_probe_extension(int ext); > > #endif >diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index >c9179a5..adadbf4 100644 >--- a/arch/riscv/lib/Makefile >+++ b/arch/riscv/lib/Makefile >@@ -16,6 +16,7 @@ obj-$(CONFIG_ANDES_PLIC) += andes_plic.o > obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o else > obj-$(CONFIG_RISCV_RDTIME) += rdtime.o >+obj-$(CONFIG_SBI) += sbi.o > obj-$(CONFIG_SBI_IPI) += sbi_ipi.o > endif > obj-y += interrupts.o >diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c new file mode 100644 >index 0000000..4b6a9e0 >--- /dev/null >+++ b/arch/riscv/lib/sbi.c >@@ -0,0 +1,181 @@ >+// SPDX-License-Identifier: GPL-2.0-only >+/* >+ * SBI initialilization and all extension implementation. >+ * >+ * Copyright (c) 2020 Western Digital Corporation or its affiliates. >+ * >+ * Taken from Linux arch/riscv/kernel/sbi.c */ >+ >+#include <common.h> >+#include <asm/encoding.h> >+#include <asm/sbi.h> >+ >+/* default SBI version is 0.1 */ >+unsigned long sbi_spec_version = SBI_SPEC_VERSION_DEFAULT; >+ >+struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, >+ unsigned long arg1, unsigned long arg2, >+ unsigned long arg3, unsigned long arg4, >+ unsigned long arg5) >+{ >+ struct sbiret ret; >+ >+ register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); >+ register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); >+ register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); >+ register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3); >+ register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4); >+ register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5); >+ register uintptr_t a6 asm ("a6") = (uintptr_t)(fid); >+ register uintptr_t a7 asm ("a7") = (uintptr_t)(ext); >+ asm volatile ("ecall" >+ : "+r" (a0), "+r" (a1) >+ : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7) >+ : "memory"); >+ ret.error = a0; >+ ret.value = a1; >+ >+ return ret; >+} >+ >+/** >+ * sbi_console_putchar() - Writes given character to the console device. >+ * @ch: The data to be written to the console. >+ * >+ * Return: None >+ */ >+void sbi_console_putchar(int ch) >+{ >+ sbi_ecall(SBI_EXT_0_1_CONSOLE_PUTCHAR, 0, ch, 0, 0, 0, 0, 0); } >+ >+/** >+ * sbi_console_getchar() - Reads a byte from console device. >+ * >+ * Returns the value read from console. >+ */ >+int sbi_console_getchar(void) >+{ >+ struct sbiret ret; >+ >+ ret = sbi_ecall(SBI_EXT_0_1_CONSOLE_GETCHAR, 0, 0, 0, 0, 0, 0, 0); >+ >+ return ret.error; >+} >+ >+/** >+ * sbi_clear_ipi() - Clear any pending IPIs for the calling hart. >+ * >+ * Return: None >+ */ >+void sbi_clear_ipi(void) >+{ >+ sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0); } >+ >+/** >+ * sbi_shutdown() - Remove all the harts from executing supervisor code. >+ * >+ * Return: None >+ */ >+void sbi_shutdown(void) >+{ >+ sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0); } >+ >+/** >+ * sbi_set_timer() - Program the timer for next timer event. >+ * @stime_value: The value after which next timer event should fire. >+ * >+ * Return: None >+ */ >+void sbi_set_timer(uint64_t stime_value) { #if __riscv_xlen == 32 >+ sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, >+ stime_value >> 32, 0, 0, 0, 0); >+#else >+ sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0); >+#endif } >+ >+/** >+ * sbi_send_ipi() - Send an IPI to any hart. >+ * @hart_mask: A cpu mask containing all the target harts. >+ * >+ * Return: None >+ */ >+void sbi_send_ipi(const unsigned long *hart_mask) { >+ sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask, >+ 0, 0, 0, 0, 0); >+} >+ >+/** >+ * sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts. >+ * @hart_mask: A cpu mask containing all the target harts. >+ * >+ * Return: None >+ */ >+void sbi_remote_fence_i(const unsigned long *hart_mask) { >+ sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0, (unsigned >long)hart_mask, >+ 0, 0, 0, 0, 0); >+} >+ >+/** >+ * sbi_remote_sfence_vma() - Execute SFENCE.VMA instructions on given >remote >+ * harts for the specified virtual address range. >+ * @hart_mask: A cpu mask containing all the target harts. >+ * @start: Start of the virtual address >+ * @size: Total size of the virtual address range. >+ * >+ * Return: None >+ */ >+void sbi_remote_sfence_vma(const unsigned long *hart_mask, >+ unsigned long start, >+ unsigned long size) >+{ >+ sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0, >+ (unsigned long)hart_mask, start, size, 0, 0, 0); } >+ >+/** >+ * sbi_remote_sfence_vma_asid() - Execute SFENCE.VMA instructions on >+given >+ * remote harts for a virtual address range belonging to a specific ASID. >+ * >+ * @hart_mask: A cpu mask containing all the target harts. >+ * @start: Start of the virtual address >+ * @size: Total size of the virtual address range. >+ * @asid: The value of address space identifier (ASID). >+ * >+ * Return: None >+ */ >+void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, >+ unsigned long start, >+ unsigned long size, >+ unsigned long asid) >+{ >+ sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0, >+ (unsigned long)hart_mask, start, size, asid, 0, 0); } >+ >+/** >+ * sbi_probe_extension() - Check if an SBI extension ID is supported or not. >+ * @extid: The extension ID to be probed. >+ * >+ * Return: Extension specific nonzero value f yes, -ENOTSUPP otherwise. >+ */ >+int sbi_probe_extension(int extid) >+{ >+ struct sbiret ret; >+ >+ ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, extid, >+ 0, 0, 0, 0, 0); >+ if (!ret.error) >+ if (ret.value) >+ return ret.value; >+ >+ return -ENOTSUPP; >+} Reviewed-by: Pragnesh Patel <pragnesh.patel at sifive.com> >-- >2.7.4
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 3338b78..09fff05 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -210,8 +210,13 @@ config NR_CPUS Stack memory is pre-allocated. U-Boot must therefore know the maximum number of CPUs that may be present. +config SBI + bool + default y if RISCV_SMODE || SPL_RISCV_SMODE + config SBI_IPI bool + depends on SBI default y if RISCV_SMODE || SPL_RISCV_SMODE depends on SMP diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 187ca58..fc8637c 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -11,91 +11,68 @@ #include <linux/types.h> -#define SBI_EXT_0_1_SET_TIMER 0x0 -#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1 -#define SBI_EXT_0_1_CONSOLE_GETCHAR 0x2 -#define SBI_EXT_0_1_CLEAR_IPI 0x3 -#define SBI_EXT_0_1_SEND_IPI 0x4 -#define SBI_EXT_0_1_REMOTE_FENCE_I 0x5 -#define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6 -#define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7 -#define SBI_EXT_0_1_SHUTDOWN 0x8 +enum sbi_ext_id { + SBI_EXT_0_1_SET_TIMER = 0x0, + SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1, + SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2, + SBI_EXT_0_1_CLEAR_IPI = 0x3, + SBI_EXT_0_1_SEND_IPI = 0x4, + SBI_EXT_0_1_REMOTE_FENCE_I = 0x5, + SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6, + SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7, + SBI_EXT_0_1_SHUTDOWN = 0x8, + SBI_EXT_BASE = 0x10, +}; -#define SBI_CALL(which, arg0, arg1, arg2, arg3) ({ \ - register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \ - register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); \ - register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); \ - register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3); \ - register uintptr_t a7 asm ("a7") = (uintptr_t)(which); \ - asm volatile ("ecall" \ - : "+r" (a0) \ - : "r" (a1), "r" (a2), "r" (a3), "r" (a7) \ - : "memory"); \ - a0; \ -}) +enum sbi_ext_base_fid { + SBI_EXT_BASE_GET_SPEC_VERSION = 0, + SBI_EXT_BASE_GET_IMP_ID, + SBI_EXT_BASE_GET_IMP_VERSION, + SBI_EXT_BASE_PROBE_EXT, + SBI_EXT_BASE_GET_MVENDORID, + SBI_EXT_BASE_GET_MARCHID, + SBI_EXT_BASE_GET_MIMPID, +}; -/* Lazy implementations until SBI is finalized */ -#define SBI_CALL_0(which) SBI_CALL(which, 0, 0, 0, 0) -#define SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0, 0) -#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0, 0) -#define SBI_CALL_3(which, arg0, arg1, arg2) \ - SBI_CALL(which, arg0, arg1, arg2, 0) -#define SBI_CALL_4(which, arg0, arg1, arg2, arg3) \ - SBI_CALL(which, arg0, arg1, arg2, arg3) +#define SBI_SPEC_VERSION_DEFAULT 0x1 +#define SBI_SPEC_VERSION_MAJOR_SHIFT 24 +#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f +#define SBI_SPEC_VERSION_MINOR_MASK 0xffffff -static inline void sbi_console_putchar(int ch) -{ - SBI_CALL_1(SBI_EXT_0_1_CONSOLE_PUTCHAR, ch); -} +/* SBI return error codes */ +#define SBI_SUCCESS 0 +#define SBI_ERR_FAILURE -1 +#define SBI_ERR_NOT_SUPPORTED -2 +#define SBI_ERR_INVALID_PARAM -3 +#define SBI_ERR_DENIED -4 +#define SBI_ERR_INVALID_ADDRESS -5 -static inline int sbi_console_getchar(void) -{ - return SBI_CALL_0(SBI_EXT_0_1_CONSOLE_GETCHAR); -} +extern unsigned long sbi_spec_version; +struct sbiret { + long error; + long value; +}; -static inline void sbi_set_timer(uint64_t stime_value) -{ -#if __riscv_xlen == 32 - SBI_CALL_2(SBI_EXT_0_1_SET_TIMER, stime_value, stime_value >> 32); -#else - SBI_CALL_1(SBI_EXT_0_1_SET_TIMER, stime_value); -#endif -} - -static inline void sbi_shutdown(void) -{ - SBI_CALL_0(SBI_EXT_0_1_SHUTDOWN); -} - -static inline void sbi_clear_ipi(void) -{ - SBI_CALL_0(SBI_EXT_0_1_CLEAR_IPI); -} - -static inline void sbi_send_ipi(const unsigned long *hart_mask) -{ - SBI_CALL_1(SBI_EXT_0_1_SEND_IPI, hart_mask); -} - -static inline void sbi_remote_fence_i(const unsigned long *hart_mask) -{ - SBI_CALL_1(SBI_EXT_0_1_REMOTE_FENCE_I, hart_mask); -} +struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, + unsigned long arg1, unsigned long arg2, + unsigned long arg3, unsigned long arg4, + unsigned long arg5); -static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask, - unsigned long start, - unsigned long size) -{ - SBI_CALL_3(SBI_EXT_0_1_REMOTE_SFENCE_VMA, hart_mask, start, size); -} +void sbi_console_putchar(int ch); +int sbi_console_getchar(void); +void sbi_clear_ipi(void); +void sbi_shutdown(void); +void sbi_set_timer(uint64_t stime_value); +void sbi_send_ipi(const unsigned long *hart_mask); +void sbi_remote_fence_i(const unsigned long *hart_mask); +void sbi_remote_sfence_vma(const unsigned long *hart_mask, + unsigned long start, + unsigned long size); +void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, + unsigned long start, + unsigned long size, + unsigned long asid); -static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, - unsigned long start, - unsigned long size, - unsigned long asid) -{ - SBI_CALL_4(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, hart_mask, - start, size, asid); -} +int sbi_probe_extension(int ext); #endif diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index c9179a5..adadbf4 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_ANDES_PLIC) += andes_plic.o obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o else obj-$(CONFIG_RISCV_RDTIME) += rdtime.o +obj-$(CONFIG_SBI) += sbi.o obj-$(CONFIG_SBI_IPI) += sbi_ipi.o endif obj-y += interrupts.o diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c new file mode 100644 index 0000000..4b6a9e0 --- /dev/null +++ b/arch/riscv/lib/sbi.c @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * SBI initialilization and all extension implementation. + * + * Copyright (c) 2020 Western Digital Corporation or its affiliates. + * + * Taken from Linux arch/riscv/kernel/sbi.c + */ + +#include <common.h> +#include <asm/encoding.h> +#include <asm/sbi.h> + +/* default SBI version is 0.1 */ +unsigned long sbi_spec_version = SBI_SPEC_VERSION_DEFAULT; + +struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, + unsigned long arg1, unsigned long arg2, + unsigned long arg3, unsigned long arg4, + unsigned long arg5) +{ + struct sbiret ret; + + register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); + register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); + register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); + register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3); + register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4); + register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5); + register uintptr_t a6 asm ("a6") = (uintptr_t)(fid); + register uintptr_t a7 asm ("a7") = (uintptr_t)(ext); + asm volatile ("ecall" + : "+r" (a0), "+r" (a1) + : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7) + : "memory"); + ret.error = a0; + ret.value = a1; + + return ret; +} + +/** + * sbi_console_putchar() - Writes given character to the console device. + * @ch: The data to be written to the console. + * + * Return: None + */ +void sbi_console_putchar(int ch) +{ + sbi_ecall(SBI_EXT_0_1_CONSOLE_PUTCHAR, 0, ch, 0, 0, 0, 0, 0); +} + +/** + * sbi_console_getchar() - Reads a byte from console device. + * + * Returns the value read from console. + */ +int sbi_console_getchar(void) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_0_1_CONSOLE_GETCHAR, 0, 0, 0, 0, 0, 0, 0); + + return ret.error; +} + +/** + * sbi_clear_ipi() - Clear any pending IPIs for the calling hart. + * + * Return: None + */ +void sbi_clear_ipi(void) +{ + sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0); +} + +/** + * sbi_shutdown() - Remove all the harts from executing supervisor code. + * + * Return: None + */ +void sbi_shutdown(void) +{ + sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0); +} + +/** + * sbi_set_timer() - Program the timer for next timer event. + * @stime_value: The value after which next timer event should fire. + * + * Return: None + */ +void sbi_set_timer(uint64_t stime_value) +{ +#if __riscv_xlen == 32 + sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, + stime_value >> 32, 0, 0, 0, 0); +#else + sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0); +#endif +} + +/** + * sbi_send_ipi() - Send an IPI to any hart. + * @hart_mask: A cpu mask containing all the target harts. + * + * Return: None + */ +void sbi_send_ipi(const unsigned long *hart_mask) +{ + sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask, + 0, 0, 0, 0, 0); +} + +/** + * sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts. + * @hart_mask: A cpu mask containing all the target harts. + * + * Return: None + */ +void sbi_remote_fence_i(const unsigned long *hart_mask) +{ + sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0, (unsigned long)hart_mask, + 0, 0, 0, 0, 0); +} + +/** + * sbi_remote_sfence_vma() - Execute SFENCE.VMA instructions on given remote + * harts for the specified virtual address range. + * @hart_mask: A cpu mask containing all the target harts. + * @start: Start of the virtual address + * @size: Total size of the virtual address range. + * + * Return: None + */ +void sbi_remote_sfence_vma(const unsigned long *hart_mask, + unsigned long start, + unsigned long size) +{ + sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0, + (unsigned long)hart_mask, start, size, 0, 0, 0); +} + +/** + * sbi_remote_sfence_vma_asid() - Execute SFENCE.VMA instructions on given + * remote harts for a virtual address range belonging to a specific ASID. + * + * @hart_mask: A cpu mask containing all the target harts. + * @start: Start of the virtual address + * @size: Total size of the virtual address range. + * @asid: The value of address space identifier (ASID). + * + * Return: None + */ +void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, + unsigned long start, + unsigned long size, + unsigned long asid) +{ + sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0, + (unsigned long)hart_mask, start, size, asid, 0, 0); +} + +/** + * sbi_probe_extension() - Check if an SBI extension ID is supported or not. + * @extid: The extension ID to be probed. + * + * Return: Extension specific nonzero value f yes, -ENOTSUPP otherwise. + */ +int sbi_probe_extension(int extid) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, extid, + 0, 0, 0, 0, 0); + if (!ret.error) + if (ret.value) + return ret.value; + + return -ENOTSUPP; +}
The SBI v0.2 introduces a base extension which is backward compatible with v0.1. Implement all helper functions and minimum required SBI calls from v0.2 for now. All other base extension function will be added later as per need. As v0.2 calling convention is backward compatible with v0.1, remove the v0.1 helper functions and just use v0.2 calling convention. Add a new Kconfig options CONFIG_SBI for the new SBI v0.2 codes, and let CONFIG_SBI_IPI depend on it. This commit is inspired from Linux kernel patch: https://patchwork.kernel.org/patch/11407363/ Signed-off-by: Bin Meng <bmeng.cn at gmail.com> --- arch/riscv/Kconfig | 5 ++ arch/riscv/include/asm/sbi.h | 135 +++++++++++++------------------- arch/riscv/lib/Makefile | 1 + arch/riscv/lib/sbi.c | 181 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 243 insertions(+), 79 deletions(-) create mode 100644 arch/riscv/lib/sbi.c