diff mbox series

[RFC,2/3] dt-bindings: gpio: Add binding documentation for Etron EJ168/EJ188/EJ198

Message ID 20201004162908.3216898-3-martin.blumenstingl@googlemail.com
State New
Headers show
Series GPIO support on the Etron EJ168/EJ188/EJ198 xHCI controllers | expand

Commit Message

Martin Blumenstingl Oct. 4, 2020, 4:29 p.m. UTC
Etron EJ168/EJ188/EJ198 are USB xHCI host controllers which embed a GPIO
controller.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 .../devicetree/bindings/gpio/etron,ej1x8.yaml | 48 +++++++++++++++++++
 1 file changed, 48 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpio/etron,ej1x8.yaml

Comments

Rob Herring (Arm) Oct. 6, 2020, 9:25 p.m. UTC | #1
On Sun, Oct 04, 2020 at 06:29:07PM +0200, Martin Blumenstingl wrote:
> Etron EJ168/EJ188/EJ198 are USB xHCI host controllers which embed a GPIO
> controller.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  .../devicetree/bindings/gpio/etron,ej1x8.yaml | 48 +++++++++++++++++++
>  1 file changed, 48 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/gpio/etron,ej1x8.yaml
> 
> diff --git a/Documentation/devicetree/bindings/gpio/etron,ej1x8.yaml b/Documentation/devicetree/bindings/gpio/etron,ej1x8.yaml
> new file mode 100644
> index 000000000000..fa554045bdb5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpio/etron,ej1x8.yaml
> @@ -0,0 +1,48 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/gpio/etron,ej1x8.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: GPIO controller embedded into the EJ168/EJ188/EJ198 xHCI controllers
> +
> +maintainers:
> +  - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> +
> +properties:
> +  compatible:
> +    enum:
> +      - pci1b6f,7023
> +      - pci1b6f,7052
> +
> +  reg:
> +    maxItems: 1
> +
> +  "#gpio-cells":
> +    const: 2
> +
> +  gpio-controller: true
> +
> +required:
> +  - compatible
> +  - reg
> +  - "#gpio-cells"
> +  - gpio-controller
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +      pcie {
> +        #address-cells = <3>;
> +        #size-cells = <2>;
> +
> +        gpio@0,0,0 {
> +          compatible = "pci1b6f,7023";
> +          reg = <0x0 0x0 0x0 0x0 0x1000>;
> +          gpio-controller;
> +          #gpio-cells = <2>;
> +        };

How would this look if you needed to describe the XHCI controller? 
That's another PCI function?

> +      };
> +
> +...
> -- 
> 2.28.0
>
Linus Walleij Oct. 7, 2020, 9:19 a.m. UTC | #2
On Sun, Oct 4, 2020 at 8:00 PM Martin Blumenstingl
<martin.blumenstingl@googlemail.com> wrote:

> +properties:
> +  compatible:
> +    enum:
> +      - pci1b6f,7023
> +      - pci1b6f,7052

I think it is better to let the PCI driver for the whole hardware in
drivers/usb/host/xhci-pci.c probe from the PCI configuration space
numbers, and then add a gpio_chip to xhci-pci.c.

Thanks!
Linus Walleij
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/gpio/etron,ej1x8.yaml b/Documentation/devicetree/bindings/gpio/etron,ej1x8.yaml
new file mode 100644
index 000000000000..fa554045bdb5
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/etron,ej1x8.yaml
@@ -0,0 +1,48 @@ 
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/etron,ej1x8.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: GPIO controller embedded into the EJ168/EJ188/EJ198 xHCI controllers
+
+maintainers:
+  - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+
+properties:
+  compatible:
+    enum:
+      - pci1b6f,7023
+      - pci1b6f,7052
+
+  reg:
+    maxItems: 1
+
+  "#gpio-cells":
+    const: 2
+
+  gpio-controller: true
+
+required:
+  - compatible
+  - reg
+  - "#gpio-cells"
+  - gpio-controller
+
+additionalProperties: false
+
+examples:
+  - |
+      pcie {
+        #address-cells = <3>;
+        #size-cells = <2>;
+
+        gpio@0,0,0 {
+          compatible = "pci1b6f,7023";
+          reg = <0x0 0x0 0x0 0x0 0x1000>;
+          gpio-controller;
+          #gpio-cells = <2>;
+        };
+      };
+
+...