| Message ID | 20201227130407.10991-1-wsa+renesas@sang-engineering.com |
|---|---|
| Headers | show |
| Series | v3u: add support for RAVB | expand |
On Sun, Dec 27, 2020 at 02:04:06PM +0100, Wolfram Sang wrote: > Retrieving a GPIO currently fails, so probing the whole driver fails > then. Remove them for now to get a working AVB device for testing. > > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> I just pushed out another version of this branch. There, in the depending gpio branch, a fix for the GPIO DTS addition has been applied, so 'reset-gpios' work now as expected. So, this patch has been dropped.
Hi Wolfram, On Sun, Dec 27, 2020 at 2:06 PM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > Document the compatible value for the RAVB block in the Renesas R-Car > V3U (R8A779A0) SoC. This variant has no stream buffer, so we only need > to add the new compatible. > > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Thanks for your patch! > --- a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml > +++ b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml > @@ -40,6 +40,7 @@ properties: > - renesas,etheravb-r8a77980 # R-Car V3H > - renesas,etheravb-r8a77990 # R-Car E3 > - renesas,etheravb-r8a77995 # R-Car D3 > + - renesas,etheravb-r8a779a0 # R-Car V3U > - const: renesas,etheravb-rcar-gen3 # R-Car Gen3 and RZ/G2 > > reg: true EtherAVB on R-Car V3U does have the Tx clock internal Delay Mode bit in the APSR register, so its compatible value should be added to the list of SoCs where tx-internal-delay-ps is required. With that fixed: Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> The various Counter Registers starting at offset 0x700 are limited to 16-bit values, like on R-Car Gen2, while they support 32-bit values on other R-Car Gen3 variants. The driver uses only the Transmit Retry Over Counter Register (TROCR), for statistics, so we can just ignore that difference. V3U also has a new block of registers related to UDP/IP support (offset 0x800 and up). I guess we can just ignore them too, for now. Gr{oetje,eeting}s, Geert
Hi Wolfram, On Sun, Dec 27, 2020 at 2:04 PM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > From: Tho Vu <tho.vu.wh@renesas.com> > > Define the generic parts of Ethernet-AVB device nodes. Only AVB0 was > tested because it was the only port with a PHY on current hardware. > > Signed-off-by: Tho Vu <tho.vu.wh@renesas.com> > [wsa: double checked & rebased] > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Thanks for your patch! > --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi > @@ -377,6 +377,276 @@ i2c6: i2c@e66e8000 { > status = "disabled"; > }; > > + avb0: ethernet@e6800000 { > + compatible = "renesas,etheravb-r8a779a0", > + "renesas,etheravb-rcar-gen3"; > + reg = <0 0xe6800000 0 0x800>; > + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "ch0", "ch1", "ch2", "ch3", > + "ch4", "ch5", "ch6", "ch7", > + "ch8", "ch9", "ch10", "ch11", > + "ch12", "ch13", "ch14", "ch15", > + "ch16", "ch17", "ch18", "ch19", > + "ch20", "ch21", "ch22", "ch23", > + "ch24"; > + clocks = <&cpg CPG_MOD 211>; > + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; > + resets = <&cpg 211>; > + phy-mode = "rgmii"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; $ make dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/net/renesas,etheravb.yaml arch/arm64/boot/dts/renesas/r8a779a0-falcon.dt.yaml: ethernet@e6800000: 'rx-internal-delay-ps' is a required property Similarly, "tx-internal-delay-ps" should be added to all instances, too. The rest looks good to me, so with the above fixed: Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On Sun, 27 Dec 2020 14:04:02 +0100, Wolfram Sang wrote: > Document the compatible value for the RAVB block in the Renesas R-Car > V3U (R8A779A0) SoC. This variant has no stream buffer, so we only need > to add the new compatible. > > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> > --- > Documentation/devicetree/bindings/net/renesas,etheravb.yaml | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh@kernel.org>