| Message ID | 20210203230057.3961239-1-suzuki.poulose@arm.com |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55 | expand |
Hi Suzuki, On Wed, Feb 03, 2021 at 11:00:57PM +0000, Suzuki K Poulose wrote: > The erratum 1024718 affects Cortex-A55 r0p0 to r2p0. However > we apply the work around for r0p0 - r1p0. Unfortunately this > won't be fixed for the future revisions for the CPU. Thus > extend the work around for all versions of A55, to cover > for r2p0 and any future revisions. > > Cc: stable@vger.kernel.org > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: James Morse <james.morse@arm.com> > Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> > --- > arch/arm64/kernel/cpufeature.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index e99eddec0a46..db400ca77427 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -1455,7 +1455,7 @@ static bool cpu_has_broken_dbm(void) > /* List of CPUs which have broken DBM support. */ > static const struct midr_range cpus[] = { > #ifdef CONFIG_ARM64_ERRATUM_1024718 > - MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0 > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), I think we have bigger problems with this erratum, since cpu_has_hw_af() doesn't taken this erratum into account at all, meaning that arch_faults_on_old_pte() will return the wrong value on any system with an A55. Please can you fix that along with this patch? You'll need to pay extra attention to the stuff I've queued on for-next/faultaround, where we will actually want arch_wants_old_prefaulted_pte() to return 'true' if any of the CPUs have DBM, since it's a pure performance thing. Cheers, Will
Hi Will On 2/4/21 9:54 AM, Will Deacon wrote: > Hi Suzuki, > > On Wed, Feb 03, 2021 at 11:00:57PM +0000, Suzuki K Poulose wrote: >> The erratum 1024718 affects Cortex-A55 r0p0 to r2p0. However >> we apply the work around for r0p0 - r1p0. Unfortunately this >> won't be fixed for the future revisions for the CPU. Thus >> extend the work around for all versions of A55, to cover >> for r2p0 and any future revisions. >> >> Cc: stable@vger.kernel.org >> Cc: Catalin Marinas <catalin.marinas@arm.com> >> Cc: Will Deacon <will@kernel.org> >> Cc: James Morse <james.morse@arm.com> >> Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> >> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> >> --- >> arch/arm64/kernel/cpufeature.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c >> index e99eddec0a46..db400ca77427 100644 >> --- a/arch/arm64/kernel/cpufeature.c >> +++ b/arch/arm64/kernel/cpufeature.c >> @@ -1455,7 +1455,7 @@ static bool cpu_has_broken_dbm(void) >> /* List of CPUs which have broken DBM support. */ >> static const struct midr_range cpus[] = { >> #ifdef CONFIG_ARM64_ERRATUM_1024718 >> - MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0 >> + MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), > > I think we have bigger problems with this erratum, since cpu_has_hw_af() > doesn't taken this erratum into account at all, meaning that > arch_faults_on_old_pte() will return the wrong value on any system with an > A55. Please note that we enable HW_AF on these CPUs even with this erratum as they are not affected. It is only the DBM that we selectively disable. Thus the AF flag checks are still valid (See __cpu_setup in arch/arm64/mm/proc.S). Or am I miss something ? Kind regards Suzuki > > Please can you fix that along with this patch? You'll need to pay extra > attention to the stuff I've queued on for-next/faultaround, where we will > actually want arch_wants_old_prefaulted_pte() to return 'true' if any of the > CPUs have DBM, since it's a pure performance thing. > > Cheers, > > Will >
On Fri, Feb 05, 2021 at 05:41:05PM +0000, Suzuki K Poulose wrote: > On 2/4/21 9:54 AM, Will Deacon wrote: > > On Wed, Feb 03, 2021 at 11:00:57PM +0000, Suzuki K Poulose wrote: > > > The erratum 1024718 affects Cortex-A55 r0p0 to r2p0. However > > > we apply the work around for r0p0 - r1p0. Unfortunately this > > > won't be fixed for the future revisions for the CPU. Thus > > > extend the work around for all versions of A55, to cover > > > for r2p0 and any future revisions. > > > > > > Cc: stable@vger.kernel.org > > > Cc: Catalin Marinas <catalin.marinas@arm.com> > > > Cc: Will Deacon <will@kernel.org> > > > Cc: James Morse <james.morse@arm.com> > > > Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> > > > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> > > > --- > > > arch/arm64/kernel/cpufeature.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > > > index e99eddec0a46..db400ca77427 100644 > > > --- a/arch/arm64/kernel/cpufeature.c > > > +++ b/arch/arm64/kernel/cpufeature.c > > > @@ -1455,7 +1455,7 @@ static bool cpu_has_broken_dbm(void) > > > /* List of CPUs which have broken DBM support. */ > > > static const struct midr_range cpus[] = { > > > #ifdef CONFIG_ARM64_ERRATUM_1024718 > > > - MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0 > > > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), > > > > I think we have bigger problems with this erratum, since cpu_has_hw_af() > > doesn't taken this erratum into account at all, meaning that > > arch_faults_on_old_pte() will return the wrong value on any system with an > > A55. > > Please note that we enable HW_AF on these CPUs even with this erratum as > they are not affected. It is only the DBM that we selectively disable. Thus > the AF flag checks are still valid (See __cpu_setup in arch/arm64/mm/proc.S). > Or am I miss something ? Thanks, you're completely right! I'll queue this one then, and update the Kconfig test at the same time. Will
On Wed, 3 Feb 2021 23:00:57 +0000, Suzuki K Poulose wrote: > The erratum 1024718 affects Cortex-A55 r0p0 to r2p0. However > we apply the work around for r0p0 - r1p0. Unfortunately this > won't be fixed for the future revisions for the CPU. Thus > extend the work around for all versions of A55, to cover > for r2p0 and any future revisions. Applied to arm64 (for-next/errata), thanks! [1/1] arm64: Extend workaround for erratum 1024718 to all versions of Cortex-A55 https://git.kernel.org/arm64/c/c0b15c25d251 Cheers, -- Will https://fixes.arm64.dev https://next.arm64.dev https://will.arm64.dev
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index e99eddec0a46..db400ca77427 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1455,7 +1455,7 @@ static bool cpu_has_broken_dbm(void) /* List of CPUs which have broken DBM support. */ static const struct midr_range cpus[] = { #ifdef CONFIG_ARM64_ERRATUM_1024718 - MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0 + MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), /* Kryo4xx Silver (rdpe => r1p0) */ MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), #endif
The erratum 1024718 affects Cortex-A55 r0p0 to r2p0. However we apply the work around for r0p0 - r1p0. Unfortunately this won't be fixed for the future revisions for the CPU. Thus extend the work around for all versions of A55, to cover for r2p0 and any future revisions. Cc: stable@vger.kernel.org Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: James Morse <james.morse@arm.com> Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- arch/arm64/kernel/cpufeature.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.24.1