| Message ID | 20210315211400.2805330-5-tobias@waldekranz.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | net: dsa: mv88e6xxx: Offload bridge port flags | expand |
On Mon, Mar 15, 2021 at 10:13:59PM +0100, Tobias Waldekranz wrote: > Allow a user to control automatic learning per port. > > Many chips have an explicit "LearningDisable"-bit that can be used for > this, but we opt for setting/clearing the PAV instead, as it works on > all devices at least as far back as 6083. > > Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com> > --- > drivers/net/dsa/mv88e6xxx/chip.c | 29 +++++++++++++++++++++-------- > drivers/net/dsa/mv88e6xxx/port.c | 21 +++++++++++++++++++++ > drivers/net/dsa/mv88e6xxx/port.h | 2 ++ > 3 files changed, 44 insertions(+), 8 deletions(-) > > diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c > index 01e4ac32d1e5..48e65f22641e 100644 > --- a/drivers/net/dsa/mv88e6xxx/chip.c > +++ b/drivers/net/dsa/mv88e6xxx/chip.c > @@ -2689,15 +2689,20 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) > return err; > } > > - /* Port Association Vector: when learning source addresses > - * of packets, add the address to the address database using > - * a port bitmap that has only the bit for this port set and > - * the other bits clear. > + /* Port Association Vector: disable automatic address learning > + * on all user ports since they start out in standalone > + * mode. When joining a bridge, learning will be configured to > + * match the bridge port settings. Enable learning on all > + * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the > + * learning process. > + * > + * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, > + * and RefreshLocked. I.e. setup standard automatic learning. > */ > - reg = 1 << port; > - /* Disable learning for CPU port */ > - if (dsa_is_cpu_port(ds, port)) > + if (dsa_is_user_port(ds, port)) > reg = 0; > + else > + reg = 1 << port; > > err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, > reg); Can this be refactored to use mv88e6xxx_port_set_assoc_vector too? > @@ -5426,7 +5431,7 @@ static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, > struct mv88e6xxx_chip *chip = ds->priv; > const struct mv88e6xxx_ops *ops; > > - if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD)) > + if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD)) > return -EINVAL; > > ops = chip->info->ops; > @@ -5449,6 +5454,14 @@ static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, > > mv88e6xxx_reg_lock(chip); > > + if (flags.mask & BR_LEARNING) { > + u16 pav = (flags.val & BR_LEARNING) ? (1 << port) : 0; > + > + err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); > + if (err) > + goto out; > + } > + > if (flags.mask & BR_FLOOD) { > bool unicast = !!(flags.val & BR_FLOOD); > > diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c > index 4561f289ab76..d716cd61b6c6 100644 > --- a/drivers/net/dsa/mv88e6xxx/port.c > +++ b/drivers/net/dsa/mv88e6xxx/port.c > @@ -1171,6 +1171,27 @@ int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) > 0x0001); > } > > +/* Offset 0x0B: Port Association Vector */ > + > +int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port, > + u16 pav) > +{ > + u16 reg, mask; > + int err; > + > + err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, > + ®); > + if (err) > + return err; > + > + mask = GENMASK(mv88e6xxx_num_ports(chip), 0); mv88e6xxx_num_ports(chip) - 1, maybe? > + reg &= ~mask; > + reg |= pav & mask; > + > + return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, > + reg); > +} > + > /* Offset 0x0C: Port ATU Control */ > > int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port) > diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h > index e6d0eaa6aa1d..635b6571a0e9 100644 > --- a/drivers/net/dsa/mv88e6xxx/port.h > +++ b/drivers/net/dsa/mv88e6xxx/port.h > @@ -361,6 +361,8 @@ int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, > size_t size); > int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); > int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); > +int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port, > + u16 pav); > int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, > u8 out); > int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, > -- > 2.25.1 >
On Tue, Mar 16, 2021 at 11:27, Vladimir Oltean <olteanv@gmail.com> wrote: > On Mon, Mar 15, 2021 at 10:13:59PM +0100, Tobias Waldekranz wrote: >> Allow a user to control automatic learning per port. >> >> Many chips have an explicit "LearningDisable"-bit that can be used for >> this, but we opt for setting/clearing the PAV instead, as it works on >> all devices at least as far back as 6083. >> >> Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com> >> --- >> drivers/net/dsa/mv88e6xxx/chip.c | 29 +++++++++++++++++++++-------- >> drivers/net/dsa/mv88e6xxx/port.c | 21 +++++++++++++++++++++ >> drivers/net/dsa/mv88e6xxx/port.h | 2 ++ >> 3 files changed, 44 insertions(+), 8 deletions(-) >> >> diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c >> index 01e4ac32d1e5..48e65f22641e 100644 >> --- a/drivers/net/dsa/mv88e6xxx/chip.c >> +++ b/drivers/net/dsa/mv88e6xxx/chip.c >> @@ -2689,15 +2689,20 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) >> return err; >> } >> >> - /* Port Association Vector: when learning source addresses >> - * of packets, add the address to the address database using >> - * a port bitmap that has only the bit for this port set and >> - * the other bits clear. >> + /* Port Association Vector: disable automatic address learning >> + * on all user ports since they start out in standalone >> + * mode. When joining a bridge, learning will be configured to >> + * match the bridge port settings. Enable learning on all >> + * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the >> + * learning process. >> + * >> + * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, >> + * and RefreshLocked. I.e. setup standard automatic learning. >> */ >> - reg = 1 << port; >> - /* Disable learning for CPU port */ >> - if (dsa_is_cpu_port(ds, port)) >> + if (dsa_is_user_port(ds, port)) >> reg = 0; >> + else >> + reg = 1 << port; >> >> err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, >> reg); > > Can this be refactored to use mv88e6xxx_port_set_assoc_vector too? That was my initial thought as well. But this write also ensures that the other learning related settings are in a known state. So I settled for leaving the raw write, but I made sure to document that we depend on the values of the other flags (second paragraph). >> @@ -5426,7 +5431,7 @@ static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, >> struct mv88e6xxx_chip *chip = ds->priv; >> const struct mv88e6xxx_ops *ops; >> >> - if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD)) >> + if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD)) >> return -EINVAL; >> >> ops = chip->info->ops; >> @@ -5449,6 +5454,14 @@ static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, >> >> mv88e6xxx_reg_lock(chip); >> >> + if (flags.mask & BR_LEARNING) { >> + u16 pav = (flags.val & BR_LEARNING) ? (1 << port) : 0; >> + >> + err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); >> + if (err) >> + goto out; >> + } >> + >> if (flags.mask & BR_FLOOD) { >> bool unicast = !!(flags.val & BR_FLOOD); >> >> diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c >> index 4561f289ab76..d716cd61b6c6 100644 >> --- a/drivers/net/dsa/mv88e6xxx/port.c >> +++ b/drivers/net/dsa/mv88e6xxx/port.c >> @@ -1171,6 +1171,27 @@ int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) >> 0x0001); >> } >> >> +/* Offset 0x0B: Port Association Vector */ >> + >> +int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port, >> + u16 pav) >> +{ >> + u16 reg, mask; >> + int err; >> + >> + err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, >> + ®); >> + if (err) >> + return err; >> + >> + mask = GENMASK(mv88e6xxx_num_ports(chip), 0); > > mv88e6xxx_num_ports(chip) - 1, maybe? Ahh thanks. This made me think that there should be a helper for this; turns out Vivien added mv88e6xxx_port_mask four years ago :) >> + reg &= ~mask; >> + reg |= pav & mask; >> + >> + return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, >> + reg); >> +} >> + >> /* Offset 0x0C: Port ATU Control */ >> >> int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port) >> diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h >> index e6d0eaa6aa1d..635b6571a0e9 100644 >> --- a/drivers/net/dsa/mv88e6xxx/port.h >> +++ b/drivers/net/dsa/mv88e6xxx/port.h >> @@ -361,6 +361,8 @@ int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, >> size_t size); >> int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); >> int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); >> +int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port, >> + u16 pav); >> int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, >> u8 out); >> int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, >> -- >> 2.25.1 >>
On Mon, Mar 15, 2021 at 10:13:59PM +0100, Tobias Waldekranz wrote: > + if (flags.mask & BR_LEARNING) { > + u16 pav = (flags.val & BR_LEARNING) ? (1 << port) : 0; > + > + err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); > + if (err) > + goto out; > + } > + If flags.val & BR_LEARNING is off, could you please call mv88e6xxx_port_fast_age too? This ensures that existing ATU entries that were automatically learned are purged.
On Wed, Mar 17, 2021 at 16:12, Vladimir Oltean <olteanv@gmail.com> wrote: > On Mon, Mar 15, 2021 at 10:13:59PM +0100, Tobias Waldekranz wrote: >> + if (flags.mask & BR_LEARNING) { >> + u16 pav = (flags.val & BR_LEARNING) ? (1 << port) : 0; >> + >> + err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); >> + if (err) >> + goto out; >> + } >> + > > If flags.val & BR_LEARNING is off, could you please call > mv88e6xxx_port_fast_age too? This ensures that existing ATU entries that > were automatically learned are purged. This opened up another can of worms. It turns out that the hardware is incapable of fast aging a LAG. I can see two workarounds. Both are awful in their own special ways: 1. Iterate over all entries of all FIDs in the ATU, removing all matching dynamic entries. This will accomplish the same thing, but it is a very expensive operation, and having that in the control path of STP does not feel quite right. 2. Flushing all dynamic entries in the entire ATU. Fast, but obviously results in a period of lots of flooded packets. Any opinion on which approach you think would hurt less? Or, even better, if there is a third way that I have missed. For this series I am leaning towards making mv88e6xxx_port_fast_age a no-op for LAG ports. We could then come back to this problem when we add other LAG-related FDB operations like static FDB entries. Acceptable?
On Wed, Mar 17, 2021 at 07:45:46PM +0100, Tobias Waldekranz wrote: > On Wed, Mar 17, 2021 at 16:12, Vladimir Oltean <olteanv@gmail.com> wrote: > > On Mon, Mar 15, 2021 at 10:13:59PM +0100, Tobias Waldekranz wrote: > >> + if (flags.mask & BR_LEARNING) { > >> + u16 pav = (flags.val & BR_LEARNING) ? (1 << port) : 0; > >> + > >> + err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); > >> + if (err) > >> + goto out; > >> + } > >> + > > > > If flags.val & BR_LEARNING is off, could you please call > > mv88e6xxx_port_fast_age too? This ensures that existing ATU entries that > > were automatically learned are purged. > > This opened up another can of worms. > > It turns out that the hardware is incapable of fast aging a LAG. You sound pretty definitive about it, do you know why? > I can see two workarounds. Both are awful in their own special ways: > > 1. Iterate over all entries of all FIDs in the ATU, removing all > matching dynamic entries. This will accomplish the same thing, but it > is a very expensive operation, and having that in the control path of > STP does not feel quite right. When does it ever feel right? :) I think of it like a faster 'bridge fdb' command (since 'bridge fdb' traverses the ATU super inefficiently, it dumps the whole table for each port). On my system with 24 mv88e6xxx ports, 'time bridge fdb' takes around 34 seconds. So that means a 'slow age' will take around 1.4 seconds for a single LAG. On the other hand, on my system with 7 sja1105 ports, I have no choice but to do slow ageing - the hardware simply doesn't have the concept of 'fast ageing'. There, 'time bridge fdb' returns 1.781s, so I expect a slow age would take around 0.25 seconds. Of course I'm not happy about it, but I think I'll bite the bullet. > 2. Flushing all dynamic entries in the entire ATU. Fast, but obviously > results in a period of lots of flooded packets. This one seems like an overreaction to me. Would that even solve the problem? Couly you destroy and re-create the trunk? > Any opinion on which approach you think would hurt less? Or, even > better, if there is a third way that I have missed. > > For this series I am leaning towards making mv88e6xxx_port_fast_age a > no-op for LAG ports. We could then come back to this problem when we add > other LAG-related FDB operations like static FDB entries. Acceptable? Yeah, I guess that's fair.
On Wed, Mar 17, 2021 at 21:29, Vladimir Oltean <olteanv@gmail.com> wrote: > On Wed, Mar 17, 2021 at 07:45:46PM +0100, Tobias Waldekranz wrote: >> On Wed, Mar 17, 2021 at 16:12, Vladimir Oltean <olteanv@gmail.com> wrote: >> > On Mon, Mar 15, 2021 at 10:13:59PM +0100, Tobias Waldekranz wrote: >> >> + if (flags.mask & BR_LEARNING) { >> >> + u16 pav = (flags.val & BR_LEARNING) ? (1 << port) : 0; >> >> + >> >> + err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); >> >> + if (err) >> >> + goto out; >> >> + } >> >> + >> > >> > If flags.val & BR_LEARNING is off, could you please call >> > mv88e6xxx_port_fast_age too? This ensures that existing ATU entries that >> > were automatically learned are purged. >> >> This opened up another can of worms. >> >> It turns out that the hardware is incapable of fast aging a LAG. > > You sound pretty definitive about it, do you know why? The big note saying "Entries associated with a LAG cannot be moved or removed using these commands" was the first clue :) This is pure speculation on my part. In the first iterations of this family of devices (before it was bought by Marvell), cross-chip LAGs where not supported. You would simply set multiple bits in the PAV for all LAG members to associate stations with the LAG. In that scenario you can fast-age a LAG by fast-aging each individual port. Later, cross-chip LAGs where added, and enough support was bolted on to the ATU to support automatic learning, but not enough to support fast-aging. >> I can see two workarounds. Both are awful in their own special ways: >> >> 1. Iterate over all entries of all FIDs in the ATU, removing all >> matching dynamic entries. This will accomplish the same thing, but it >> is a very expensive operation, and having that in the control path of >> STP does not feel quite right. > > When does it ever feel right? :) > > I think of it like a faster 'bridge fdb' command (since 'bridge fdb' > traverses the ATU super inefficiently, it dumps the whole table for each > port). > > On my system with 24 mv88e6xxx ports, 'time bridge fdb' takes around 34 > seconds. So that means a 'slow age' will take around 1.4 seconds for a > single LAG. Well, it also scales linearly with the number of active entries in the ATU. Here are some times for "bridge fdb" on my system with a single 6390X: Entries Time 1 0.17s 10 0.48s 100 3.20s 200 6.24s 1000 31.82s (I used trafgen to generate broadcasts with random SAs) Then you have to consider that you are not simply walking the ATU, you also have to write back entries whenever you come across one attached to the LAG you are fast-aging. > On the other hand, on my system with 7 sja1105 ports, I have no choice > but to do slow ageing - the hardware simply doesn't have the concept of > 'fast ageing'. There, 'time bridge fdb' returns 1.781s, so I expect a > slow age would take around 0.25 seconds. Of course I'm not happy about > it, but I think I'll bite the bullet. > >> 2. Flushing all dynamic entries in the entire ATU. Fast, but obviously >> results in a period of lots of flooded packets. > > This one seems like an overreaction to me. Would that even solve the > problem? Couly you destroy and re-create the trunk? It would make sure that no entries lingered on the port in question, absolutely. Unfortunately that would also be true for all other ports :) Adding/removing a LAG in hardware has no connection to ATU entries unfortunately. >> Any opinion on which approach you think would hurt less? Or, even >> better, if there is a third way that I have missed. >> >> For this series I am leaning towards making mv88e6xxx_port_fast_age a >> no-op for LAG ports. We could then come back to this problem when we add >> other LAG-related FDB operations like static FDB entries. Acceptable? > > Yeah, I guess that's fair. Great. I will try to put together a v2 tomorrow.
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index 01e4ac32d1e5..48e65f22641e 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -2689,15 +2689,20 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) return err; } - /* Port Association Vector: when learning source addresses - * of packets, add the address to the address database using - * a port bitmap that has only the bit for this port set and - * the other bits clear. + /* Port Association Vector: disable automatic address learning + * on all user ports since they start out in standalone + * mode. When joining a bridge, learning will be configured to + * match the bridge port settings. Enable learning on all + * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the + * learning process. + * + * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, + * and RefreshLocked. I.e. setup standard automatic learning. */ - reg = 1 << port; - /* Disable learning for CPU port */ - if (dsa_is_cpu_port(ds, port)) + if (dsa_is_user_port(ds, port)) reg = 0; + else + reg = 1 << port; err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, reg); @@ -5426,7 +5431,7 @@ static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, struct mv88e6xxx_chip *chip = ds->priv; const struct mv88e6xxx_ops *ops; - if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD)) + if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD)) return -EINVAL; ops = chip->info->ops; @@ -5449,6 +5454,14 @@ static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, mv88e6xxx_reg_lock(chip); + if (flags.mask & BR_LEARNING) { + u16 pav = (flags.val & BR_LEARNING) ? (1 << port) : 0; + + err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); + if (err) + goto out; + } + if (flags.mask & BR_FLOOD) { bool unicast = !!(flags.val & BR_FLOOD); diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c index 4561f289ab76..d716cd61b6c6 100644 --- a/drivers/net/dsa/mv88e6xxx/port.c +++ b/drivers/net/dsa/mv88e6xxx/port.c @@ -1171,6 +1171,27 @@ int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) 0x0001); } +/* Offset 0x0B: Port Association Vector */ + +int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port, + u16 pav) +{ + u16 reg, mask; + int err; + + err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, + ®); + if (err) + return err; + + mask = GENMASK(mv88e6xxx_num_ports(chip), 0); + reg &= ~mask; + reg |= pav & mask; + + return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, + reg); +} + /* Offset 0x0C: Port ATU Control */ int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port) diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h index e6d0eaa6aa1d..635b6571a0e9 100644 --- a/drivers/net/dsa/mv88e6xxx/port.h +++ b/drivers/net/dsa/mv88e6xxx/port.h @@ -361,6 +361,8 @@ int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, size_t size); int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); +int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port, + u16 pav); int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, u8 out); int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
Allow a user to control automatic learning per port. Many chips have an explicit "LearningDisable"-bit that can be used for this, but we opt for setting/clearing the PAV instead, as it works on all devices at least as far back as 6083. Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com> --- drivers/net/dsa/mv88e6xxx/chip.c | 29 +++++++++++++++++++++-------- drivers/net/dsa/mv88e6xxx/port.c | 21 +++++++++++++++++++++ drivers/net/dsa/mv88e6xxx/port.h | 2 ++ 3 files changed, 44 insertions(+), 8 deletions(-)