[net-next,5/5] arm64: dts: zynqmp: Add ZCU104 based TSN endpoint

Combination of Xilinx ZCU104 with Avnet AES-FMC-NETW1-G and TSN endpoint
Ethernet MAC implemented in FPGA.

Signed-off-by: Gerhard Engleder <gerhard@engleder-embedded.com>
---
 arch/arm64/boot/dts/xilinx/Makefile         |  1 +
 arch/arm64/boot/dts/xilinx/zynqmp-tsnep.dts | 50 +++++++++++++++++++++
 2 files changed, 51 insertions(+)
 create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-tsnep.dts

On Tue, Jul 27, 2021 at 1:41 AM Rob Herring <robh+dt@kernel.org> wrote:
> > +       compatible = "engleder,zynqmp-tsnep", "xlnx,zynqmp-zcu104-revC",
> > +                    "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
>
> I don't think this will pass schema validation.

You are right. I did rerun the validation and now I see the error.

> In general, do we need a new top-level compatible for every possible
> FPGA image? Shouldn't this be an overlay?

All the devices I have dealt with so far had just a single FPGA image.
There were no dynamic selection of the FPGA image or partial
reconfiguration of the FPGA. So the FPGA image could be seen as part
of the schematics. In this case the FPGA image stuff shall be in the
device tree of the device. For me the question is: Does this combination
of evaluation boards with its own FPGA image form a new device?

The evaluation platform is based on ZCU104. The difference is not
only the FPGA image. Also a FMC extension card with Ethernet PHYs is
needed. So also the physical hardware is different.

On Tue, Jul 27, 2021 at 2:11 PM Gerhard Engleder
<gerhard@engleder-embedded.com> wrote:
>
> On Tue, Jul 27, 2021 at 1:41 AM Rob Herring <robh+dt@kernel.org> wrote:
> > > +       compatible = "engleder,zynqmp-tsnep", "xlnx,zynqmp-zcu104-revC",
> > > +                    "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
> >
> > I don't think this will pass schema validation.
>
> You are right. I did rerun the validation and now I see the error.
>
> > In general, do we need a new top-level compatible for every possible
> > FPGA image? Shouldn't this be an overlay?
>
> All the devices I have dealt with so far had just a single FPGA image.
> There were no dynamic selection of the FPGA image or partial
> reconfiguration of the FPGA. So the FPGA image could be seen as part
> of the schematics. In this case the FPGA image stuff shall be in the
> device tree of the device. For me the question is: Does this combination
> of evaluation boards with its own FPGA image form a new device?
>
> The evaluation platform is based on ZCU104. The difference is not
> only the FPGA image. Also a FMC extension card with Ethernet PHYs is
> needed. So also the physical hardware is different.

Okay, that's enough of a reason for another compatible. You'll have to
update the schema.

> From my point of view it is a separate hardware platform with its own
> device tree. It's purpose is to show two tsnep Ethernet controllers in
> action. So far it worked good for me to see the FPGA image as part of
> the schematics like the list of devices on the SPI bus. No special handling
> just because an FPGA is used, which in the end is not relevant for the
> software because software cannot and need not differentiate between
> normal hardware and FPGA based hardware.
>
> But I also understand the view of just another FPGA image for an existing
> hardware.
>
> My goal is to get all necessary stuff, which is needed to run the evaluation
> platform, into mainline. I must confess, I have not thought about using an
> overlay. Is it right that overlays are not part of the kernel tree?

There's some work in progress on it. We can build and apply overlays
at build time now, but we haven't added any overlays under /arch.

Given the overall h/w is different, it doesn't seem like overlay will
buy you anything here.

Rob

On Tue, Jul 27, 2021 at 10:18 PM Rob Herring <robh+dt@kernel.org> wrote:
> > The evaluation platform is based on ZCU104. The difference is not
> > only the FPGA image. Also a FMC extension card with Ethernet PHYs is
> > needed. So also the physical hardware is different.
>
> Okay, that's enough of a reason for another compatible. You'll have to
> update the schema.

Ok, I will update Documentation/devicetree/bindings/arm/xilinx.yaml.

Gerhard

On 7/27/21 10:23 PM, Gerhard Engleder wrote:
> On Tue, Jul 27, 2021 at 10:18 PM Rob Herring <robh+dt@kernel.org> wrote:
>>> The evaluation platform is based on ZCU104. The difference is not
>>> only the FPGA image. Also a FMC extension card with Ethernet PHYs is
>>> needed. So also the physical hardware is different.
>>
>> Okay, that's enough of a reason for another compatible. You'll have to
>> update the schema.
> 
> Ok, I will update Documentation/devicetree/bindings/arm/xilinx.yaml.

In past we said that we won't be accepting any FPGA description in
u-boot/linux projects. I don't think anything has changed from that time
and I don't want to end up in situation that we will have a lot of
configurations which none else can try and use.
Also based on your description where you use evaluation board with FMC
card it is far from any product and looks like demonstration configuration.
You can add the same fragment to dt binding example which should be
enough for everybody to understand how your IP should be described.

Thanks,
Michal

On Wed, Jul 28, 2021 at 12:59 PM Michal Simek <michal.simek@xilinx.com> wrote:
> >> In past we said that we won't be accepting any FPGA description in
> >> u-boot/linux projects. I don't think anything has changed from that time
> >> and I don't want to end up in situation that we will have a lot of
> >> configurations which none else can try and use.
> You have to share to customers bitstream. Likely also boot.bin with
> PS/PL configuration and other files in it. That's why it will be quite
> simple to also share them full DT or DT overlay just for your IP in the
> same image.

That's possible of course.

> Till now I didn't hear any strong argument why this should be accepted.

I want to try a new argument:

For new bindings a schema is used. The goal is to ensure that the binding
schema and the driver fit together. The validation chain is the following:
1) The binding schema is used to validate the device tree.
2) The device tree is used to "validate" the driver by booting.

So the kernel tree needs to contain a device tree which uses the binding
to build up the complete validation chain. The validation of the driver against
the binding is not possible without a device tree. The only option would be
to compare driver and binding manually, which is error prone.

If device trees with FPGA descriptions are not allowed in the kernel tree, then
the kernel tree will never contain complete validation chains für FPGA based
IPs. The validation of bindings for FPGA based IPs has to rely on device trees
which are maintained out of tree. It is possible/likely that schema
validation is
not done out of tree. As a result it is more likely that binding and
driver do not
fit together for FPGA based IPs. In the end the quality of the support for FPGA
based IPs would suffer.

I suggest allowing a single device tree with FPGA descriptions for a binding
of FPGA based IPs. This will build up the complete validation chain in the
kernel tree and ensures that binding and driver fit together. This single device
tree would form the reference platform for the FPGA based IP.

Gerhard