| Message ID | 1629983731-10595-1-git-send-email-rajpat@codeaurora.org |
|---|---|
| Headers | show |
| Series | Add QSPI and QUPv3 DT nodes for SC7280 SoC | expand |
Can you please Cc folks who have reviewed prior series when you send again? Quoting Rajesh Patil (2021-08-26 06:15:25) > From: Roja Rani Yarubandi <rojay@codeaurora.org> > > Add QSPI DT node and qspi_opp_table for SC7280 SoC. Might be worth adding here that we put the opp table in / because SPI nodes assume any child node is a spi device and so we can't put the table underneath the spi controller. > > Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> > Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 62 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 62 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 53a21d0..f8dd5ff 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -1318,6 +1337,24 @@ > }; > }; > > + qspi: spi@88dc000 { > + compatible = "qcom,qspi-v1"; > + reg = <0 0x088dc000 0 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, > + <&gcc GCC_QSPI_CORE_CLK>; > + clock-names = "iface", "core"; > + interconnects = <&gem_noc MASTER_APPSS_PROC 0 > + &cnoc2 SLAVE_QSPI_0 0>; > + interconnect-names = "qspi-config"; > + power-domains = <&rpmhpd SC7280_CX>; > + operating-points-v2 = <&qspi_opp_table>; > + status = "disabled"; > + Nitpick: Drop newline above. > + }; > + > dc_noc: interconnect@90e0000 { > reg = <0 0x090e0000 0 0x5080>; > compatible = "qcom,sc7280-dc-noc";
On Thu, Aug 26, 2021 at 06:45:27PM +0530, Rajesh Patil wrote: > From: Roja Rani Yarubandi <rojay@codeaurora.org> > > Add QUPv3 wrapper_0 DT nodes for SC7280 SoC. > > Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> > Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 724 ++++++++++++++++++++++++++++++++++- > 1 file changed, 722 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index f8dd5ff..da3cf19 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -434,6 +434,25 @@ > }; > }; > > + qup_opp_table: qup-opp-table { > + compatible = "operating-points-v2"; > + > + opp-75000000 { > + opp-hz = /bits/ 64 <75000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-100000000 { > + opp-hz = /bits/ 64 <100000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-128000000 { > + opp-hz = /bits/ 64 <128000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + > soc: soc@0 { > #address-cells = <2>; > #size-cells = <2>; > @@ -536,24 +555,425 @@ > qupv3_id_0: geniqup@9c0000 { > compatible = "qcom,geni-se-qup"; > reg = <0 0x009c0000 0 0x2000>; > - clock-names = "m-ahb", "s-ahb"; > clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, > <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; > + clock-names = "m-ahb", "s-ahb"; > #address-cells = <2>; > #size-cells = <2>; > ranges; > + iommus = <&apps_smmu 0x123 0x0>; > status = "disabled"; > > + i2c0: i2c@980000 { > + compatible = "qcom,geni-i2c"; > + reg = <0 0x00980000 0 0x4000>; > + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; > + clock-names = "se"; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c0_data_clk>; > + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, > + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names = "qup-core", "qup-config", > + "qup-memory"; > + status = "disabled"; > + }; > + > + spi0: spi@980000 { > + compatible = "qcom,geni-spi"; > + reg = <0 0x00980000 0 0x4000>; > + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; > + clock-names = "se"; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>, <&qup_spi0_cs_gpio>; as per the discussion on v5 (https://patchwork.kernel.org/project/linux-arm-msm/patch/1628754078-29779-4-git-send-email-rajpat@codeaurora.org/) I remain unconvinced that configuring the CS pin both as CS and GPIO is a good idea. If you think it is necessary in this case (maybe some kind of quirk?) please provide a rationale.
On 2021-08-26 23:32, Stephen Boyd wrote: > Can you please Cc folks who have reviewed prior series when you send > again? > > Quoting Rajesh Patil (2021-08-26 06:15:25) >> From: Roja Rani Yarubandi <rojay@codeaurora.org> >> >> Add QSPI DT node and qspi_opp_table for SC7280 SoC. > > Might be worth adding here that we put the opp table in / because SPI > nodes assume any child node is a spi device and so we can't put the > table underneath the spi controller. > Okay >> >> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> >> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> >> --- >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 62 >> ++++++++++++++++++++++++++++++++++++ >> 1 file changed, 62 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 53a21d0..f8dd5ff 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -1318,6 +1337,24 @@ >> }; >> }; >> >> + qspi: spi@88dc000 { >> + compatible = "qcom,qspi-v1"; >> + reg = <0 0x088dc000 0 0x1000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, >> + <&gcc GCC_QSPI_CORE_CLK>; >> + clock-names = "iface", "core"; >> + interconnects = <&gem_noc MASTER_APPSS_PROC 0 >> + &cnoc2 SLAVE_QSPI_0 0>; >> + interconnect-names = "qspi-config"; >> + power-domains = <&rpmhpd SC7280_CX>; >> + operating-points-v2 = <&qspi_opp_table>; >> + status = "disabled"; >> + > > Nitpick: Drop newline above. Okay > >> + }; >> + >> dc_noc: interconnect@90e0000 { >> reg = <0 0x090e0000 0 0x5080>; >> compatible = "qcom,sc7280-dc-noc";
On 2021-08-26 23:42, Stephen Boyd wrote: > Quoting Rajesh Patil (2021-08-26 06:15:31) >> Add aliases for i2c and spi for sc7280 soc. >> >> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> >> --- >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 32 >> ++++++++++++++++++++++++++++++++ >> 1 file changed, 32 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 32f411f..c659f61 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -28,6 +28,38 @@ >> aliases { >> mmc1 = &sdhc_1; >> mmc2 = &sdhc_2; >> + i2c0 = &i2c0; >> + i2c1 = &i2c1; >> + i2c2 = &i2c2; >> + i2c3 = &i2c3; >> + i2c4 = &i2c4; >> + i2c5 = &i2c5; >> + i2c6 = &i2c6; >> + i2c7 = &i2c7; >> + i2c8 = &i2c8; >> + i2c9 = &i2c9; >> + i2c10 = &i2c10; >> + i2c11 = &i2c11; >> + i2c12 = &i2c12; >> + i2c13 = &i2c13; >> + i2c14 = &i2c14; >> + i2c15 = &i2c15; > > Please alphabet sort this on alias name. "i" before "m" Okay i will change according to alphabet order > >> + spi0 = &spi0; >> + spi1 = &spi1; >> + spi2 = &spi2; >> + spi3 = &spi3; >> + spi4 = &spi4; >> + spi5 = &spi5; >> + spi6 = &spi6; >> + spi7 = &spi7; >> + spi8 = &spi8; >> + spi9 = &spi9; >> + spi10 = &spi10; >> + spi11 = &spi11; >> + spi12 = &spi12; >> + spi13 = &spi13; >> + spi14 = &spi14; >> + spi15 = &spi15; >> }; >> >> clocks { >> --
Changes in V6: - As per Matthias' comments, 1. Squashed "Update QUPv3 UART5 DT node" and "Configure debug uart for sc7280-idp" 2. Moved qup_opp_table from /soc to / 3. Changed convention "clocks" followed by "clock-names" - As per Doug comments, added aliases for i2c and spi Changes in V5: - As per Matthias' comments, I've split the patches as below: 1. Add QSPI node 2. Configure SPI-NOR FLASH for sc7280-idp 3. Add QUPv3 wrapper_0 nodes 4. Update QUPv3 UART5 DT node 5. Configure debug uart for sc7280-idp 6. Configure uart7 to support bluetooth on sc7280-idp 7. Add QUPv3 wrapper_1 nodes Changes in V4: - As per Stephen's comment updated spi-max-frequency to 37.5MHz, moved qspi_opp_table from /soc to / (root). - As per Bjorn's comment, added QUP Wrapper_0 nodes as separate patch and debug-uart node as separate patch. - Dropped interconnect votes for wrapper_0 and wrapper_1 node - Corrected QUP Wrapper_1 SE node's pin control functions like below QUP Wrapper_0: SE0-SE7 uses qup00 - qup07 pin-cntrl functions. QUP Wrapper_1: SE0-SE7 uses qup10 - qup17 pin-cntrl functions. Changes in V3: - Broken the huge V2 patch into 3 smaller patches. 1. QSPI DT nodes 2. QUP wrapper_0 DT nodes 3. QUP wrapper_1 DT nodes Changes in V2: - As per Doug's comments removed pinmux/pinconf subnodes. - As per Doug's comments split of SPI, UART nodes has been done. - Moved QSPI node before aps_smmu as per the order. Rajesh Patil (3): arm64: dts: sc7280: Configure SPI-NOR FLASH for sc7280-idp arm64: dts: sc7280: Configure uart7 to support bluetooth on sc7280-idp arm64: dts: sc7280: Add aliases for I2C and SPI Roja Rani Yarubandi (4): arm64: dts: sc7280: Add QSPI node arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes arm64: dts: sc7280: Update QUPv3 UART5 DT node arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 129 +- arch/arm64/boot/dts/qcom/sc7280.dtsi | 3197 ++++++++++++++++++++++-------- 2 files changed, 2511 insertions(+), 815 deletions(-)