| Message ID | 20210828131814.29589-16-konrad.dybcio@somainline.org |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,01/18] dt-bindings: arm: cpus: Add Kryo 560 CPUs | expand |
On Sat 28 Aug 08:18 CDT 2021, Konrad Dybcio wrote: > This is required for us to be able to access the associated registers, which > are (on at least some devices) gated by default. > Please either merge this with the patch that introduces the SMMU (which I presume causes this "issue") or introduce the SMMU earlier in the series. Regards, Bjorn > Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> > --- > arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi > index a3a1f0e63ace..95e69d9f8657 100644 > --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi > @@ -584,6 +584,7 @@ usb_1_dwc3: dwc3@a600000 { > compatible = "snps,dwc3"; > reg = <0 0x0a600000 0 0xcd00>; > interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; > + iommus = <&apps_smmu 0x540 0x0>; > snps,dis_u2_susphy_quirk; > snps,dis_enblslpm_quirk; > snps,has-lpm-erratum; > -- > 2.33.0 >
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index a3a1f0e63ace..95e69d9f8657 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -584,6 +584,7 @@ usb_1_dwc3: dwc3@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x540 0x0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; snps,has-lpm-erratum;
This is required for us to be able to access the associated registers, which are (on at least some devices) gated by default. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 + 1 file changed, 1 insertion(+)