diff mbox series

[1/2] ARM: dts: imx: change the spi-nor tx

Message ID 1629451790-10507-1-git-send-email-haibo.chen@nxp.com
State Accepted
Commit b2a4f4a302b83976ad0d2930abe0f38e6119a144
Headers show
Series [1/2] ARM: dts: imx: change the spi-nor tx | expand

Commit Message

Bough Chen Aug. 20, 2021, 9:29 a.m. UTC 
From: Haibo Chen <haibo.chen@nxp.com>

Before commit 0e30f47232ab5 ("mtd: spi-nor: add support for DTR protocol"),
for all PP command, it only support 1-1-1 mode, no matter the tx setting
in dts. But after the upper commit, the logic change. It will choose
the best mode(fastest mode) which flash device and spi-nor host controller
both support.

Though the spi-nor device on imx6sx-sdb/imx6ul(l/z)-14x14-evk board
do not support PP-1-4-4/PP-1-1-4, but if tx is 4 in dts file, it will also
impact the read mode selection. For the spi-nor device on the upper mentioned
boards, they support read 1-4-4 mode and read 1-1-4 mode according to the
device internal sfdp register. But qspi host controller do not support
read 1-4-4 mode. so need to set the tx to 1, let the common code finally
select read 1-1-4 mode, PP-1-1-1 mode.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
 arch/arm/boot/dts/imx6sx-sdb.dts        | 4 ++--
 arch/arm/boot/dts/imx6ul-14x14-evk.dtsi | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

Comments

Shawn Guo Oct. 4, 2021, 3:25 a.m. UTC | #1 
On Fri, Aug 20, 2021 at 05:29:49PM +0800, haibo.chen@nxp.com wrote:
> From: Haibo Chen <haibo.chen@nxp.com>

> 

> Before commit 0e30f47232ab5 ("mtd: spi-nor: add support for DTR protocol"),

> for all PP command, it only support 1-1-1 mode, no matter the tx setting

> in dts. But after the upper commit, the logic change. It will choose

> the best mode(fastest mode) which flash device and spi-nor host controller

> both support.

> 

> Though the spi-nor device on imx6sx-sdb/imx6ul(l/z)-14x14-evk board

> do not support PP-1-4-4/PP-1-1-4, but if tx is 4 in dts file, it will also

> impact the read mode selection. For the spi-nor device on the upper mentioned

> boards, they support read 1-4-4 mode and read 1-1-4 mode according to the

> device internal sfdp register. But qspi host controller do not support

> read 1-4-4 mode. so need to set the tx to 1, let the common code finally

> select read 1-1-4 mode, PP-1-1-1 mode.

> 

> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>


Applied both, thanks!
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index 5a63ca615722..99f4cf777a38 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -114,7 +114,7 @@ 
 		compatible = "micron,n25q256a", "jedec,spi-nor";
 		spi-max-frequency = <29000000>;
 		spi-rx-bus-width = <4>;
-		spi-tx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
 		reg = <0>;
 	};
 
@@ -124,7 +124,7 @@ 
 		compatible = "micron,n25q256a", "jedec,spi-nor";
 		spi-max-frequency = <29000000>;
 		spi-rx-bus-width = <4>;
-		spi-tx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
 		reg = <2>;
 	};
 };
diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
index 779cc536566d..a3fde3316c73 100644
--- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
+++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
@@ -292,7 +292,7 @@ 
 		compatible = "micron,n25q256a", "jedec,spi-nor";
 		spi-max-frequency = <29000000>;
 		spi-rx-bus-width = <4>;
-		spi-tx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
 		reg = <0>;
 	};
 };